pci-uclass.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #define LOG_CATEGORY UCLASS_PCI
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <pci.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <dm/device-internal.h>
  17. #include <dm/lists.h>
  18. #include <dm/uclass-internal.h>
  19. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  20. #include <asm/fsp/fsp_support.h>
  21. #endif
  22. #include <dt-bindings/pci/pci.h>
  23. #include <linux/delay.h>
  24. #include "pci_internal.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. int pci_get_bus(int busnum, struct udevice **busp)
  27. {
  28. int ret;
  29. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  30. /* Since buses may not be numbered yet try a little harder with bus 0 */
  31. if (ret == -ENODEV) {
  32. ret = uclass_first_device_err(UCLASS_PCI, busp);
  33. if (ret)
  34. return ret;
  35. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  36. }
  37. return ret;
  38. }
  39. struct udevice *pci_get_controller(struct udevice *dev)
  40. {
  41. while (device_is_on_pci_bus(dev))
  42. dev = dev->parent;
  43. return dev;
  44. }
  45. pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
  46. {
  47. struct pci_child_plat *pplat = dev_get_parent_plat(dev);
  48. struct udevice *bus = dev->parent;
  49. /*
  50. * This error indicates that @dev is a device on an unprobed PCI bus.
  51. * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
  52. * will produce a bad BDF>
  53. *
  54. * A common cause of this problem is that this function is called in the
  55. * of_to_plat() method of @dev. Accessing the PCI bus in that
  56. * method is not allowed, since it has not yet been probed. To fix this,
  57. * move that access to the probe() method of @dev instead.
  58. */
  59. if (!device_active(bus))
  60. log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
  61. bus->name);
  62. return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
  63. }
  64. /**
  65. * pci_get_bus_max() - returns the bus number of the last active bus
  66. *
  67. * @return last bus number, or -1 if no active buses
  68. */
  69. static int pci_get_bus_max(void)
  70. {
  71. struct udevice *bus;
  72. struct uclass *uc;
  73. int ret = -1;
  74. ret = uclass_get(UCLASS_PCI, &uc);
  75. uclass_foreach_dev(bus, uc) {
  76. if (dev_seq(bus) > ret)
  77. ret = dev_seq(bus);
  78. }
  79. debug("%s: ret=%d\n", __func__, ret);
  80. return ret;
  81. }
  82. int pci_last_busno(void)
  83. {
  84. return pci_get_bus_max();
  85. }
  86. int pci_get_ff(enum pci_size_t size)
  87. {
  88. switch (size) {
  89. case PCI_SIZE_8:
  90. return 0xff;
  91. case PCI_SIZE_16:
  92. return 0xffff;
  93. default:
  94. return 0xffffffff;
  95. }
  96. }
  97. static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
  98. ofnode *rnode)
  99. {
  100. struct fdt_pci_addr addr;
  101. ofnode node;
  102. int ret;
  103. dev_for_each_subnode(node, bus) {
  104. ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
  105. &addr);
  106. if (ret)
  107. continue;
  108. if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
  109. continue;
  110. *rnode = node;
  111. break;
  112. }
  113. };
  114. int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
  115. struct udevice **devp)
  116. {
  117. struct udevice *dev;
  118. for (device_find_first_child(bus, &dev);
  119. dev;
  120. device_find_next_child(&dev)) {
  121. struct pci_child_plat *pplat;
  122. pplat = dev_get_parent_plat(dev);
  123. if (pplat && pplat->devfn == find_devfn) {
  124. *devp = dev;
  125. return 0;
  126. }
  127. }
  128. return -ENODEV;
  129. }
  130. int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
  131. {
  132. struct udevice *bus;
  133. int ret;
  134. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  135. if (ret)
  136. return ret;
  137. return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
  138. }
  139. static int pci_device_matches_ids(struct udevice *dev,
  140. const struct pci_device_id *ids)
  141. {
  142. struct pci_child_plat *pplat;
  143. int i;
  144. pplat = dev_get_parent_plat(dev);
  145. if (!pplat)
  146. return -EINVAL;
  147. for (i = 0; ids[i].vendor != 0; i++) {
  148. if (pplat->vendor == ids[i].vendor &&
  149. pplat->device == ids[i].device)
  150. return i;
  151. }
  152. return -EINVAL;
  153. }
  154. int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
  155. int *indexp, struct udevice **devp)
  156. {
  157. struct udevice *dev;
  158. /* Scan all devices on this bus */
  159. for (device_find_first_child(bus, &dev);
  160. dev;
  161. device_find_next_child(&dev)) {
  162. if (pci_device_matches_ids(dev, ids) >= 0) {
  163. if ((*indexp)-- <= 0) {
  164. *devp = dev;
  165. return 0;
  166. }
  167. }
  168. }
  169. return -ENODEV;
  170. }
  171. int pci_find_device_id(const struct pci_device_id *ids, int index,
  172. struct udevice **devp)
  173. {
  174. struct udevice *bus;
  175. /* Scan all known buses */
  176. for (uclass_first_device(UCLASS_PCI, &bus);
  177. bus;
  178. uclass_next_device(&bus)) {
  179. if (!pci_bus_find_devices(bus, ids, &index, devp))
  180. return 0;
  181. }
  182. *devp = NULL;
  183. return -ENODEV;
  184. }
  185. static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
  186. unsigned int device, int *indexp,
  187. struct udevice **devp)
  188. {
  189. struct pci_child_plat *pplat;
  190. struct udevice *dev;
  191. for (device_find_first_child(bus, &dev);
  192. dev;
  193. device_find_next_child(&dev)) {
  194. pplat = dev_get_parent_plat(dev);
  195. if (pplat->vendor == vendor && pplat->device == device) {
  196. if (!(*indexp)--) {
  197. *devp = dev;
  198. return 0;
  199. }
  200. }
  201. }
  202. return -ENODEV;
  203. }
  204. int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
  205. struct udevice **devp)
  206. {
  207. struct udevice *bus;
  208. /* Scan all known buses */
  209. for (uclass_first_device(UCLASS_PCI, &bus);
  210. bus;
  211. uclass_next_device(&bus)) {
  212. if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
  213. return device_probe(*devp);
  214. }
  215. *devp = NULL;
  216. return -ENODEV;
  217. }
  218. int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
  219. {
  220. struct udevice *dev;
  221. /* Scan all known buses */
  222. for (pci_find_first_device(&dev);
  223. dev;
  224. pci_find_next_device(&dev)) {
  225. struct pci_child_plat *pplat = dev_get_parent_plat(dev);
  226. if (pplat->class == find_class && !index--) {
  227. *devp = dev;
  228. return device_probe(*devp);
  229. }
  230. }
  231. *devp = NULL;
  232. return -ENODEV;
  233. }
  234. int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
  235. unsigned long value, enum pci_size_t size)
  236. {
  237. struct dm_pci_ops *ops;
  238. ops = pci_get_ops(bus);
  239. if (!ops->write_config)
  240. return -ENOSYS;
  241. return ops->write_config(bus, bdf, offset, value, size);
  242. }
  243. int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
  244. u32 clr, u32 set)
  245. {
  246. ulong val;
  247. int ret;
  248. ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
  249. if (ret)
  250. return ret;
  251. val &= ~clr;
  252. val |= set;
  253. return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
  254. }
  255. int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
  256. enum pci_size_t size)
  257. {
  258. struct udevice *bus;
  259. int ret;
  260. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  261. if (ret)
  262. return ret;
  263. return pci_bus_write_config(bus, bdf, offset, value, size);
  264. }
  265. int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
  266. enum pci_size_t size)
  267. {
  268. struct udevice *bus;
  269. for (bus = dev; device_is_on_pci_bus(bus);)
  270. bus = bus->parent;
  271. return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
  272. size);
  273. }
  274. int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
  275. {
  276. return pci_write_config(bdf, offset, value, PCI_SIZE_32);
  277. }
  278. int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
  279. {
  280. return pci_write_config(bdf, offset, value, PCI_SIZE_16);
  281. }
  282. int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
  283. {
  284. return pci_write_config(bdf, offset, value, PCI_SIZE_8);
  285. }
  286. int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
  287. {
  288. return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
  289. }
  290. int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
  291. {
  292. return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
  293. }
  294. int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
  295. {
  296. return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
  297. }
  298. int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
  299. unsigned long *valuep, enum pci_size_t size)
  300. {
  301. struct dm_pci_ops *ops;
  302. ops = pci_get_ops(bus);
  303. if (!ops->read_config)
  304. return -ENOSYS;
  305. return ops->read_config(bus, bdf, offset, valuep, size);
  306. }
  307. int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
  308. enum pci_size_t size)
  309. {
  310. struct udevice *bus;
  311. int ret;
  312. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  313. if (ret)
  314. return ret;
  315. return pci_bus_read_config(bus, bdf, offset, valuep, size);
  316. }
  317. int dm_pci_read_config(const struct udevice *dev, int offset,
  318. unsigned long *valuep, enum pci_size_t size)
  319. {
  320. const struct udevice *bus;
  321. for (bus = dev; device_is_on_pci_bus(bus);)
  322. bus = bus->parent;
  323. return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
  324. size);
  325. }
  326. int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
  327. {
  328. unsigned long value;
  329. int ret;
  330. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
  331. if (ret)
  332. return ret;
  333. *valuep = value;
  334. return 0;
  335. }
  336. int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
  337. {
  338. unsigned long value;
  339. int ret;
  340. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
  341. if (ret)
  342. return ret;
  343. *valuep = value;
  344. return 0;
  345. }
  346. int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
  347. {
  348. unsigned long value;
  349. int ret;
  350. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
  351. if (ret)
  352. return ret;
  353. *valuep = value;
  354. return 0;
  355. }
  356. int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
  357. {
  358. unsigned long value;
  359. int ret;
  360. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
  361. if (ret)
  362. return ret;
  363. *valuep = value;
  364. return 0;
  365. }
  366. int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
  367. {
  368. unsigned long value;
  369. int ret;
  370. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
  371. if (ret)
  372. return ret;
  373. *valuep = value;
  374. return 0;
  375. }
  376. int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
  377. {
  378. unsigned long value;
  379. int ret;
  380. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
  381. if (ret)
  382. return ret;
  383. *valuep = value;
  384. return 0;
  385. }
  386. int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
  387. {
  388. u8 val;
  389. int ret;
  390. ret = dm_pci_read_config8(dev, offset, &val);
  391. if (ret)
  392. return ret;
  393. val &= ~clr;
  394. val |= set;
  395. return dm_pci_write_config8(dev, offset, val);
  396. }
  397. int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
  398. {
  399. u16 val;
  400. int ret;
  401. ret = dm_pci_read_config16(dev, offset, &val);
  402. if (ret)
  403. return ret;
  404. val &= ~clr;
  405. val |= set;
  406. return dm_pci_write_config16(dev, offset, val);
  407. }
  408. int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
  409. {
  410. u32 val;
  411. int ret;
  412. ret = dm_pci_read_config32(dev, offset, &val);
  413. if (ret)
  414. return ret;
  415. val &= ~clr;
  416. val |= set;
  417. return dm_pci_write_config32(dev, offset, val);
  418. }
  419. static void set_vga_bridge_bits(struct udevice *dev)
  420. {
  421. struct udevice *parent = dev->parent;
  422. u16 bc;
  423. while (dev_seq(parent) != 0) {
  424. dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
  425. bc |= PCI_BRIDGE_CTL_VGA;
  426. dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
  427. parent = parent->parent;
  428. }
  429. }
  430. int pci_auto_config_devices(struct udevice *bus)
  431. {
  432. struct pci_controller *hose = dev_get_uclass_priv(bus);
  433. struct pci_child_plat *pplat;
  434. unsigned int sub_bus;
  435. struct udevice *dev;
  436. int ret;
  437. sub_bus = dev_seq(bus);
  438. debug("%s: start\n", __func__);
  439. pciauto_config_init(hose);
  440. for (ret = device_find_first_child(bus, &dev);
  441. !ret && dev;
  442. ret = device_find_next_child(&dev)) {
  443. unsigned int max_bus;
  444. int ret;
  445. debug("%s: device %s\n", __func__, dev->name);
  446. if (dev_has_ofnode(dev) &&
  447. dev_read_bool(dev, "pci,no-autoconfig"))
  448. continue;
  449. ret = dm_pciauto_config_device(dev);
  450. if (ret < 0)
  451. return log_msg_ret("auto", ret);
  452. max_bus = ret;
  453. sub_bus = max(sub_bus, max_bus);
  454. if (dev_get_parent(dev) == bus)
  455. continue;
  456. pplat = dev_get_parent_plat(dev);
  457. if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
  458. set_vga_bridge_bits(dev);
  459. }
  460. debug("%s: done\n", __func__);
  461. return log_msg_ret("sub", sub_bus);
  462. }
  463. int pci_generic_mmap_write_config(
  464. const struct udevice *bus,
  465. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  466. void **addrp),
  467. pci_dev_t bdf,
  468. uint offset,
  469. ulong value,
  470. enum pci_size_t size)
  471. {
  472. void *address;
  473. if (addr_f(bus, bdf, offset, &address) < 0)
  474. return 0;
  475. switch (size) {
  476. case PCI_SIZE_8:
  477. writeb(value, address);
  478. return 0;
  479. case PCI_SIZE_16:
  480. writew(value, address);
  481. return 0;
  482. case PCI_SIZE_32:
  483. writel(value, address);
  484. return 0;
  485. default:
  486. return -EINVAL;
  487. }
  488. }
  489. int pci_generic_mmap_read_config(
  490. const struct udevice *bus,
  491. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  492. void **addrp),
  493. pci_dev_t bdf,
  494. uint offset,
  495. ulong *valuep,
  496. enum pci_size_t size)
  497. {
  498. void *address;
  499. if (addr_f(bus, bdf, offset, &address) < 0) {
  500. *valuep = pci_get_ff(size);
  501. return 0;
  502. }
  503. switch (size) {
  504. case PCI_SIZE_8:
  505. *valuep = readb(address);
  506. return 0;
  507. case PCI_SIZE_16:
  508. *valuep = readw(address);
  509. return 0;
  510. case PCI_SIZE_32:
  511. *valuep = readl(address);
  512. return 0;
  513. default:
  514. return -EINVAL;
  515. }
  516. }
  517. int dm_pci_hose_probe_bus(struct udevice *bus)
  518. {
  519. int sub_bus;
  520. int ret;
  521. int ea_pos;
  522. u8 reg;
  523. debug("%s\n", __func__);
  524. ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
  525. if (ea_pos) {
  526. dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
  527. &reg);
  528. sub_bus = reg;
  529. } else {
  530. sub_bus = pci_get_bus_max() + 1;
  531. }
  532. debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
  533. dm_pciauto_prescan_setup_bridge(bus, sub_bus);
  534. ret = device_probe(bus);
  535. if (ret) {
  536. debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
  537. ret);
  538. return log_msg_ret("probe", ret);
  539. }
  540. if (!ea_pos)
  541. sub_bus = pci_get_bus_max();
  542. dm_pciauto_postscan_setup_bridge(bus, sub_bus);
  543. return sub_bus;
  544. }
  545. /**
  546. * pci_match_one_device - Tell if a PCI device structure has a matching
  547. * PCI device id structure
  548. * @id: single PCI device id structure to match
  549. * @find: the PCI device id structure to match against
  550. *
  551. * Returns true if the finding pci_device_id structure matched or false if
  552. * there is no match.
  553. */
  554. static bool pci_match_one_id(const struct pci_device_id *id,
  555. const struct pci_device_id *find)
  556. {
  557. if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
  558. (id->device == PCI_ANY_ID || id->device == find->device) &&
  559. (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
  560. (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
  561. !((id->class ^ find->class) & id->class_mask))
  562. return true;
  563. return false;
  564. }
  565. /**
  566. * pci_need_device_pre_reloc() - Check if a device should be bound
  567. *
  568. * This checks a list of vendor/device-ID values indicating devices that should
  569. * be bound before relocation.
  570. *
  571. * @bus: Bus to check
  572. * @vendor: Vendor ID to check
  573. * @device: Device ID to check
  574. * @return true if the vendor/device is in the list, false if not
  575. */
  576. static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
  577. uint device)
  578. {
  579. u32 vendev;
  580. int index;
  581. for (index = 0;
  582. !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
  583. &vendev);
  584. index++) {
  585. if (vendev == PCI_VENDEV(vendor, device))
  586. return true;
  587. }
  588. return false;
  589. }
  590. /**
  591. * pci_find_and_bind_driver() - Find and bind the right PCI driver
  592. *
  593. * This only looks at certain fields in the descriptor.
  594. *
  595. * @parent: Parent bus
  596. * @find_id: Specification of the driver to find
  597. * @bdf: Bus/device/function addreess - see PCI_BDF()
  598. * @devp: Returns a pointer to the device created
  599. * @return 0 if OK, -EPERM if the device is not needed before relocation and
  600. * therefore was not created, other -ve value on error
  601. */
  602. static int pci_find_and_bind_driver(struct udevice *parent,
  603. struct pci_device_id *find_id,
  604. pci_dev_t bdf, struct udevice **devp)
  605. {
  606. struct pci_driver_entry *start, *entry;
  607. ofnode node = ofnode_null();
  608. const char *drv;
  609. int n_ents;
  610. int ret;
  611. char name[30], *str;
  612. bool bridge;
  613. *devp = NULL;
  614. debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
  615. find_id->vendor, find_id->device);
  616. /* Determine optional OF node */
  617. if (ofnode_valid(dev_ofnode(parent)))
  618. pci_dev_find_ofnode(parent, bdf, &node);
  619. if (ofnode_valid(node) && !ofnode_is_available(node)) {
  620. debug("%s: Ignoring disabled device\n", __func__);
  621. return log_msg_ret("dis", -EPERM);
  622. }
  623. start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
  624. n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
  625. for (entry = start; entry != start + n_ents; entry++) {
  626. const struct pci_device_id *id;
  627. struct udevice *dev;
  628. const struct driver *drv;
  629. for (id = entry->match;
  630. id->vendor || id->subvendor || id->class_mask;
  631. id++) {
  632. if (!pci_match_one_id(id, find_id))
  633. continue;
  634. drv = entry->driver;
  635. /*
  636. * In the pre-relocation phase, we only bind devices
  637. * whose driver has the DM_FLAG_PRE_RELOC set, to save
  638. * precious memory space as on some platforms as that
  639. * space is pretty limited (ie: using Cache As RAM).
  640. */
  641. if (!(gd->flags & GD_FLG_RELOC) &&
  642. !(drv->flags & DM_FLAG_PRE_RELOC))
  643. return log_msg_ret("pre", -EPERM);
  644. /*
  645. * We could pass the descriptor to the driver as
  646. * plat (instead of NULL) and allow its bind()
  647. * method to return -ENOENT if it doesn't support this
  648. * device. That way we could continue the search to
  649. * find another driver. For now this doesn't seem
  650. * necesssary, so just bind the first match.
  651. */
  652. ret = device_bind(parent, drv, drv->name, NULL, node,
  653. &dev);
  654. if (ret)
  655. goto error;
  656. debug("%s: Match found: %s\n", __func__, drv->name);
  657. dev->driver_data = id->driver_data;
  658. *devp = dev;
  659. return 0;
  660. }
  661. }
  662. bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
  663. /*
  664. * In the pre-relocation phase, we only bind bridge devices to save
  665. * precious memory space as on some platforms as that space is pretty
  666. * limited (ie: using Cache As RAM).
  667. */
  668. if (!(gd->flags & GD_FLG_RELOC) && !bridge &&
  669. !pci_need_device_pre_reloc(parent, find_id->vendor,
  670. find_id->device))
  671. return log_msg_ret("notbr", -EPERM);
  672. /* Bind a generic driver so that the device can be used */
  673. sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
  674. PCI_FUNC(bdf));
  675. str = strdup(name);
  676. if (!str)
  677. return -ENOMEM;
  678. drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
  679. ret = device_bind_driver_to_node(parent, drv, str, node, devp);
  680. if (ret) {
  681. debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
  682. free(str);
  683. return ret;
  684. }
  685. debug("%s: No match found: bound generic driver instead\n", __func__);
  686. return 0;
  687. error:
  688. debug("%s: No match found: error %d\n", __func__, ret);
  689. return ret;
  690. }
  691. __weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
  692. {
  693. }
  694. int pci_bind_bus_devices(struct udevice *bus)
  695. {
  696. ulong vendor, device;
  697. ulong header_type;
  698. pci_dev_t bdf, end;
  699. bool found_multi;
  700. int ari_off;
  701. int ret;
  702. found_multi = false;
  703. end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
  704. PCI_MAX_PCI_FUNCTIONS - 1);
  705. for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
  706. bdf += PCI_BDF(0, 0, 1)) {
  707. struct pci_child_plat *pplat;
  708. struct udevice *dev;
  709. ulong class;
  710. if (!PCI_FUNC(bdf))
  711. found_multi = false;
  712. if (PCI_FUNC(bdf) && !found_multi)
  713. continue;
  714. /* Check only the first access, we don't expect problems */
  715. ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
  716. PCI_SIZE_16);
  717. if (ret)
  718. goto error;
  719. if (vendor == 0xffff || vendor == 0x0000)
  720. continue;
  721. pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
  722. &header_type, PCI_SIZE_8);
  723. if (!PCI_FUNC(bdf))
  724. found_multi = header_type & 0x80;
  725. debug("%s: bus %d/%s: found device %x, function %d", __func__,
  726. dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  727. pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
  728. PCI_SIZE_16);
  729. pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
  730. PCI_SIZE_32);
  731. class >>= 8;
  732. /* Find this device in the device tree */
  733. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  734. debug(": find ret=%d\n", ret);
  735. /* If nothing in the device tree, bind a device */
  736. if (ret == -ENODEV) {
  737. struct pci_device_id find_id;
  738. ulong val;
  739. memset(&find_id, '\0', sizeof(find_id));
  740. find_id.vendor = vendor;
  741. find_id.device = device;
  742. find_id.class = class;
  743. if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
  744. pci_bus_read_config(bus, bdf,
  745. PCI_SUBSYSTEM_VENDOR_ID,
  746. &val, PCI_SIZE_32);
  747. find_id.subvendor = val & 0xffff;
  748. find_id.subdevice = val >> 16;
  749. }
  750. ret = pci_find_and_bind_driver(bus, &find_id, bdf,
  751. &dev);
  752. }
  753. if (ret == -EPERM)
  754. continue;
  755. else if (ret)
  756. return ret;
  757. /* Update the platform data */
  758. pplat = dev_get_parent_plat(dev);
  759. pplat->devfn = PCI_MASK_BUS(bdf);
  760. pplat->vendor = vendor;
  761. pplat->device = device;
  762. pplat->class = class;
  763. if (IS_ENABLED(CONFIG_PCI_ARID)) {
  764. ari_off = dm_pci_find_ext_capability(dev,
  765. PCI_EXT_CAP_ID_ARI);
  766. if (ari_off) {
  767. u16 ari_cap;
  768. /*
  769. * Read Next Function number in ARI Cap
  770. * Register
  771. */
  772. dm_pci_read_config16(dev, ari_off + 4,
  773. &ari_cap);
  774. /*
  775. * Update next scan on this function number,
  776. * subtract 1 in BDF to satisfy loop increment.
  777. */
  778. if (ari_cap & 0xff00) {
  779. bdf = PCI_BDF(PCI_BUS(bdf),
  780. PCI_DEV(ari_cap),
  781. PCI_FUNC(ari_cap));
  782. bdf = bdf - 0x100;
  783. }
  784. }
  785. }
  786. board_pci_fixup_dev(bus, dev);
  787. }
  788. return 0;
  789. error:
  790. printf("Cannot read bus configuration: %d\n", ret);
  791. return ret;
  792. }
  793. static void decode_regions(struct pci_controller *hose, ofnode parent_node,
  794. ofnode node)
  795. {
  796. int pci_addr_cells, addr_cells, size_cells;
  797. int cells_per_record;
  798. struct bd_info *bd;
  799. const u32 *prop;
  800. int max_regions;
  801. int len;
  802. int i;
  803. prop = ofnode_get_property(node, "ranges", &len);
  804. if (!prop) {
  805. debug("%s: Cannot decode regions\n", __func__);
  806. return;
  807. }
  808. pci_addr_cells = ofnode_read_simple_addr_cells(node);
  809. addr_cells = ofnode_read_simple_addr_cells(parent_node);
  810. size_cells = ofnode_read_simple_size_cells(node);
  811. /* PCI addresses are always 3-cells */
  812. len /= sizeof(u32);
  813. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  814. hose->region_count = 0;
  815. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  816. cells_per_record);
  817. /* Dynamically allocate the regions array */
  818. max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
  819. hose->regions = (struct pci_region *)
  820. calloc(1, max_regions * sizeof(struct pci_region));
  821. for (i = 0; i < max_regions; i++, len -= cells_per_record) {
  822. u64 pci_addr, addr, size;
  823. int space_code;
  824. u32 flags;
  825. int type;
  826. int pos;
  827. if (len < cells_per_record)
  828. break;
  829. flags = fdt32_to_cpu(prop[0]);
  830. space_code = (flags >> 24) & 3;
  831. pci_addr = fdtdec_get_number(prop + 1, 2);
  832. prop += pci_addr_cells;
  833. addr = fdtdec_get_number(prop, addr_cells);
  834. prop += addr_cells;
  835. size = fdtdec_get_number(prop, size_cells);
  836. prop += size_cells;
  837. debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
  838. __func__, hose->region_count, pci_addr, addr, size, space_code);
  839. if (space_code & 2) {
  840. type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
  841. PCI_REGION_MEM;
  842. } else if (space_code & 1) {
  843. type = PCI_REGION_IO;
  844. } else {
  845. continue;
  846. }
  847. if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
  848. type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
  849. debug(" - beyond the 32-bit boundary, ignoring\n");
  850. continue;
  851. }
  852. pos = -1;
  853. if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
  854. for (i = 0; i < hose->region_count; i++) {
  855. if (hose->regions[i].flags == type)
  856. pos = i;
  857. }
  858. }
  859. if (pos == -1)
  860. pos = hose->region_count++;
  861. debug(" - type=%d, pos=%d\n", type, pos);
  862. pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
  863. }
  864. /* Add a region for our local memory */
  865. bd = gd->bd;
  866. if (!bd)
  867. return;
  868. for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
  869. if (bd->bi_dram[i].size) {
  870. phys_addr_t start = bd->bi_dram[i].start;
  871. if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
  872. start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
  873. pci_set_region(hose->regions + hose->region_count++,
  874. start, start, bd->bi_dram[i].size,
  875. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  876. }
  877. }
  878. return;
  879. }
  880. static int pci_uclass_pre_probe(struct udevice *bus)
  881. {
  882. struct pci_controller *hose;
  883. struct uclass *uc;
  884. int ret;
  885. debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
  886. bus->parent->name);
  887. hose = dev_get_uclass_priv(bus);
  888. /*
  889. * Set the sequence number, if device_bind() doesn't. We want control
  890. * of this so that numbers are allocated as devices are probed. That
  891. * ensures that sub-bus numbered is correct (sub-buses must get numbers
  892. * higher than their parents)
  893. */
  894. if (dev_seq(bus) == -1) {
  895. ret = uclass_get(UCLASS_PCI, &uc);
  896. if (ret)
  897. return ret;
  898. bus->seq_ = uclass_find_next_free_seq(uc);
  899. }
  900. /* For bridges, use the top-level PCI controller */
  901. if (!device_is_on_pci_bus(bus)) {
  902. hose->ctlr = bus;
  903. decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
  904. } else {
  905. struct pci_controller *parent_hose;
  906. parent_hose = dev_get_uclass_priv(bus->parent);
  907. hose->ctlr = parent_hose->bus;
  908. }
  909. hose->bus = bus;
  910. hose->first_busno = dev_seq(bus);
  911. hose->last_busno = dev_seq(bus);
  912. if (dev_has_ofnode(bus)) {
  913. hose->skip_auto_config_until_reloc =
  914. dev_read_bool(bus,
  915. "u-boot,skip-auto-config-until-reloc");
  916. }
  917. return 0;
  918. }
  919. static int pci_uclass_post_probe(struct udevice *bus)
  920. {
  921. struct pci_controller *hose = dev_get_uclass_priv(bus);
  922. int ret;
  923. debug("%s: probing bus %d\n", __func__, dev_seq(bus));
  924. ret = pci_bind_bus_devices(bus);
  925. if (ret)
  926. return log_msg_ret("bind", ret);
  927. if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
  928. (!hose->skip_auto_config_until_reloc ||
  929. (gd->flags & GD_FLG_RELOC))) {
  930. ret = pci_auto_config_devices(bus);
  931. if (ret < 0)
  932. return log_msg_ret("cfg", ret);
  933. }
  934. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  935. /*
  936. * Per Intel FSP specification, we should call FSP notify API to
  937. * inform FSP that PCI enumeration has been done so that FSP will
  938. * do any necessary initialization as required by the chipset's
  939. * BIOS Writer's Guide (BWG).
  940. *
  941. * Unfortunately we have to put this call here as with driver model,
  942. * the enumeration is all done on a lazy basis as needed, so until
  943. * something is touched on PCI it won't happen.
  944. *
  945. * Note we only call this 1) after U-Boot is relocated, and 2)
  946. * root bus has finished probing.
  947. */
  948. if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
  949. ret = fsp_init_phase_pci();
  950. if (ret)
  951. return log_msg_ret("fsp", ret);
  952. }
  953. #endif
  954. return 0;
  955. }
  956. static int pci_uclass_child_post_bind(struct udevice *dev)
  957. {
  958. struct pci_child_plat *pplat;
  959. if (!dev_has_ofnode(dev))
  960. return 0;
  961. pplat = dev_get_parent_plat(dev);
  962. /* Extract vendor id and device id if available */
  963. ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
  964. /* Extract the devfn from fdt_pci_addr */
  965. pplat->devfn = pci_get_devfn(dev);
  966. return 0;
  967. }
  968. static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
  969. uint offset, ulong *valuep,
  970. enum pci_size_t size)
  971. {
  972. struct pci_controller *hose = dev_get_uclass_priv(bus);
  973. return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
  974. }
  975. static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
  976. uint offset, ulong value,
  977. enum pci_size_t size)
  978. {
  979. struct pci_controller *hose = dev_get_uclass_priv(bus);
  980. return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
  981. }
  982. static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
  983. {
  984. struct udevice *dev;
  985. int ret = 0;
  986. /*
  987. * Scan through all the PCI controllers. On x86 there will only be one
  988. * but that is not necessarily true on other hardware.
  989. */
  990. do {
  991. device_find_first_child(bus, &dev);
  992. if (dev) {
  993. *devp = dev;
  994. return 0;
  995. }
  996. ret = uclass_next_device(&bus);
  997. if (ret)
  998. return ret;
  999. } while (bus);
  1000. return 0;
  1001. }
  1002. int pci_find_next_device(struct udevice **devp)
  1003. {
  1004. struct udevice *child = *devp;
  1005. struct udevice *bus = child->parent;
  1006. int ret;
  1007. /* First try all the siblings */
  1008. *devp = NULL;
  1009. while (child) {
  1010. device_find_next_child(&child);
  1011. if (child) {
  1012. *devp = child;
  1013. return 0;
  1014. }
  1015. }
  1016. /* We ran out of siblings. Try the next bus */
  1017. ret = uclass_next_device(&bus);
  1018. if (ret)
  1019. return ret;
  1020. return bus ? skip_to_next_device(bus, devp) : 0;
  1021. }
  1022. int pci_find_first_device(struct udevice **devp)
  1023. {
  1024. struct udevice *bus;
  1025. int ret;
  1026. *devp = NULL;
  1027. ret = uclass_first_device(UCLASS_PCI, &bus);
  1028. if (ret)
  1029. return ret;
  1030. return skip_to_next_device(bus, devp);
  1031. }
  1032. ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
  1033. {
  1034. switch (size) {
  1035. case PCI_SIZE_8:
  1036. return (value >> ((offset & 3) * 8)) & 0xff;
  1037. case PCI_SIZE_16:
  1038. return (value >> ((offset & 2) * 8)) & 0xffff;
  1039. default:
  1040. return value;
  1041. }
  1042. }
  1043. ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
  1044. enum pci_size_t size)
  1045. {
  1046. uint off_mask;
  1047. uint val_mask, shift;
  1048. ulong ldata, mask;
  1049. switch (size) {
  1050. case PCI_SIZE_8:
  1051. off_mask = 3;
  1052. val_mask = 0xff;
  1053. break;
  1054. case PCI_SIZE_16:
  1055. off_mask = 2;
  1056. val_mask = 0xffff;
  1057. break;
  1058. default:
  1059. return value;
  1060. }
  1061. shift = (offset & off_mask) * 8;
  1062. ldata = (value & val_mask) << shift;
  1063. mask = val_mask << shift;
  1064. value = (old & ~mask) | ldata;
  1065. return value;
  1066. }
  1067. int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
  1068. {
  1069. int pci_addr_cells, addr_cells, size_cells;
  1070. int cells_per_record;
  1071. const u32 *prop;
  1072. int len;
  1073. int i = 0;
  1074. prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
  1075. if (!prop) {
  1076. log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
  1077. dev->name);
  1078. return -EINVAL;
  1079. }
  1080. pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
  1081. addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
  1082. size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
  1083. /* PCI addresses are always 3-cells */
  1084. len /= sizeof(u32);
  1085. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  1086. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  1087. cells_per_record);
  1088. while (len) {
  1089. memp->bus_start = fdtdec_get_number(prop + 1, 2);
  1090. prop += pci_addr_cells;
  1091. memp->phys_start = fdtdec_get_number(prop, addr_cells);
  1092. prop += addr_cells;
  1093. memp->size = fdtdec_get_number(prop, size_cells);
  1094. prop += size_cells;
  1095. if (i == index)
  1096. return 0;
  1097. i++;
  1098. len -= cells_per_record;
  1099. }
  1100. return -EINVAL;
  1101. }
  1102. int pci_get_regions(struct udevice *dev, struct pci_region **iop,
  1103. struct pci_region **memp, struct pci_region **prefp)
  1104. {
  1105. struct udevice *bus = pci_get_controller(dev);
  1106. struct pci_controller *hose = dev_get_uclass_priv(bus);
  1107. int i;
  1108. *iop = NULL;
  1109. *memp = NULL;
  1110. *prefp = NULL;
  1111. for (i = 0; i < hose->region_count; i++) {
  1112. switch (hose->regions[i].flags) {
  1113. case PCI_REGION_IO:
  1114. if (!*iop || (*iop)->size < hose->regions[i].size)
  1115. *iop = hose->regions + i;
  1116. break;
  1117. case PCI_REGION_MEM:
  1118. if (!*memp || (*memp)->size < hose->regions[i].size)
  1119. *memp = hose->regions + i;
  1120. break;
  1121. case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
  1122. if (!*prefp || (*prefp)->size < hose->regions[i].size)
  1123. *prefp = hose->regions + i;
  1124. break;
  1125. }
  1126. }
  1127. return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
  1128. }
  1129. u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
  1130. {
  1131. u32 addr;
  1132. int bar;
  1133. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1134. dm_pci_read_config32(dev, bar, &addr);
  1135. /*
  1136. * If we get an invalid address, return this so that comparisons with
  1137. * FDT_ADDR_T_NONE work correctly
  1138. */
  1139. if (addr == 0xffffffff)
  1140. return addr;
  1141. else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
  1142. return addr & PCI_BASE_ADDRESS_IO_MASK;
  1143. else
  1144. return addr & PCI_BASE_ADDRESS_MEM_MASK;
  1145. }
  1146. void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
  1147. {
  1148. int bar;
  1149. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1150. dm_pci_write_config32(dev, bar, addr);
  1151. }
  1152. static int _dm_pci_bus_to_phys(struct udevice *ctlr,
  1153. pci_addr_t bus_addr, unsigned long flags,
  1154. unsigned long skip_mask, phys_addr_t *pa)
  1155. {
  1156. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  1157. struct pci_region *res;
  1158. int i;
  1159. if (hose->region_count == 0) {
  1160. *pa = bus_addr;
  1161. return 0;
  1162. }
  1163. for (i = 0; i < hose->region_count; i++) {
  1164. res = &hose->regions[i];
  1165. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1166. continue;
  1167. if (res->flags & skip_mask)
  1168. continue;
  1169. if (bus_addr >= res->bus_start &&
  1170. (bus_addr - res->bus_start) < res->size) {
  1171. *pa = (bus_addr - res->bus_start + res->phys_start);
  1172. return 0;
  1173. }
  1174. }
  1175. return 1;
  1176. }
  1177. phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
  1178. unsigned long flags)
  1179. {
  1180. phys_addr_t phys_addr = 0;
  1181. struct udevice *ctlr;
  1182. int ret;
  1183. /* The root controller has the region information */
  1184. ctlr = pci_get_controller(dev);
  1185. /*
  1186. * if PCI_REGION_MEM is set we do a two pass search with preference
  1187. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1188. */
  1189. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1190. ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
  1191. flags, PCI_REGION_SYS_MEMORY,
  1192. &phys_addr);
  1193. if (!ret)
  1194. return phys_addr;
  1195. }
  1196. ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
  1197. if (ret)
  1198. puts("pci_hose_bus_to_phys: invalid physical address\n");
  1199. return phys_addr;
  1200. }
  1201. int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1202. unsigned long flags, unsigned long skip_mask,
  1203. pci_addr_t *ba)
  1204. {
  1205. struct pci_region *res;
  1206. struct udevice *ctlr;
  1207. pci_addr_t bus_addr;
  1208. int i;
  1209. struct pci_controller *hose;
  1210. /* The root controller has the region information */
  1211. ctlr = pci_get_controller(dev);
  1212. hose = dev_get_uclass_priv(ctlr);
  1213. if (hose->region_count == 0) {
  1214. *ba = phys_addr;
  1215. return 0;
  1216. }
  1217. for (i = 0; i < hose->region_count; i++) {
  1218. res = &hose->regions[i];
  1219. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1220. continue;
  1221. if (res->flags & skip_mask)
  1222. continue;
  1223. bus_addr = phys_addr - res->phys_start + res->bus_start;
  1224. if (bus_addr >= res->bus_start &&
  1225. (bus_addr - res->bus_start) < res->size) {
  1226. *ba = bus_addr;
  1227. return 0;
  1228. }
  1229. }
  1230. return 1;
  1231. }
  1232. pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1233. unsigned long flags)
  1234. {
  1235. pci_addr_t bus_addr = 0;
  1236. int ret;
  1237. /*
  1238. * if PCI_REGION_MEM is set we do a two pass search with preference
  1239. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1240. */
  1241. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1242. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
  1243. PCI_REGION_SYS_MEMORY, &bus_addr);
  1244. if (!ret)
  1245. return bus_addr;
  1246. }
  1247. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
  1248. if (ret)
  1249. puts("pci_hose_phys_to_bus: invalid physical address\n");
  1250. return bus_addr;
  1251. }
  1252. static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
  1253. struct pci_child_plat *pdata)
  1254. {
  1255. phys_addr_t addr = 0;
  1256. /*
  1257. * In the case of a Virtual Function device using BAR
  1258. * base and size, add offset for VFn BAR(1, 2, 3...n)
  1259. */
  1260. if (pdata->is_virtfn) {
  1261. size_t sz;
  1262. u32 ea_entry;
  1263. /* MaxOffset, 1st DW */
  1264. dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
  1265. sz = ea_entry & PCI_EA_FIELD_MASK;
  1266. /* Fill up lower 2 bits */
  1267. sz |= (~PCI_EA_FIELD_MASK);
  1268. if (ea_entry & PCI_EA_IS_64) {
  1269. /* MaxOffset 2nd DW */
  1270. dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
  1271. sz |= ((u64)ea_entry) << 32;
  1272. }
  1273. addr = (pdata->virtid - 1) * (sz + 1);
  1274. }
  1275. return addr;
  1276. }
  1277. static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
  1278. int ea_off, struct pci_child_plat *pdata)
  1279. {
  1280. int ea_cnt, i, entry_size;
  1281. int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
  1282. u32 ea_entry;
  1283. phys_addr_t addr;
  1284. if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
  1285. /*
  1286. * In the case of a Virtual Function device, device is
  1287. * Physical function, so pdata will point to required VF
  1288. * specific data.
  1289. */
  1290. if (pdata->is_virtfn)
  1291. bar_id += PCI_EA_BEI_VF_BAR0;
  1292. }
  1293. /* EA capability structure header */
  1294. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1295. ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
  1296. ea_off += PCI_EA_FIRST_ENT;
  1297. for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
  1298. /* Entry header */
  1299. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1300. entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
  1301. if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
  1302. continue;
  1303. /* Base address, 1st DW */
  1304. dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
  1305. addr = ea_entry & PCI_EA_FIELD_MASK;
  1306. if (ea_entry & PCI_EA_IS_64) {
  1307. /* Base address, 2nd DW, skip over 4B MaxOffset */
  1308. dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
  1309. addr |= ((u64)ea_entry) << 32;
  1310. }
  1311. if (IS_ENABLED(CONFIG_PCI_SRIOV))
  1312. addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
  1313. /* size ignored for now */
  1314. return map_physmem(addr, 0, flags);
  1315. }
  1316. return 0;
  1317. }
  1318. void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
  1319. {
  1320. struct pci_child_plat *pdata = dev_get_parent_plat(dev);
  1321. struct udevice *udev = dev;
  1322. pci_addr_t pci_bus_addr;
  1323. u32 bar_response;
  1324. int ea_off;
  1325. if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
  1326. /*
  1327. * In case of Virtual Function devices, use PF udevice
  1328. * as EA capability is defined in Physical Function
  1329. */
  1330. if (pdata->is_virtfn)
  1331. udev = pdata->pfdev;
  1332. }
  1333. /*
  1334. * if the function supports Enhanced Allocation use that instead of
  1335. * BARs
  1336. * Incase of virtual functions, pdata will help read VF BEI
  1337. * and EA entry size.
  1338. */
  1339. ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
  1340. if (ea_off)
  1341. return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
  1342. /* read BAR address */
  1343. dm_pci_read_config32(udev, bar, &bar_response);
  1344. pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
  1345. /*
  1346. * Pass "0" as the length argument to pci_bus_to_virt. The arg
  1347. * isn't actually used on any platform because U-Boot assumes a static
  1348. * linear mapping. In the future, this could read the BAR size
  1349. * and pass that as the size if needed.
  1350. */
  1351. return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
  1352. }
  1353. static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
  1354. {
  1355. int ttl = PCI_FIND_CAP_TTL;
  1356. u8 id;
  1357. u16 ent;
  1358. dm_pci_read_config8(dev, pos, &pos);
  1359. while (ttl--) {
  1360. if (pos < PCI_STD_HEADER_SIZEOF)
  1361. break;
  1362. pos &= ~3;
  1363. dm_pci_read_config16(dev, pos, &ent);
  1364. id = ent & 0xff;
  1365. if (id == 0xff)
  1366. break;
  1367. if (id == cap)
  1368. return pos;
  1369. pos = (ent >> 8);
  1370. }
  1371. return 0;
  1372. }
  1373. int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
  1374. {
  1375. return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
  1376. cap);
  1377. }
  1378. int dm_pci_find_capability(struct udevice *dev, int cap)
  1379. {
  1380. u16 status;
  1381. u8 header_type;
  1382. u8 pos;
  1383. dm_pci_read_config16(dev, PCI_STATUS, &status);
  1384. if (!(status & PCI_STATUS_CAP_LIST))
  1385. return 0;
  1386. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  1387. if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
  1388. pos = PCI_CB_CAPABILITY_LIST;
  1389. else
  1390. pos = PCI_CAPABILITY_LIST;
  1391. return _dm_pci_find_next_capability(dev, pos, cap);
  1392. }
  1393. int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
  1394. {
  1395. u32 header;
  1396. int ttl;
  1397. int pos = PCI_CFG_SPACE_SIZE;
  1398. /* minimum 8 bytes per capability */
  1399. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  1400. if (start)
  1401. pos = start;
  1402. dm_pci_read_config32(dev, pos, &header);
  1403. /*
  1404. * If we have no capabilities, this is indicated by cap ID,
  1405. * cap version and next pointer all being 0.
  1406. */
  1407. if (header == 0)
  1408. return 0;
  1409. while (ttl--) {
  1410. if (PCI_EXT_CAP_ID(header) == cap)
  1411. return pos;
  1412. pos = PCI_EXT_CAP_NEXT(header);
  1413. if (pos < PCI_CFG_SPACE_SIZE)
  1414. break;
  1415. dm_pci_read_config32(dev, pos, &header);
  1416. }
  1417. return 0;
  1418. }
  1419. int dm_pci_find_ext_capability(struct udevice *dev, int cap)
  1420. {
  1421. return dm_pci_find_next_ext_capability(dev, 0, cap);
  1422. }
  1423. int dm_pci_flr(struct udevice *dev)
  1424. {
  1425. int pcie_off;
  1426. u32 cap;
  1427. /* look for PCI Express Capability */
  1428. pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
  1429. if (!pcie_off)
  1430. return -ENOENT;
  1431. /* check FLR capability */
  1432. dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
  1433. if (!(cap & PCI_EXP_DEVCAP_FLR))
  1434. return -ENOENT;
  1435. dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
  1436. PCI_EXP_DEVCTL_BCR_FLR);
  1437. /* wait 100ms, per PCI spec */
  1438. mdelay(100);
  1439. return 0;
  1440. }
  1441. #if defined(CONFIG_PCI_SRIOV)
  1442. int pci_sriov_init(struct udevice *pdev, int vf_en)
  1443. {
  1444. u16 vendor, device;
  1445. struct udevice *bus;
  1446. struct udevice *dev;
  1447. pci_dev_t bdf;
  1448. u16 ctrl;
  1449. u16 num_vfs;
  1450. u16 total_vf;
  1451. u16 vf_offset;
  1452. u16 vf_stride;
  1453. int vf, ret;
  1454. int pos;
  1455. pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  1456. if (!pos) {
  1457. debug("Error: SRIOV capability not found\n");
  1458. return -ENOENT;
  1459. }
  1460. dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
  1461. dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
  1462. if (vf_en > total_vf)
  1463. vf_en = total_vf;
  1464. dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
  1465. ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
  1466. dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
  1467. dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
  1468. if (num_vfs > vf_en)
  1469. num_vfs = vf_en;
  1470. dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
  1471. dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
  1472. dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
  1473. dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
  1474. bdf = dm_pci_get_bdf(pdev);
  1475. pci_get_bus(PCI_BUS(bdf), &bus);
  1476. if (!bus)
  1477. return -ENODEV;
  1478. bdf += PCI_BDF(0, 0, vf_offset);
  1479. for (vf = 0; vf < num_vfs; vf++) {
  1480. struct pci_child_plat *pplat;
  1481. ulong class;
  1482. pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
  1483. &class, PCI_SIZE_16);
  1484. debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
  1485. dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  1486. /* Find this device in the device tree */
  1487. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  1488. if (ret == -ENODEV) {
  1489. struct pci_device_id find_id;
  1490. memset(&find_id, '\0', sizeof(find_id));
  1491. find_id.vendor = vendor;
  1492. find_id.device = device;
  1493. find_id.class = class;
  1494. ret = pci_find_and_bind_driver(bus, &find_id,
  1495. bdf, &dev);
  1496. if (ret)
  1497. return ret;
  1498. }
  1499. /* Update the platform data */
  1500. pplat = dev_get_parent_plat(dev);
  1501. pplat->devfn = PCI_MASK_BUS(bdf);
  1502. pplat->vendor = vendor;
  1503. pplat->device = device;
  1504. pplat->class = class;
  1505. pplat->is_virtfn = true;
  1506. pplat->pfdev = pdev;
  1507. pplat->virtid = vf * vf_stride + vf_offset;
  1508. debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
  1509. __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
  1510. PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
  1511. bdf += PCI_BDF(0, 0, vf_stride);
  1512. }
  1513. return 0;
  1514. }
  1515. int pci_sriov_get_totalvfs(struct udevice *pdev)
  1516. {
  1517. u16 total_vf;
  1518. int pos;
  1519. pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  1520. if (!pos) {
  1521. debug("Error: SRIOV capability not found\n");
  1522. return -ENOENT;
  1523. }
  1524. dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
  1525. return total_vf;
  1526. }
  1527. #endif /* SRIOV */
  1528. UCLASS_DRIVER(pci) = {
  1529. .id = UCLASS_PCI,
  1530. .name = "pci",
  1531. .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
  1532. .post_bind = dm_scan_fdt_dev,
  1533. .pre_probe = pci_uclass_pre_probe,
  1534. .post_probe = pci_uclass_post_probe,
  1535. .child_post_bind = pci_uclass_child_post_bind,
  1536. .per_device_auto = sizeof(struct pci_controller),
  1537. .per_child_plat_auto = sizeof(struct pci_child_plat),
  1538. };
  1539. static const struct dm_pci_ops pci_bridge_ops = {
  1540. .read_config = pci_bridge_read_config,
  1541. .write_config = pci_bridge_write_config,
  1542. };
  1543. static const struct udevice_id pci_bridge_ids[] = {
  1544. { .compatible = "pci-bridge" },
  1545. { }
  1546. };
  1547. U_BOOT_DRIVER(pci_bridge_drv) = {
  1548. .name = "pci_bridge_drv",
  1549. .id = UCLASS_PCI,
  1550. .of_match = pci_bridge_ids,
  1551. .ops = &pci_bridge_ops,
  1552. };
  1553. UCLASS_DRIVER(pci_generic) = {
  1554. .id = UCLASS_PCI_GENERIC,
  1555. .name = "pci_generic",
  1556. };
  1557. static const struct udevice_id pci_generic_ids[] = {
  1558. { .compatible = "pci-generic" },
  1559. { }
  1560. };
  1561. U_BOOT_DRIVER(pci_generic_drv) = {
  1562. .name = "pci_generic_drv",
  1563. .id = UCLASS_PCI_GENERIC,
  1564. .of_match = pci_generic_ids,
  1565. };
  1566. int pci_init(void)
  1567. {
  1568. struct udevice *bus;
  1569. /*
  1570. * Enumerate all known controller devices. Enumeration has the side-
  1571. * effect of probing them, so PCIe devices will be enumerated too.
  1572. */
  1573. for (uclass_first_device_check(UCLASS_PCI, &bus);
  1574. bus;
  1575. uclass_next_device_check(&bus)) {
  1576. ;
  1577. }
  1578. return 0;
  1579. }