pci-rcar-gen3.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas RCar Gen3 PCIEC driver
  4. *
  5. * Copyright (C) 2018-2019 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Based on Linux PCIe driver for Renesas R-Car SoCs
  8. * Copyright (C) 2014 Renesas Electronics Europe Ltd
  9. *
  10. * Based on:
  11. * arch/sh/drivers/pci/pcie-sh7786.c
  12. * arch/sh/drivers/pci/ops-sh7786.c
  13. * Copyright (C) 2009 - 2011 Paul Mundt
  14. *
  15. * Author: Phil Edworthy <phil.edworthy@renesas.com>
  16. */
  17. #include <common.h>
  18. #include <asm/io.h>
  19. #include <clk.h>
  20. #include <dm.h>
  21. #include <errno.h>
  22. #include <pci.h>
  23. #include <wait_bit.h>
  24. #include <linux/bitops.h>
  25. #include <linux/log2.h>
  26. #define PCIECAR 0x000010
  27. #define PCIECCTLR 0x000018
  28. #define CONFIG_SEND_ENABLE BIT(31)
  29. #define TYPE0 (0 << 8)
  30. #define TYPE1 BIT(8)
  31. #define PCIECDR 0x000020
  32. #define PCIEMSR 0x000028
  33. #define PCIEINTXR 0x000400
  34. #define PCIEPHYSR 0x0007f0
  35. #define PHYRDY BIT(0)
  36. #define PCIEMSITXR 0x000840
  37. /* Transfer control */
  38. #define PCIETCTLR 0x02000
  39. #define CFINIT 1
  40. #define PCIETSTR 0x02004
  41. #define DATA_LINK_ACTIVE 1
  42. #define PCIEERRFR 0x02020
  43. #define UNSUPPORTED_REQUEST BIT(4)
  44. #define PCIEMSIFR 0x02044
  45. #define PCIEMSIALR 0x02048
  46. #define MSIFE 1
  47. #define PCIEMSIAUR 0x0204c
  48. #define PCIEMSIIER 0x02050
  49. /* root port address */
  50. #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
  51. /* local address reg & mask */
  52. #define PCIELAR(x) (0x02200 + ((x) * 0x20))
  53. #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
  54. #define LAM_PREFETCH BIT(3)
  55. #define LAM_64BIT BIT(2)
  56. #define LAR_ENABLE BIT(1)
  57. /* PCIe address reg & mask */
  58. #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
  59. #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
  60. #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
  61. #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
  62. #define PAR_ENABLE BIT(31)
  63. #define IO_SPACE BIT(8)
  64. /* Configuration */
  65. #define PCICONF(x) (0x010000 + ((x) * 0x4))
  66. #define PMCAP(x) (0x010040 + ((x) * 0x4))
  67. #define EXPCAP(x) (0x010070 + ((x) * 0x4))
  68. #define VCCAP(x) (0x010100 + ((x) * 0x4))
  69. /* link layer */
  70. #define IDSETR1 0x011004
  71. #define TLCTLR 0x011048
  72. #define MACSR 0x011054
  73. #define SPCHGFIN BIT(4)
  74. #define SPCHGFAIL BIT(6)
  75. #define SPCHGSUC BIT(7)
  76. #define LINK_SPEED (0xf << 16)
  77. #define LINK_SPEED_2_5GTS (1 << 16)
  78. #define LINK_SPEED_5_0GTS (2 << 16)
  79. #define MACCTLR 0x011058
  80. #define SPEED_CHANGE BIT(24)
  81. #define SCRAMBLE_DISABLE BIT(27)
  82. #define MACS2R 0x011078
  83. #define MACCGSPSETR 0x011084
  84. #define SPCNGRSN BIT(31)
  85. /* R-Car H1 PHY */
  86. #define H1_PCIEPHYADRR 0x04000c
  87. #define WRITE_CMD BIT(16)
  88. #define PHY_ACK BIT(24)
  89. #define RATE_POS 12
  90. #define LANE_POS 8
  91. #define ADR_POS 0
  92. #define H1_PCIEPHYDOUTR 0x040014
  93. /* R-Car Gen2 PHY */
  94. #define GEN2_PCIEPHYADDR 0x780
  95. #define GEN2_PCIEPHYDATA 0x784
  96. #define GEN2_PCIEPHYCTRL 0x78c
  97. #define INT_PCI_MSI_NR 32
  98. #define RCONF(x) (PCICONF(0) + (x))
  99. #define RPMCAP(x) (PMCAP(0) + (x))
  100. #define REXPCAP(x) (EXPCAP(0) + (x))
  101. #define RVCCAP(x) (VCCAP(0) + (x))
  102. #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
  103. #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
  104. #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
  105. #define RCAR_PCI_MAX_RESOURCES 4
  106. #define MAX_NR_INBOUND_MAPS 6
  107. enum {
  108. RCAR_PCI_ACCESS_READ,
  109. RCAR_PCI_ACCESS_WRITE,
  110. };
  111. struct rcar_gen3_pcie_priv {
  112. fdt_addr_t regs;
  113. };
  114. static void rcar_rmw32(struct udevice *dev, int where, u32 mask, u32 data)
  115. {
  116. struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
  117. int shift = 8 * (where & 3);
  118. clrsetbits_le32(priv->regs + (where & ~3),
  119. mask << shift, data << shift);
  120. }
  121. static u32 rcar_read_conf(const struct udevice *dev, int where)
  122. {
  123. struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
  124. int shift = 8 * (where & 3);
  125. return readl(priv->regs + (where & ~3)) >> shift;
  126. }
  127. static int rcar_pcie_config_access(const struct udevice *udev,
  128. unsigned char access_type,
  129. pci_dev_t bdf, int where, ulong *data)
  130. {
  131. struct rcar_gen3_pcie_priv *priv = dev_get_plat(udev);
  132. u32 reg = where & ~3;
  133. /* Root bus */
  134. if (PCI_DEV(bdf) == 0) {
  135. if (access_type == RCAR_PCI_ACCESS_READ)
  136. *data = readl(priv->regs + PCICONF(where / 4));
  137. else
  138. writel(*data, priv->regs + PCICONF(where / 4));
  139. return 0;
  140. }
  141. /* Clear errors */
  142. clrbits_le32(priv->regs + PCIEERRFR, 0);
  143. /* Set the PIO address */
  144. writel((bdf << 8) | reg, priv->regs + PCIECAR);
  145. /* Enable the configuration access */
  146. if (!PCI_BUS(bdf))
  147. writel(CONFIG_SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR);
  148. else
  149. writel(CONFIG_SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR);
  150. /* Check for errors */
  151. if (readl(priv->regs + PCIEERRFR) & UNSUPPORTED_REQUEST)
  152. return -ENODEV;
  153. /* Check for master and target aborts */
  154. if (rcar_read_conf(udev, RCONF(PCI_STATUS)) &
  155. (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
  156. return -ENODEV;
  157. if (access_type == RCAR_PCI_ACCESS_READ)
  158. *data = readl(priv->regs + PCIECDR);
  159. else
  160. writel(*data, priv->regs + PCIECDR);
  161. /* Disable the configuration access */
  162. writel(0, priv->regs + PCIECCTLR);
  163. return 0;
  164. }
  165. static int rcar_gen3_pcie_addr_valid(pci_dev_t d, uint where)
  166. {
  167. u32 slot;
  168. if (PCI_BUS(d))
  169. return -EINVAL;
  170. if (PCI_FUNC(d))
  171. return -EINVAL;
  172. slot = PCI_DEV(d);
  173. if (slot > 1)
  174. return -EINVAL;
  175. return 0;
  176. }
  177. static int rcar_gen3_pcie_read_config(const struct udevice *dev, pci_dev_t bdf,
  178. uint where, ulong *val,
  179. enum pci_size_t size)
  180. {
  181. ulong reg;
  182. int ret;
  183. ret = rcar_gen3_pcie_addr_valid(bdf, where);
  184. if (ret) {
  185. *val = pci_get_ff(size);
  186. return 0;
  187. }
  188. ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_READ,
  189. bdf, where, &reg);
  190. if (ret != 0)
  191. reg = 0xffffffffUL;
  192. *val = pci_conv_32_to_size(reg, where, size);
  193. return ret;
  194. }
  195. static int rcar_gen3_pcie_write_config(struct udevice *dev, pci_dev_t bdf,
  196. uint where, ulong val,
  197. enum pci_size_t size)
  198. {
  199. ulong data;
  200. int ret;
  201. ret = rcar_gen3_pcie_addr_valid(bdf, where);
  202. if (ret)
  203. return ret;
  204. data = pci_conv_32_to_size(val, where, size);
  205. ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_WRITE,
  206. bdf, where, &data);
  207. return ret;
  208. }
  209. static int rcar_gen3_pcie_wait_for_phyrdy(struct udevice *dev)
  210. {
  211. struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
  212. return wait_for_bit_le32((void *)priv->regs + PCIEPHYSR, PHYRDY,
  213. true, 50, false);
  214. }
  215. static int rcar_gen3_pcie_wait_for_dl(struct udevice *dev)
  216. {
  217. struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
  218. return wait_for_bit_le32((void *)priv->regs + PCIETSTR,
  219. DATA_LINK_ACTIVE, true, 50, false);
  220. }
  221. static int rcar_gen3_pcie_hw_init(struct udevice *dev)
  222. {
  223. struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
  224. int ret;
  225. /* Begin initialization */
  226. writel(0, priv->regs + PCIETCTLR);
  227. /* Set mode */
  228. writel(1, priv->regs + PCIEMSR);
  229. ret = rcar_gen3_pcie_wait_for_phyrdy(dev);
  230. if (ret)
  231. return ret;
  232. /*
  233. * Initial header for port config space is type 1, set the device
  234. * class to match. Hardware takes care of propagating the IDSETR
  235. * settings, so there is no need to bother with a quirk.
  236. */
  237. writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1);
  238. /*
  239. * Setup Secondary Bus Number & Subordinate Bus Number, even though
  240. * they aren't used, to avoid bridge being detected as broken.
  241. */
  242. rcar_rmw32(dev, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
  243. rcar_rmw32(dev, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
  244. /* Initialize default capabilities. */
  245. rcar_rmw32(dev, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
  246. rcar_rmw32(dev, REXPCAP(PCI_EXP_FLAGS),
  247. PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
  248. rcar_rmw32(dev, RCONF(PCI_HEADER_TYPE), 0x7f,
  249. PCI_HEADER_TYPE_BRIDGE);
  250. /* Enable data link layer active state reporting */
  251. rcar_rmw32(dev, REXPCAP(PCI_EXP_LNKCAP),
  252. PCI_EXP_LNKCAP_DLLLARC, PCI_EXP_LNKCAP_DLLLARC);
  253. /* Write out the physical slot number = 0 */
  254. rcar_rmw32(dev, REXPCAP(PCI_EXP_SLTCAP),
  255. PCI_EXP_SLTCAP_PSN, 0);
  256. /* Set the completion timer timeout to the maximum 50ms. */
  257. rcar_rmw32(dev, TLCTLR + 1, 0x3f, 50);
  258. /* Terminate list of capabilities (Next Capability Offset=0) */
  259. rcar_rmw32(dev, RVCCAP(0), 0xfff00000, 0);
  260. /* Finish initialization - establish a PCI Express link */
  261. writel(CFINIT, priv->regs + PCIETCTLR);
  262. return rcar_gen3_pcie_wait_for_dl(dev);
  263. }
  264. static int rcar_gen3_pcie_probe(struct udevice *dev)
  265. {
  266. struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
  267. struct pci_controller *hose = dev_get_uclass_priv(dev);
  268. struct clk pci_clk;
  269. u32 mask;
  270. int i, cnt, ret;
  271. ret = clk_get_by_index(dev, 0, &pci_clk);
  272. if (ret)
  273. return ret;
  274. ret = clk_enable(&pci_clk);
  275. if (ret)
  276. return ret;
  277. for (i = 0; i < hose->region_count; i++) {
  278. if (hose->regions[i].flags != PCI_REGION_SYS_MEMORY)
  279. continue;
  280. if (hose->regions[i].phys_start == 0)
  281. continue;
  282. mask = (roundup_pow_of_two(hose->regions[i].size) - 1) & ~0xf;
  283. mask |= LAR_ENABLE;
  284. writel(rounddown_pow_of_two(hose->regions[i].phys_start),
  285. priv->regs + PCIEPRAR(0));
  286. writel(rounddown_pow_of_two(hose->regions[i].phys_start),
  287. priv->regs + PCIELAR(0));
  288. writel(mask, priv->regs + PCIELAMR(0));
  289. break;
  290. }
  291. writel(0, priv->regs + PCIEPRAR(1));
  292. writel(0, priv->regs + PCIELAR(1));
  293. writel(0, priv->regs + PCIELAMR(1));
  294. ret = rcar_gen3_pcie_hw_init(dev);
  295. if (ret)
  296. return ret;
  297. for (i = 0, cnt = 0; i < hose->region_count; i++) {
  298. if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
  299. continue;
  300. writel(0, priv->regs + PCIEPTCTLR(cnt));
  301. writel((hose->regions[i].size - 1) & ~0x7f,
  302. priv->regs + PCIEPAMR(cnt));
  303. writel(upper_32_bits(hose->regions[i].phys_start),
  304. priv->regs + PCIEPAUR(cnt));
  305. writel(lower_32_bits(hose->regions[i].phys_start),
  306. priv->regs + PCIEPALR(cnt));
  307. mask = PAR_ENABLE;
  308. if (hose->regions[i].flags == PCI_REGION_IO)
  309. mask |= IO_SPACE;
  310. writel(mask, priv->regs + PCIEPTCTLR(cnt));
  311. cnt++;
  312. }
  313. return 0;
  314. }
  315. static int rcar_gen3_pcie_of_to_plat(struct udevice *dev)
  316. {
  317. struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
  318. priv->regs = devfdt_get_addr_index(dev, 0);
  319. if (!priv->regs)
  320. return -EINVAL;
  321. return 0;
  322. }
  323. static const struct dm_pci_ops rcar_gen3_pcie_ops = {
  324. .read_config = rcar_gen3_pcie_read_config,
  325. .write_config = rcar_gen3_pcie_write_config,
  326. };
  327. static const struct udevice_id rcar_gen3_pcie_ids[] = {
  328. { .compatible = "renesas,pcie-rcar-gen3" },
  329. { }
  330. };
  331. U_BOOT_DRIVER(rcar_gen3_pcie) = {
  332. .name = "rcar_gen3_pcie",
  333. .id = UCLASS_PCI,
  334. .of_match = rcar_gen3_pcie_ids,
  335. .ops = &rcar_gen3_pcie_ops,
  336. .probe = rcar_gen3_pcie_probe,
  337. .of_to_plat = rcar_gen3_pcie_of_to_plat,
  338. .plat_auto = sizeof(struct rcar_gen3_pcie_priv),
  339. };