pci-aardvark.c 27 KB

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  1. /*
  2. * ***************************************************************************
  3. * Copyright (C) 2015 Marvell International Ltd.
  4. * ***************************************************************************
  5. * This program is free software: you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation, either version 2 of the License, or any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  16. * ***************************************************************************
  17. */
  18. /* pcie_advk.c
  19. *
  20. * Ported from Linux driver - driver/pci/host/pci-aardvark.c
  21. *
  22. * Author: Victor Gu <xigu@marvell.com>
  23. * Hezi Shahmoon <hezi.shahmoon@marvell.com>
  24. *
  25. */
  26. #include <common.h>
  27. #include <dm.h>
  28. #include <pci.h>
  29. #include <asm/io.h>
  30. #include <asm-generic/gpio.h>
  31. #include <dm/device_compat.h>
  32. #include <linux/bitops.h>
  33. #include <linux/delay.h>
  34. #include <linux/ioport.h>
  35. /* PCIe core registers */
  36. #define PCIE_CORE_CMD_STATUS_REG 0x4
  37. #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
  38. #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
  39. #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
  40. #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
  41. #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
  42. #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
  43. #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2
  44. #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5
  45. #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2
  46. #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
  47. #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
  48. #define PCIE_CORE_LINK_TRAINING BIT(5)
  49. #define PCIE_CORE_ERR_CAPCTL_REG 0x118
  50. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
  51. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
  52. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
  53. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
  54. /* PIO registers base address and register offsets */
  55. #define PIO_BASE_ADDR 0x4000
  56. #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
  57. #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
  58. #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
  59. #define PIO_STAT (PIO_BASE_ADDR + 0x4)
  60. #define PIO_COMPLETION_STATUS_SHIFT 7
  61. #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
  62. #define PIO_COMPLETION_STATUS_OK 0
  63. #define PIO_COMPLETION_STATUS_UR 1
  64. #define PIO_COMPLETION_STATUS_CRS 2
  65. #define PIO_COMPLETION_STATUS_CA 4
  66. #define PIO_NON_POSTED_REQ BIT(10)
  67. #define PIO_ERR_STATUS BIT(11)
  68. #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
  69. #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
  70. #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
  71. #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
  72. #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
  73. #define PIO_START (PIO_BASE_ADDR + 0x1c)
  74. #define PIO_ISR (PIO_BASE_ADDR + 0x20)
  75. /* Aardvark Control registers */
  76. #define CONTROL_BASE_ADDR 0x4800
  77. #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
  78. #define PCIE_GEN_SEL_MSK 0x3
  79. #define PCIE_GEN_SEL_SHIFT 0x0
  80. #define SPEED_GEN_1 0
  81. #define SPEED_GEN_2 1
  82. #define SPEED_GEN_3 2
  83. #define IS_RC_MSK 1
  84. #define IS_RC_SHIFT 2
  85. #define LANE_CNT_MSK 0x18
  86. #define LANE_CNT_SHIFT 0x3
  87. #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
  88. #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
  89. #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
  90. #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
  91. #define LINK_TRAINING_EN BIT(6)
  92. #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
  93. #define PCIE_CORE_CTRL2_RESERVED 0x7
  94. #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
  95. #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
  96. #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
  97. /* PCIe window configuration */
  98. #define OB_WIN_BASE_ADDR 0x4c00
  99. #define OB_WIN_BLOCK_SIZE 0x20
  100. #define OB_WIN_COUNT 8
  101. #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
  102. OB_WIN_BLOCK_SIZE * (win) + \
  103. (offset))
  104. #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
  105. #define OB_WIN_ENABLE BIT(0)
  106. #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
  107. #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
  108. #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
  109. #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
  110. #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
  111. #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
  112. #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
  113. #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
  114. #define OB_WIN_FUNC_NUM_SHIFT 24
  115. #define OB_WIN_FUNC_NUM_ENABLE BIT(23)
  116. #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
  117. #define OB_WIN_BUS_NUM_BITS_SHIFT 20
  118. #define OB_WIN_MSG_CODE_ENABLE BIT(22)
  119. #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
  120. #define OB_WIN_MSG_CODE_SHIFT 14
  121. #define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
  122. #define OB_WIN_ATTR_ENABLE BIT(11)
  123. #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
  124. #define OB_WIN_ATTR_TC_SHIFT 8
  125. #define OB_WIN_ATTR_RELAXED BIT(7)
  126. #define OB_WIN_ATTR_NOSNOOP BIT(6)
  127. #define OB_WIN_ATTR_POISON BIT(5)
  128. #define OB_WIN_ATTR_IDO BIT(4)
  129. #define OB_WIN_TYPE_MASK GENMASK(3, 0)
  130. #define OB_WIN_TYPE_SHIFT 0
  131. #define OB_WIN_TYPE_MEM 0x0
  132. #define OB_WIN_TYPE_IO 0x4
  133. #define OB_WIN_TYPE_CONFIG_TYPE0 0x8
  134. #define OB_WIN_TYPE_CONFIG_TYPE1 0x9
  135. #define OB_WIN_TYPE_MSG 0xc
  136. /* LMI registers base address and register offsets */
  137. #define LMI_BASE_ADDR 0x6000
  138. #define CFG_REG (LMI_BASE_ADDR + 0x0)
  139. #define LTSSM_SHIFT 24
  140. #define LTSSM_MASK 0x3f
  141. #define LTSSM_L0 0x10
  142. #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
  143. /* PCIe core controller registers */
  144. #define CTRL_CORE_BASE_ADDR 0x18000
  145. #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
  146. #define CTRL_MODE_SHIFT 0x0
  147. #define CTRL_MODE_MASK 0x1
  148. #define PCIE_CORE_MODE_DIRECT 0x0
  149. #define PCIE_CORE_MODE_COMMAND 0x1
  150. /* Transaction types */
  151. #define PCIE_CONFIG_RD_TYPE0 0x8
  152. #define PCIE_CONFIG_RD_TYPE1 0x9
  153. #define PCIE_CONFIG_WR_TYPE0 0xa
  154. #define PCIE_CONFIG_WR_TYPE1 0xb
  155. /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
  156. #define PCIE_BDF(dev) (dev << 4)
  157. #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
  158. #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
  159. #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
  160. #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
  161. #define PCIE_CONF_ADDR(bus, devfn, where) \
  162. (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
  163. PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
  164. /* PCIe Retries & Timeout definitions */
  165. #define PIO_MAX_RETRIES 1500
  166. #define PIO_WAIT_TIMEOUT 1000
  167. #define LINK_MAX_RETRIES 10
  168. #define LINK_WAIT_TIMEOUT 100000
  169. #define CFG_RD_CRS_VAL 0xFFFF0001
  170. /**
  171. * struct pcie_advk - Advk PCIe controller state
  172. *
  173. * @reg_base: The base address of the register space.
  174. * @first_busno: This driver supports multiple PCIe controllers.
  175. * first_busno stores the bus number of the PCIe root-port
  176. * number which may vary depending on the PCIe setup
  177. * (PEX switches etc).
  178. * @device: The pointer to PCI uclass device.
  179. */
  180. struct pcie_advk {
  181. void *base;
  182. int first_busno;
  183. struct udevice *dev;
  184. struct gpio_desc reset_gpio;
  185. };
  186. static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
  187. {
  188. writel(val, pcie->base + reg);
  189. }
  190. static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
  191. {
  192. return readl(pcie->base + reg);
  193. }
  194. /**
  195. * pcie_advk_addr_valid() - Check for valid bus address
  196. *
  197. * @bdf: The PCI device to access
  198. * @first_busno: Bus number of the PCIe controller root complex
  199. *
  200. * Return: 1 on valid, 0 on invalid
  201. */
  202. static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
  203. {
  204. /*
  205. * In PCIE-E only a single device (0) can exist
  206. * on the local bus. Beyound the local bus, there might be
  207. * a Switch and everything is possible.
  208. */
  209. if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
  210. return 0;
  211. return 1;
  212. }
  213. /**
  214. * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
  215. *
  216. * @pcie: The PCI device to access
  217. *
  218. * Wait up to 1.5 seconds for PIO access to be accomplished.
  219. *
  220. * Return positive - retry count if PIO access is accomplished.
  221. * Return negative - error if PIO access is timed out.
  222. */
  223. static int pcie_advk_wait_pio(struct pcie_advk *pcie)
  224. {
  225. uint start, isr;
  226. uint count;
  227. for (count = 1; count <= PIO_MAX_RETRIES; count++) {
  228. start = advk_readl(pcie, PIO_START);
  229. isr = advk_readl(pcie, PIO_ISR);
  230. if (!start && isr)
  231. return count;
  232. /*
  233. * Do not check the PIO state too frequently,
  234. * 100us delay is appropriate.
  235. */
  236. udelay(PIO_WAIT_TIMEOUT);
  237. }
  238. dev_err(pcie->dev, "PIO read/write transfer time out\n");
  239. return -ETIMEDOUT;
  240. }
  241. /**
  242. * pcie_advk_check_pio_status() - Validate PIO status and get the read result
  243. *
  244. * @pcie: Pointer to the PCI bus
  245. * @allow_crs: Only for read requests, if CRS response is allowed
  246. * @read_val: Pointer to the read result
  247. *
  248. * Return: 0 on success
  249. */
  250. static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
  251. bool allow_crs,
  252. uint *read_val)
  253. {
  254. int ret;
  255. uint reg;
  256. unsigned int status;
  257. char *strcomp_status, *str_posted;
  258. reg = advk_readl(pcie, PIO_STAT);
  259. status = (reg & PIO_COMPLETION_STATUS_MASK) >>
  260. PIO_COMPLETION_STATUS_SHIFT;
  261. switch (status) {
  262. case PIO_COMPLETION_STATUS_OK:
  263. if (reg & PIO_ERR_STATUS) {
  264. strcomp_status = "COMP_ERR";
  265. ret = -EFAULT;
  266. break;
  267. }
  268. /* Get the read result */
  269. if (read_val)
  270. *read_val = advk_readl(pcie, PIO_RD_DATA);
  271. /* No error */
  272. strcomp_status = NULL;
  273. ret = 0;
  274. break;
  275. case PIO_COMPLETION_STATUS_UR:
  276. strcomp_status = "UR";
  277. ret = -EOPNOTSUPP;
  278. break;
  279. case PIO_COMPLETION_STATUS_CRS:
  280. if (allow_crs && read_val) {
  281. /* For reading, CRS is not an error status. */
  282. *read_val = CFG_RD_CRS_VAL;
  283. strcomp_status = NULL;
  284. ret = 0;
  285. } else {
  286. strcomp_status = "CRS";
  287. ret = -EAGAIN;
  288. }
  289. break;
  290. case PIO_COMPLETION_STATUS_CA:
  291. strcomp_status = "CA";
  292. ret = -ECANCELED;
  293. break;
  294. default:
  295. strcomp_status = "Unknown";
  296. ret = -EINVAL;
  297. break;
  298. }
  299. if (!strcomp_status)
  300. return ret;
  301. if (reg & PIO_NON_POSTED_REQ)
  302. str_posted = "Non-posted";
  303. else
  304. str_posted = "Posted";
  305. dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
  306. str_posted, strcomp_status, reg,
  307. advk_readl(pcie, PIO_ADDR_LS));
  308. return ret;
  309. }
  310. /**
  311. * pcie_advk_read_config() - Read from configuration space
  312. *
  313. * @bus: Pointer to the PCI bus
  314. * @bdf: Identifies the PCIe device to access
  315. * @offset: The offset into the device's configuration space
  316. * @valuep: A pointer at which to store the read value
  317. * @size: Indicates the size of access to perform
  318. *
  319. * Read a value of size @size from offset @offset within the configuration
  320. * space of the device identified by the bus, device & function numbers in @bdf
  321. * on the PCI bus @bus.
  322. *
  323. * Return: 0 on success
  324. */
  325. static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
  326. uint offset, ulong *valuep,
  327. enum pci_size_t size)
  328. {
  329. struct pcie_advk *pcie = dev_get_priv(bus);
  330. int retry_count;
  331. bool allow_crs;
  332. uint reg;
  333. int ret;
  334. dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  335. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  336. if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
  337. dev_dbg(pcie->dev, "- out of range\n");
  338. *valuep = pci_get_ff(size);
  339. return 0;
  340. }
  341. /*
  342. * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to
  343. * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
  344. * only when CRSSVE bit in Root Port PCIe device is enabled. In all
  345. * other error PCIe Root Complex must return all-ones.
  346. * Aardvark HW does not have Root Port PCIe device and U-Boot does not
  347. * implement emulation of this device.
  348. * U-Boot currently does not support handling of CRS return value for
  349. * PCI_VENDOR_ID config read request and also does not set CRSSVE bit.
  350. * Therefore disable returning CRS response for now.
  351. */
  352. allow_crs = false;
  353. if (advk_readl(pcie, PIO_START)) {
  354. dev_err(pcie->dev,
  355. "Previous PIO read/write transfer is still running\n");
  356. if (allow_crs) {
  357. *valuep = CFG_RD_CRS_VAL;
  358. return 0;
  359. }
  360. *valuep = pci_get_ff(size);
  361. return -EAGAIN;
  362. }
  363. /* Program the control register */
  364. reg = advk_readl(pcie, PIO_CTRL);
  365. reg &= ~PIO_CTRL_TYPE_MASK;
  366. if (PCI_BUS(bdf) == pcie->first_busno)
  367. reg |= PCIE_CONFIG_RD_TYPE0;
  368. else
  369. reg |= PCIE_CONFIG_RD_TYPE1;
  370. advk_writel(pcie, reg, PIO_CTRL);
  371. /* Program the address registers */
  372. reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
  373. advk_writel(pcie, reg, PIO_ADDR_LS);
  374. advk_writel(pcie, 0, PIO_ADDR_MS);
  375. retry_count = 0;
  376. retry:
  377. /* Start the transfer */
  378. advk_writel(pcie, 1, PIO_ISR);
  379. advk_writel(pcie, 1, PIO_START);
  380. ret = pcie_advk_wait_pio(pcie);
  381. if (ret < 0) {
  382. if (allow_crs) {
  383. *valuep = CFG_RD_CRS_VAL;
  384. return 0;
  385. }
  386. *valuep = pci_get_ff(size);
  387. return ret;
  388. }
  389. retry_count += ret;
  390. /* Check PIO status and get the read result */
  391. ret = pcie_advk_check_pio_status(pcie, allow_crs, &reg);
  392. if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
  393. goto retry;
  394. if (ret) {
  395. *valuep = pci_get_ff(size);
  396. return ret;
  397. }
  398. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
  399. offset, size, reg);
  400. *valuep = pci_conv_32_to_size(reg, offset, size);
  401. return 0;
  402. }
  403. /**
  404. * pcie_calc_datastrobe() - Calculate data strobe
  405. *
  406. * @offset: The offset into the device's configuration space
  407. * @size: Indicates the size of access to perform
  408. *
  409. * Calculate data strobe according to offset and size
  410. *
  411. */
  412. static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
  413. {
  414. uint bytes, data_strobe;
  415. switch (size) {
  416. case PCI_SIZE_8:
  417. bytes = 1;
  418. break;
  419. case PCI_SIZE_16:
  420. bytes = 2;
  421. break;
  422. default:
  423. bytes = 4;
  424. }
  425. data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
  426. return data_strobe;
  427. }
  428. /**
  429. * pcie_advk_write_config() - Write to configuration space
  430. *
  431. * @bus: Pointer to the PCI bus
  432. * @bdf: Identifies the PCIe device to access
  433. * @offset: The offset into the device's configuration space
  434. * @value: The value to write
  435. * @size: Indicates the size of access to perform
  436. *
  437. * Write the value @value of size @size from offset @offset within the
  438. * configuration space of the device identified by the bus, device & function
  439. * numbers in @bdf on the PCI bus @bus.
  440. *
  441. * Return: 0 on success
  442. */
  443. static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
  444. uint offset, ulong value,
  445. enum pci_size_t size)
  446. {
  447. struct pcie_advk *pcie = dev_get_priv(bus);
  448. int retry_count;
  449. uint reg;
  450. int ret;
  451. dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  452. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  453. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
  454. offset, size, value);
  455. if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
  456. dev_dbg(pcie->dev, "- out of range\n");
  457. return 0;
  458. }
  459. if (advk_readl(pcie, PIO_START)) {
  460. dev_err(pcie->dev,
  461. "Previous PIO read/write transfer is still running\n");
  462. return -EAGAIN;
  463. }
  464. /* Program the control register */
  465. reg = advk_readl(pcie, PIO_CTRL);
  466. reg &= ~PIO_CTRL_TYPE_MASK;
  467. if (PCI_BUS(bdf) == pcie->first_busno)
  468. reg |= PCIE_CONFIG_WR_TYPE0;
  469. else
  470. reg |= PCIE_CONFIG_WR_TYPE1;
  471. advk_writel(pcie, reg, PIO_CTRL);
  472. /* Program the address registers */
  473. reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
  474. advk_writel(pcie, reg, PIO_ADDR_LS);
  475. advk_writel(pcie, 0, PIO_ADDR_MS);
  476. dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
  477. /* Program the data register */
  478. reg = pci_conv_size_to_32(0, value, offset, size);
  479. advk_writel(pcie, reg, PIO_WR_DATA);
  480. dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
  481. /* Program the data strobe */
  482. reg = pcie_calc_datastrobe(offset, size);
  483. advk_writel(pcie, reg, PIO_WR_DATA_STRB);
  484. dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
  485. retry_count = 0;
  486. retry:
  487. /* Start the transfer */
  488. advk_writel(pcie, 1, PIO_ISR);
  489. advk_writel(pcie, 1, PIO_START);
  490. ret = pcie_advk_wait_pio(pcie);
  491. if (ret < 0)
  492. return ret;
  493. retry_count += ret;
  494. /* Check PIO status */
  495. ret = pcie_advk_check_pio_status(pcie, false, NULL);
  496. if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
  497. goto retry;
  498. return ret;
  499. }
  500. /**
  501. * pcie_advk_link_up() - Check if PCIe link is up or not
  502. *
  503. * @pcie: The PCI device to access
  504. *
  505. * Return 1 (true) on link up.
  506. * Return 0 (false) on link down.
  507. */
  508. static int pcie_advk_link_up(struct pcie_advk *pcie)
  509. {
  510. u32 val, ltssm_state;
  511. val = advk_readl(pcie, CFG_REG);
  512. ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
  513. return ltssm_state >= LTSSM_L0;
  514. }
  515. /**
  516. * pcie_advk_wait_for_link() - Wait for link training to be accomplished
  517. *
  518. * @pcie: The PCI device to access
  519. *
  520. * Wait up to 1 second for link training to be accomplished.
  521. *
  522. * Return 1 (true) if link training ends up with link up success.
  523. * Return 0 (false) if link training ends up with link up failure.
  524. */
  525. static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
  526. {
  527. int retries;
  528. /* check if the link is up or not */
  529. for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
  530. if (pcie_advk_link_up(pcie)) {
  531. printf("PCIE-%d: Link up\n", pcie->first_busno);
  532. return 0;
  533. }
  534. udelay(LINK_WAIT_TIMEOUT);
  535. }
  536. printf("PCIE-%d: Link down\n", pcie->first_busno);
  537. return -ETIMEDOUT;
  538. }
  539. /*
  540. * Set PCIe address window register which could be used for memory
  541. * mapping.
  542. */
  543. static void pcie_advk_set_ob_win(struct pcie_advk *pcie, u8 win_num,
  544. phys_addr_t match, phys_addr_t remap,
  545. phys_addr_t mask, u32 actions)
  546. {
  547. advk_writel(pcie, OB_WIN_ENABLE |
  548. lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
  549. advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
  550. advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
  551. advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
  552. advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
  553. advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
  554. advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
  555. }
  556. static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
  557. {
  558. advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
  559. advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
  560. advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
  561. advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
  562. advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
  563. advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
  564. advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
  565. }
  566. static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
  567. struct pci_region *region, u32 actions)
  568. {
  569. phys_addr_t phys_start = region->phys_start;
  570. pci_addr_t bus_start = region->bus_start;
  571. pci_size_t size = region->size;
  572. phys_addr_t win_mask;
  573. u64 win_size;
  574. if (*wins == -1)
  575. return;
  576. /*
  577. * The n-th PCIe window is configured by tuple (match, remap, mask)
  578. * and an access to address A uses this window if A matches the
  579. * match with given mask.
  580. * So every PCIe window size must be a power of two and every start
  581. * address must be aligned to window size. Minimal size is 64 KiB
  582. * because lower 16 bits of mask must be zero. Remapped address
  583. * may have set only bits from the mask.
  584. */
  585. while (*wins < OB_WIN_COUNT && size > 0) {
  586. /* Calculate the largest aligned window size */
  587. win_size = (1ULL << (fls64(size) - 1)) |
  588. (phys_start ? (1ULL << __ffs64(phys_start)) : 0);
  589. win_size = 1ULL << __ffs64(win_size);
  590. win_mask = ~(win_size - 1);
  591. if (win_size < 0x10000 || (bus_start & ~win_mask))
  592. break;
  593. dev_dbg(pcie->dev,
  594. "Configuring PCIe window %d: [0x%llx-0x%llx] as 0x%x\n",
  595. *wins, (u64)phys_start, (u64)phys_start + win_size,
  596. actions);
  597. pcie_advk_set_ob_win(pcie, *wins, phys_start, bus_start,
  598. win_mask, actions);
  599. phys_start += win_size;
  600. bus_start += win_size;
  601. size -= win_size;
  602. (*wins)++;
  603. }
  604. if (size > 0) {
  605. *wins = -1;
  606. dev_err(pcie->dev,
  607. "Invalid PCIe region [0x%llx-0x%llx]\n",
  608. (u64)region->phys_start,
  609. (u64)region->phys_start + region->size);
  610. }
  611. }
  612. /**
  613. * pcie_advk_setup_hw() - PCIe initailzation
  614. *
  615. * @pcie: The PCI device to access
  616. *
  617. * Return: 0 on success
  618. */
  619. static int pcie_advk_setup_hw(struct pcie_advk *pcie)
  620. {
  621. struct pci_region *io, *mem, *pref;
  622. int i, wins;
  623. u32 reg;
  624. /* Set to Direct mode */
  625. reg = advk_readl(pcie, CTRL_CONFIG_REG);
  626. reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
  627. reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
  628. advk_writel(pcie, reg, CTRL_CONFIG_REG);
  629. /* Set PCI global control register to RC mode */
  630. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  631. reg |= (IS_RC_MSK << IS_RC_SHIFT);
  632. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  633. /*
  634. * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
  635. * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
  636. * id in high 16 bits. Updating this register changes readback value of
  637. * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
  638. * for erratum 4.1: "The value of device and vendor ID is incorrect".
  639. */
  640. advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
  641. /* Set Advanced Error Capabilities and Control PF0 register */
  642. reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
  643. PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
  644. PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
  645. PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
  646. advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
  647. /* Set PCIe Device Control and Status 1 PF0 register */
  648. reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
  649. (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<
  650. PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |
  651. (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<
  652. PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
  653. PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
  654. advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
  655. /* Program PCIe Control 2 to disable strict ordering */
  656. reg = PCIE_CORE_CTRL2_RESERVED |
  657. PCIE_CORE_CTRL2_TD_ENABLE;
  658. advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  659. /* Set GEN2 */
  660. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  661. reg &= ~PCIE_GEN_SEL_MSK;
  662. reg |= SPEED_GEN_2;
  663. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  664. /* Set lane X1 */
  665. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  666. reg &= ~LANE_CNT_MSK;
  667. reg |= LANE_COUNT_1;
  668. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  669. /* Enable link training */
  670. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  671. reg |= LINK_TRAINING_EN;
  672. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  673. /*
  674. * Enable AXI address window location generation:
  675. * When it is enabled, the default outbound window
  676. * configurations (Default User Field: 0xD0074CFC)
  677. * are used to transparent address translation for
  678. * the outbound transactions. Thus, PCIe address
  679. * windows are not required for transparent memory
  680. * access when default outbound window configuration
  681. * is set for memory access.
  682. */
  683. reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
  684. reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
  685. advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  686. /*
  687. * Bypass the address window mapping for PIO:
  688. * Since PIO access already contains all required
  689. * info over AXI interface by PIO registers, the
  690. * address window is not required.
  691. */
  692. reg = advk_readl(pcie, PIO_CTRL);
  693. reg |= PIO_CTRL_ADDR_WIN_DISABLE;
  694. advk_writel(pcie, reg, PIO_CTRL);
  695. /*
  696. * Set memory access in Default User Field so it
  697. * is not required to configure PCIe address for
  698. * transparent memory access.
  699. */
  700. advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
  701. /*
  702. * Configure PCIe address windows for non-memory or
  703. * non-transparent access as by default PCIe uses
  704. * transparent memory access.
  705. */
  706. wins = 0;
  707. pci_get_regions(pcie->dev, &io, &mem, &pref);
  708. if (io)
  709. pcie_advk_set_ob_region(pcie, &wins, io, OB_WIN_TYPE_IO);
  710. if (mem && mem->phys_start != mem->bus_start)
  711. pcie_advk_set_ob_region(pcie, &wins, mem, OB_WIN_TYPE_MEM);
  712. if (pref && pref->phys_start != pref->bus_start)
  713. pcie_advk_set_ob_region(pcie, &wins, pref, OB_WIN_TYPE_MEM);
  714. /* Disable remaining PCIe outbound windows */
  715. for (i = ((wins >= 0) ? wins : 0); i < OB_WIN_COUNT; i++)
  716. pcie_advk_disable_ob_win(pcie, i);
  717. if (wins == -1)
  718. return -EINVAL;
  719. /* Wait for PCIe link up */
  720. if (pcie_advk_wait_for_link(pcie))
  721. return -ENXIO;
  722. reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
  723. reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
  724. PCIE_CORE_CMD_IO_ACCESS_EN |
  725. PCIE_CORE_CMD_MEM_IO_REQ_EN;
  726. advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
  727. return 0;
  728. }
  729. /**
  730. * pcie_advk_probe() - Probe the PCIe bus for active link
  731. *
  732. * @dev: A pointer to the device being operated on
  733. *
  734. * Probe for an active link on the PCIe bus and configure the controller
  735. * to enable this port.
  736. *
  737. * Return: 0 on success, else -ENODEV
  738. */
  739. static int pcie_advk_probe(struct udevice *dev)
  740. {
  741. struct pcie_advk *pcie = dev_get_priv(dev);
  742. gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio,
  743. GPIOD_IS_OUT);
  744. /*
  745. * Issue reset to add-in card through the dedicated GPIO.
  746. * Some boards are connecting the card reset pin to common system
  747. * reset wire and others are using separate GPIO port.
  748. * In the last case we have to release a reset of the addon card
  749. * using this GPIO.
  750. *
  751. * FIX-ME:
  752. * The PCIe RESET signal is not supposed to be released along
  753. * with the SOC RESET signal. It should be lowered as early as
  754. * possible before PCIe PHY initialization. Moreover, the PCIe
  755. * clock should be gated as well.
  756. */
  757. if (dm_gpio_is_valid(&pcie->reset_gpio)) {
  758. dev_dbg(dev, "Toggle PCIE Reset GPIO ...\n");
  759. dm_gpio_set_value(&pcie->reset_gpio, 1);
  760. mdelay(200);
  761. dm_gpio_set_value(&pcie->reset_gpio, 0);
  762. } else {
  763. dev_warn(dev, "PCIE Reset on GPIO support is missing\n");
  764. }
  765. pcie->first_busno = dev_seq(dev);
  766. pcie->dev = pci_get_controller(dev);
  767. return pcie_advk_setup_hw(pcie);
  768. }
  769. static int pcie_advk_remove(struct udevice *dev)
  770. {
  771. struct pcie_advk *pcie = dev_get_priv(dev);
  772. u32 reg;
  773. int i;
  774. for (i = 0; i < OB_WIN_COUNT; i++)
  775. pcie_advk_disable_ob_win(pcie, i);
  776. reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
  777. reg &= ~(PCIE_CORE_CMD_MEM_ACCESS_EN |
  778. PCIE_CORE_CMD_IO_ACCESS_EN |
  779. PCIE_CORE_CMD_MEM_IO_REQ_EN);
  780. advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
  781. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  782. reg &= ~LINK_TRAINING_EN;
  783. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  784. return 0;
  785. }
  786. /**
  787. * pcie_advk_of_to_plat() - Translate from DT to device state
  788. *
  789. * @dev: A pointer to the device being operated on
  790. *
  791. * Translate relevant data from the device tree pertaining to device @dev into
  792. * state that the driver will later make use of. This state is stored in the
  793. * device's private data structure.
  794. *
  795. * Return: 0 on success, else -EINVAL
  796. */
  797. static int pcie_advk_of_to_plat(struct udevice *dev)
  798. {
  799. struct pcie_advk *pcie = dev_get_priv(dev);
  800. /* Get the register base address */
  801. pcie->base = (void *)dev_read_addr_index(dev, 0);
  802. if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
  803. return -EINVAL;
  804. return 0;
  805. }
  806. static const struct dm_pci_ops pcie_advk_ops = {
  807. .read_config = pcie_advk_read_config,
  808. .write_config = pcie_advk_write_config,
  809. };
  810. static const struct udevice_id pcie_advk_ids[] = {
  811. { .compatible = "marvell,armada-3700-pcie" },
  812. { }
  813. };
  814. U_BOOT_DRIVER(pcie_advk) = {
  815. .name = "pcie_advk",
  816. .id = UCLASS_PCI,
  817. .of_match = pcie_advk_ids,
  818. .ops = &pcie_advk_ops,
  819. .of_to_plat = pcie_advk_of_to_plat,
  820. .probe = pcie_advk_probe,
  821. .remove = pcie_advk_remove,
  822. .flags = DM_FLAG_OS_PREPARE,
  823. .priv_auto = sizeof(struct pcie_advk),
  824. };