fsl_pci_init.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <asm/fsl_serdes.h>
  11. #include <asm/global_data.h>
  12. #include <linux/delay.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. /*
  15. * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  16. *
  17. * Initialize controller and call the common driver/pci pci_hose_scan to
  18. * scan for bridges and devices.
  19. *
  20. * Hose fields which need to be pre-initialized by board specific code:
  21. * regions[]
  22. * first_busno
  23. *
  24. * Fields updated:
  25. * last_busno
  26. */
  27. #include <pci.h>
  28. #include <asm/io.h>
  29. #include <asm/fsl_pci.h>
  30. #define MAX_PCI_REGIONS 7
  31. #ifndef CONFIG_SYS_PCI_MEMORY_BUS
  32. #define CONFIG_SYS_PCI_MEMORY_BUS 0
  33. #endif
  34. #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
  35. #define CONFIG_SYS_PCI_MEMORY_PHYS 0
  36. #endif
  37. #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
  38. #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
  39. #endif
  40. /* Setup one inbound ATMU window.
  41. *
  42. * We let the caller decide what the window size should be
  43. */
  44. static void set_inbound_window(volatile pit_t *pi,
  45. struct pci_region *r,
  46. u64 size)
  47. {
  48. u32 sz = (__ilog2_u64(size) - 1);
  49. #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
  50. u32 flag = 0;
  51. #else
  52. u32 flag = PIWAR_LOCAL;
  53. #endif
  54. flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  55. out_be32(&pi->pitar, r->phys_start >> 12);
  56. out_be32(&pi->piwbar, r->bus_start >> 12);
  57. #ifdef CONFIG_SYS_PCI_64BIT
  58. out_be32(&pi->piwbear, r->bus_start >> 44);
  59. #else
  60. out_be32(&pi->piwbear, 0);
  61. #endif
  62. if (r->flags & PCI_REGION_PREFETCH)
  63. flag |= PIWAR_PF;
  64. out_be32(&pi->piwar, flag | sz);
  65. }
  66. int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
  67. {
  68. volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
  69. /* Reset hose to make sure its in a clean state */
  70. memset(hose, 0, sizeof(struct pci_controller));
  71. hose->regions = (struct pci_region *)
  72. calloc(1, MAX_PCI_REGIONS * sizeof(struct pci_region));
  73. pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
  74. return fsl_is_pci_agent(hose);
  75. }
  76. static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
  77. u64 out_lo, u8 pcie_cap,
  78. volatile pit_t *pi)
  79. {
  80. struct pci_region *r = hose->regions + hose->region_count;
  81. u64 sz = min((u64)gd->ram_size, (1ull << 32));
  82. phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  83. pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  84. pci_size_t pci_sz;
  85. /* we have no space available for inbound memory mapping */
  86. if (bus_start > out_lo) {
  87. printf ("no space for inbound mapping of memory\n");
  88. return 0;
  89. }
  90. /* limit size */
  91. if ((bus_start + sz) > out_lo) {
  92. sz = out_lo - bus_start;
  93. debug ("limiting size to %llx\n", sz);
  94. }
  95. pci_sz = 1ull << __ilog2_u64(sz);
  96. /*
  97. * we can overlap inbound/outbound windows on PCI-E since RX & TX
  98. * links a separate
  99. */
  100. if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
  101. debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
  102. (u64)bus_start, (u64)phys_start, (u64)sz);
  103. pci_set_region(r, bus_start, phys_start, sz,
  104. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  105. PCI_REGION_PREFETCH);
  106. /* if we aren't an exact power of two match, pci_sz is smaller
  107. * round it up to the next power of two. We report the actual
  108. * size to pci region tracking.
  109. */
  110. if (pci_sz != sz)
  111. sz = 2ull << __ilog2_u64(sz);
  112. set_inbound_window(pi--, r++, sz);
  113. sz = 0; /* make sure we dont set the R2 window */
  114. } else {
  115. debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
  116. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  117. pci_set_region(r, bus_start, phys_start, pci_sz,
  118. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  119. PCI_REGION_PREFETCH);
  120. set_inbound_window(pi--, r++, pci_sz);
  121. sz -= pci_sz;
  122. bus_start += pci_sz;
  123. phys_start += pci_sz;
  124. pci_sz = 1ull << __ilog2_u64(sz);
  125. if (sz) {
  126. debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
  127. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  128. pci_set_region(r, bus_start, phys_start, pci_sz,
  129. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  130. PCI_REGION_PREFETCH);
  131. set_inbound_window(pi--, r++, pci_sz);
  132. sz -= pci_sz;
  133. bus_start += pci_sz;
  134. phys_start += pci_sz;
  135. }
  136. }
  137. #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  138. /*
  139. * On 64-bit capable systems, set up a mapping for all of DRAM
  140. * in high pci address space.
  141. */
  142. pci_sz = 1ull << __ilog2_u64(gd->ram_size);
  143. /* round up to the next largest power of two */
  144. if (gd->ram_size > pci_sz)
  145. pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
  146. debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
  147. (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
  148. (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
  149. (u64)pci_sz);
  150. pci_set_region(r,
  151. CONFIG_SYS_PCI64_MEMORY_BUS,
  152. CONFIG_SYS_PCI_MEMORY_PHYS,
  153. pci_sz,
  154. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  155. PCI_REGION_PREFETCH);
  156. set_inbound_window(pi--, r++, pci_sz);
  157. #else
  158. pci_sz = 1ull << __ilog2_u64(sz);
  159. if (sz) {
  160. debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
  161. (u64)bus_start, (u64)phys_start, (u64)pci_sz);
  162. pci_set_region(r, bus_start, phys_start, pci_sz,
  163. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
  164. PCI_REGION_PREFETCH);
  165. sz -= pci_sz;
  166. bus_start += pci_sz;
  167. phys_start += pci_sz;
  168. set_inbound_window(pi--, r++, pci_sz);
  169. }
  170. #endif
  171. #ifdef CONFIG_PHYS_64BIT
  172. if (sz && (((u64)gd->ram_size) < (1ull << 32)))
  173. printf("Was not able to map all of memory via "
  174. "inbound windows -- %lld remaining\n", sz);
  175. #endif
  176. hose->region_count = r - hose->regions;
  177. return 1;
  178. }
  179. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  180. static void fsl_pcie_boot_master(pit_t *pi)
  181. {
  182. /* configure inbound window for slave's u-boot image */
  183. debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
  184. "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
  185. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  186. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
  187. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  188. struct pci_region r_inbound;
  189. u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
  190. - 1;
  191. pci_set_region(&r_inbound,
  192. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
  193. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  194. sz_inbound,
  195. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  196. set_inbound_window(pi--, &r_inbound,
  197. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  198. /* configure inbound window for slave's u-boot image */
  199. debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
  200. "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
  201. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  202. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
  203. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  204. pci_set_region(&r_inbound,
  205. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
  206. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  207. sz_inbound,
  208. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  209. set_inbound_window(pi--, &r_inbound,
  210. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  211. /* configure inbound window for slave's ucode and ENV */
  212. debug("PCIEBOOT - MASTER: Inbound window for slave's "
  213. "ucode and ENV; "
  214. "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
  215. (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
  216. (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
  217. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
  218. sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
  219. - 1;
  220. pci_set_region(&r_inbound,
  221. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
  222. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
  223. sz_inbound,
  224. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  225. set_inbound_window(pi--, &r_inbound,
  226. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
  227. }
  228. static void fsl_pcie_boot_master_release_slave(int port)
  229. {
  230. unsigned long release_addr;
  231. /* now release slave's core 0 */
  232. switch (port) {
  233. case 1:
  234. release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
  235. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
  236. break;
  237. #ifdef CONFIG_SYS_PCIE2_MEM_VIRT
  238. case 2:
  239. release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
  240. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
  241. break;
  242. #endif
  243. #ifdef CONFIG_SYS_PCIE3_MEM_VIRT
  244. case 3:
  245. release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
  246. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
  247. break;
  248. #endif
  249. default:
  250. release_addr = 0;
  251. break;
  252. }
  253. if (release_addr != 0) {
  254. out_be32((void *)release_addr,
  255. CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
  256. debug("PCIEBOOT - MASTER: "
  257. "Release slave successfully! Now the slave should start up!\n");
  258. } else {
  259. debug("PCIEBOOT - MASTER: "
  260. "Release slave failed!\n");
  261. }
  262. }
  263. #endif
  264. void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
  265. {
  266. u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
  267. u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
  268. u16 temp16;
  269. u32 temp32;
  270. u32 block_rev;
  271. int enabled, r, inbound = 0;
  272. u16 ltssm;
  273. u8 temp8, pcie_cap;
  274. int pcie_cap_pos;
  275. int pci_dcr;
  276. int pci_dsr;
  277. int pci_lsr;
  278. #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
  279. int pci_lcr;
  280. #endif
  281. volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
  282. struct pci_region *reg = hose->regions + hose->region_count;
  283. pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
  284. /* Initialize ATMU registers based on hose regions and flags */
  285. volatile pot_t *po = &pci->pot[1]; /* skip 0 */
  286. volatile pit_t *pi;
  287. u64 out_hi = 0, out_lo = -1ULL;
  288. u32 pcicsrbar, pcicsrbar_sz;
  289. pci_setup_indirect(hose, cfg_addr, cfg_data);
  290. #ifdef PEX_CCB_DIV
  291. /* Configure the PCIE controller core clock ratio */
  292. pci_hose_write_config_dword(hose, dev, 0x440,
  293. ((gd->bus_clk / 1000000) *
  294. (16 / PEX_CCB_DIV)) / 333);
  295. #endif
  296. block_rev = in_be32(&pci->block_rev1);
  297. if (PEX_IP_BLK_REV_2_2 <= block_rev) {
  298. pi = &pci->pit[2]; /* 0xDC0 */
  299. } else {
  300. pi = &pci->pit[3]; /* 0xDE0 */
  301. }
  302. /* Handle setup of outbound windows first */
  303. for (r = 0; r < hose->region_count; r++) {
  304. unsigned long flags = hose->regions[r].flags;
  305. u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
  306. flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
  307. if (flags != PCI_REGION_SYS_MEMORY) {
  308. u64 start = hose->regions[r].bus_start;
  309. u64 end = start + hose->regions[r].size;
  310. out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
  311. out_be32(&po->potar, start >> 12);
  312. #ifdef CONFIG_SYS_PCI_64BIT
  313. out_be32(&po->potear, start >> 44);
  314. #else
  315. out_be32(&po->potear, 0);
  316. #endif
  317. if (hose->regions[r].flags & PCI_REGION_IO) {
  318. out_be32(&po->powar, POWAR_EN | sz |
  319. POWAR_IO_READ | POWAR_IO_WRITE);
  320. } else {
  321. out_be32(&po->powar, POWAR_EN | sz |
  322. POWAR_MEM_READ | POWAR_MEM_WRITE);
  323. out_lo = min(start, out_lo);
  324. out_hi = max(end, out_hi);
  325. }
  326. po++;
  327. }
  328. }
  329. debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
  330. /* setup PCSRBAR/PEXCSRBAR */
  331. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
  332. pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
  333. pcicsrbar_sz = ~pcicsrbar_sz + 1;
  334. if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
  335. (out_lo > 0x100000000ull))
  336. pcicsrbar = 0x100000000ull - pcicsrbar_sz;
  337. else
  338. pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
  339. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
  340. out_lo = min(out_lo, (u64)pcicsrbar);
  341. debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
  342. pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
  343. pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
  344. hose->region_count++;
  345. /* see if we are a PCIe or PCI controller */
  346. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  347. pci_dcr = pcie_cap_pos + 0x08;
  348. pci_dsr = pcie_cap_pos + 0x0a;
  349. pci_lsr = pcie_cap_pos + 0x12;
  350. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  351. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  352. /* boot from PCIE --master */
  353. char *s = env_get("bootmaster");
  354. char pcie[6];
  355. sprintf(pcie, "PCIE%d", pci_info->pci_num);
  356. if (s && (strcmp(s, pcie) == 0)) {
  357. debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
  358. pci_info->pci_num);
  359. fsl_pcie_boot_master((pit_t *)pi);
  360. } else {
  361. /* inbound */
  362. inbound = fsl_pci_setup_inbound_windows(hose,
  363. out_lo, pcie_cap, pi);
  364. }
  365. #else
  366. /* inbound */
  367. inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
  368. #endif
  369. for (r = 0; r < hose->region_count; r++)
  370. debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
  371. (u64)hose->regions[r].phys_start,
  372. (u64)hose->regions[r].bus_start,
  373. (u64)hose->regions[r].size,
  374. hose->regions[r].flags);
  375. pci_register_hose(hose);
  376. pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
  377. hose->current_busno = hose->first_busno;
  378. out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
  379. out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
  380. * - Master abort (pci)
  381. * - Master PERR (pci)
  382. * - ICCA (PCIe)
  383. */
  384. pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
  385. temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
  386. pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
  387. #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
  388. pci_lcr = pcie_cap_pos + 0x10;
  389. temp32 = 0;
  390. pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
  391. temp32 &= ~0x03; /* Disable ASPM */
  392. pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
  393. udelay(1);
  394. #endif
  395. if (pcie_cap == PCI_CAP_ID_EXP) {
  396. if (block_rev >= PEX_IP_BLK_REV_3_0) {
  397. #define PEX_CSR0_LTSSM_MASK 0xFC
  398. #define PEX_CSR0_LTSSM_SHIFT 2
  399. ltssm = (in_be32(&pci->pex_csr0)
  400. & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
  401. enabled = (ltssm == 0x11) ? 1 : 0;
  402. #ifdef CONFIG_FSL_PCIE_RESET
  403. int i;
  404. /* assert PCIe reset */
  405. setbits_be32(&pci->pdb_stat, 0x08000000);
  406. (void) in_be32(&pci->pdb_stat);
  407. udelay(1000);
  408. /* clear PCIe reset */
  409. clrbits_be32(&pci->pdb_stat, 0x08000000);
  410. asm("sync;isync");
  411. for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
  412. pci_hose_read_config_word(hose, dev, PCI_LTSSM,
  413. &ltssm);
  414. udelay(1000);
  415. }
  416. #endif
  417. } else {
  418. /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
  419. /* enabled = ltssm >= PCI_LTSSM_L0; */
  420. pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
  421. enabled = ltssm >= PCI_LTSSM_L0;
  422. #ifdef CONFIG_FSL_PCIE_RESET
  423. if (ltssm == 1) {
  424. int i;
  425. debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
  426. /* assert PCIe reset */
  427. setbits_be32(&pci->pdb_stat, 0x08000000);
  428. (void) in_be32(&pci->pdb_stat);
  429. udelay(100);
  430. debug(" Asserting PCIe reset @%p = %x\n",
  431. &pci->pdb_stat, in_be32(&pci->pdb_stat));
  432. /* clear PCIe reset */
  433. clrbits_be32(&pci->pdb_stat, 0x08000000);
  434. asm("sync;isync");
  435. for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
  436. pci_hose_read_config_word(hose, dev, PCI_LTSSM,
  437. &ltssm);
  438. udelay(1000);
  439. debug("....PCIe link error. "
  440. "LTSSM=0x%02x.\n", ltssm);
  441. }
  442. enabled = ltssm >= PCI_LTSSM_L0;
  443. /* we need to re-write the bar0 since a reset will
  444. * clear it
  445. */
  446. pci_hose_write_config_dword(hose, dev,
  447. PCI_BASE_ADDRESS_0, pcicsrbar);
  448. }
  449. #endif
  450. }
  451. #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  452. if (enabled == 0) {
  453. serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  454. temp32 = in_be32(&srds_regs->srdspccr0);
  455. if ((temp32 >> 28) == 3) {
  456. int i;
  457. out_be32(&srds_regs->srdspccr0, 2 << 28);
  458. setbits_be32(&pci->pdb_stat, 0x08000000);
  459. in_be32(&pci->pdb_stat);
  460. udelay(100);
  461. clrbits_be32(&pci->pdb_stat, 0x08000000);
  462. asm("sync;isync");
  463. for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
  464. pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
  465. udelay(1000);
  466. }
  467. enabled = ltssm >= PCI_LTSSM_L0;
  468. }
  469. }
  470. #endif
  471. if (!enabled) {
  472. /* Let the user know there's no PCIe link for root
  473. * complex. for endpoint, the link may not setup, so
  474. * print undetermined.
  475. */
  476. if (fsl_is_pci_agent(hose))
  477. printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
  478. else
  479. printf("no link, regs @ 0x%lx\n", pci_info->regs);
  480. hose->last_busno = hose->first_busno;
  481. return;
  482. }
  483. out_be32(&pci->pme_msg_det, 0xffffffff);
  484. out_be32(&pci->pme_msg_int_en, 0xffffffff);
  485. /* Print the negotiated PCIe link width */
  486. pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
  487. printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
  488. (temp16 & 0xf), pci_info->regs);
  489. hose->current_busno++; /* Start scan with secondary */
  490. pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
  491. }
  492. #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
  493. /* The Read-Only Write Enable bit defaults to 1 instead of 0.
  494. * Set to 0 to protect the read-only registers.
  495. */
  496. clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
  497. #endif
  498. /* Use generic setup_device to initialize standard pci regs,
  499. * but do not allocate any windows since any BAR found (such
  500. * as PCSRBAR) is not in this cpu's memory space.
  501. */
  502. pciauto_setup_device(hose, dev, 0, hose->pci_mem,
  503. hose->pci_prefetch, hose->pci_io);
  504. if (inbound) {
  505. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
  506. pci_hose_write_config_word(hose, dev, PCI_COMMAND,
  507. temp16 | PCI_COMMAND_MEMORY);
  508. }
  509. #ifndef CONFIG_PCI_NOSCAN
  510. if (!fsl_is_pci_agent(hose)) {
  511. debug(" Scanning PCI bus %02x\n",
  512. hose->current_busno);
  513. hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
  514. } else {
  515. debug(" Not scanning PCI bus %02x. PI=%x\n",
  516. hose->current_busno, temp8);
  517. hose->last_busno = hose->current_busno;
  518. }
  519. /* if we are PCIe - update limit regs and subordinate busno
  520. * for the virtual P2P bridge
  521. */
  522. if (pcie_cap == PCI_CAP_ID_EXP) {
  523. pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
  524. }
  525. #else
  526. hose->last_busno = hose->current_busno;
  527. #endif
  528. /* Clear all error indications */
  529. if (pcie_cap == PCI_CAP_ID_EXP)
  530. out_be32(&pci->pme_msg_det, 0xffffffff);
  531. out_be32(&pci->pedr, 0xffffffff);
  532. pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
  533. if (temp16) {
  534. pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
  535. }
  536. pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
  537. if (temp16) {
  538. pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
  539. }
  540. }
  541. int fsl_is_pci_agent(struct pci_controller *hose)
  542. {
  543. int pcie_cap_pos;
  544. u8 pcie_cap;
  545. pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
  546. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  547. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  548. if (pcie_cap == PCI_CAP_ID_EXP) {
  549. u8 header_type;
  550. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
  551. &header_type);
  552. return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
  553. } else {
  554. u8 prog_if;
  555. pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
  556. /* Programming Interface (PCI_CLASS_PROG)
  557. * 0 == pci host or pcie root-complex,
  558. * 1 == pci agent or pcie end-point
  559. */
  560. return (prog_if == FSL_PROG_IF_AGENT);
  561. }
  562. }
  563. int fsl_pci_init_port(struct fsl_pci_info *pci_info,
  564. struct pci_controller *hose, int busno)
  565. {
  566. volatile ccsr_fsl_pci_t *pci;
  567. struct pci_region *r;
  568. pci_dev_t dev = PCI_BDF(busno,0,0);
  569. int pcie_cap_pos;
  570. u8 pcie_cap;
  571. pci = (ccsr_fsl_pci_t *) pci_info->regs;
  572. /* on non-PCIe controllers we don't have pme_msg_det so this code
  573. * should do nothing since the read will return 0
  574. */
  575. if (in_be32(&pci->pme_msg_det)) {
  576. out_be32(&pci->pme_msg_det, 0xffffffff);
  577. debug (" with errors. Clearing. Now 0x%08x",
  578. pci->pme_msg_det);
  579. }
  580. r = hose->regions + hose->region_count;
  581. /* outbound memory */
  582. pci_set_region(r++,
  583. pci_info->mem_bus,
  584. pci_info->mem_phys,
  585. pci_info->mem_size,
  586. PCI_REGION_MEM);
  587. /* outbound io */
  588. pci_set_region(r++,
  589. pci_info->io_bus,
  590. pci_info->io_phys,
  591. pci_info->io_size,
  592. PCI_REGION_IO);
  593. hose->region_count = r - hose->regions;
  594. hose->first_busno = busno;
  595. fsl_pci_init(hose, pci_info);
  596. if (fsl_is_pci_agent(hose)) {
  597. fsl_pci_config_unlock(hose);
  598. hose->last_busno = hose->first_busno;
  599. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  600. } else {
  601. /* boot from PCIE --master releases slave's core 0 */
  602. char *s = env_get("bootmaster");
  603. char pcie[6];
  604. sprintf(pcie, "PCIE%d", pci_info->pci_num);
  605. if (s && (strcmp(s, pcie) == 0))
  606. fsl_pcie_boot_master_release_slave(pci_info->pci_num);
  607. #endif
  608. }
  609. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  610. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  611. printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
  612. "e" : "", pci_info->pci_num,
  613. hose->first_busno, hose->last_busno);
  614. return(hose->last_busno + 1);
  615. }
  616. /* Enable inbound PCI config cycles for agent/endpoint interface */
  617. void fsl_pci_config_unlock(struct pci_controller *hose)
  618. {
  619. pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
  620. int pcie_cap_pos;
  621. u8 pcie_cap;
  622. u16 pbfr;
  623. if (!fsl_is_pci_agent(hose))
  624. return;
  625. pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
  626. pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
  627. if (pcie_cap != 0x0) {
  628. ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
  629. u32 block_rev = in_be32(&pci->block_rev1);
  630. /* PCIe - set CFG_READY bit of Configuration Ready Register */
  631. if (block_rev >= PEX_IP_BLK_REV_3_0)
  632. setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
  633. else
  634. pci_hose_write_config_byte(hose, dev,
  635. FSL_PCIE_CFG_RDY, 0x1);
  636. } else {
  637. /* PCI - clear ACL bit of PBFR */
  638. pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
  639. pbfr &= ~0x20;
  640. pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
  641. }
  642. }
  643. #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
  644. defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
  645. int fsl_configure_pcie(struct fsl_pci_info *info,
  646. struct pci_controller *hose,
  647. const char *connected, int busno)
  648. {
  649. int is_endpoint;
  650. set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
  651. set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
  652. is_endpoint = fsl_setup_hose(hose, info->regs);
  653. printf("PCIe%u: %s", info->pci_num,
  654. is_endpoint ? "Endpoint" : "Root Complex");
  655. if (connected)
  656. printf(" of %s", connected);
  657. puts(", ");
  658. return fsl_pci_init_port(info, hose, busno);
  659. }
  660. #if defined(CONFIG_FSL_CORENET)
  661. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  662. #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
  663. #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
  664. #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
  665. #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
  666. #else
  667. #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
  668. #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
  669. #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
  670. #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
  671. #endif
  672. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
  673. #elif defined(CONFIG_MPC85xx)
  674. #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
  675. #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
  676. #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
  677. #define _DEVDISR_PCIE4 0
  678. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
  679. #elif defined(CONFIG_MPC86xx)
  680. #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
  681. #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
  682. #define _DEVDISR_PCIE3 0
  683. #define _DEVDISR_PCIE4 0
  684. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
  685. (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
  686. #else
  687. #error "No defines for DEVDISR_PCIE"
  688. #endif
  689. /* Implement a dummy function for those platforms w/o SERDES */
  690. static const char *__board_serdes_name(enum srds_prtcl device)
  691. {
  692. switch (device) {
  693. #ifdef CONFIG_SYS_PCIE1_NAME
  694. case PCIE1:
  695. return CONFIG_SYS_PCIE1_NAME;
  696. #endif
  697. #ifdef CONFIG_SYS_PCIE2_NAME
  698. case PCIE2:
  699. return CONFIG_SYS_PCIE2_NAME;
  700. #endif
  701. #ifdef CONFIG_SYS_PCIE3_NAME
  702. case PCIE3:
  703. return CONFIG_SYS_PCIE3_NAME;
  704. #endif
  705. #ifdef CONFIG_SYS_PCIE4_NAME
  706. case PCIE4:
  707. return CONFIG_SYS_PCIE4_NAME;
  708. #endif
  709. default:
  710. return NULL;
  711. }
  712. return NULL;
  713. }
  714. __attribute__((weak, alias("__board_serdes_name"))) const char *
  715. board_serdes_name(enum srds_prtcl device);
  716. static u32 devdisr_mask[] = {
  717. _DEVDISR_PCIE1,
  718. _DEVDISR_PCIE2,
  719. _DEVDISR_PCIE3,
  720. _DEVDISR_PCIE4,
  721. };
  722. int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
  723. struct fsl_pci_info *pci_info)
  724. {
  725. struct pci_controller *hose;
  726. int num = dev - PCIE1;
  727. hose = calloc(1, sizeof(struct pci_controller));
  728. if (!hose)
  729. return busno;
  730. if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
  731. busno = fsl_configure_pcie(pci_info, hose,
  732. board_serdes_name(dev), busno);
  733. } else {
  734. printf("PCIe%d: disabled\n", num + 1);
  735. }
  736. return busno;
  737. }
  738. int fsl_pcie_init_board(int busno)
  739. {
  740. struct fsl_pci_info pci_info;
  741. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
  742. u32 devdisr;
  743. u32 *addr;
  744. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  745. addr = &gur->devdisr3;
  746. #else
  747. addr = &gur->devdisr;
  748. #endif
  749. devdisr = in_be32(addr);
  750. #ifdef CONFIG_PCIE1
  751. SET_STD_PCIE_INFO(pci_info, 1);
  752. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
  753. #else
  754. setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
  755. #endif
  756. #ifdef CONFIG_PCIE2
  757. SET_STD_PCIE_INFO(pci_info, 2);
  758. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
  759. #else
  760. setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
  761. #endif
  762. #ifdef CONFIG_PCIE3
  763. SET_STD_PCIE_INFO(pci_info, 3);
  764. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
  765. #else
  766. setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
  767. #endif
  768. #ifdef CONFIG_PCIE4
  769. SET_STD_PCIE_INFO(pci_info, 4);
  770. busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
  771. #else
  772. setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
  773. #endif
  774. return busno;
  775. }
  776. #else
  777. int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
  778. struct fsl_pci_info *pci_info)
  779. {
  780. return busno;
  781. }
  782. int fsl_pcie_init_board(int busno)
  783. {
  784. return busno;
  785. }
  786. #endif
  787. #ifdef CONFIG_OF_BOARD_SETUP
  788. #include <linux/libfdt.h>
  789. #include <fdt_support.h>
  790. void ft_fsl_pci_setup(void *blob, const char *pci_compat,
  791. unsigned long ctrl_addr)
  792. {
  793. int off;
  794. u32 bus_range[2];
  795. phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
  796. struct pci_controller *hose;
  797. hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
  798. /* convert ctrl_addr to true physical address */
  799. p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
  800. p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
  801. off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
  802. if (off < 0)
  803. return;
  804. /* We assume a cfg_addr not being set means we didn't setup the controller */
  805. if ((hose == NULL) || (hose->cfg_addr == NULL)) {
  806. fdt_del_node(blob, off);
  807. } else {
  808. bus_range[0] = 0;
  809. bus_range[1] = hose->last_busno - hose->first_busno;
  810. fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
  811. fdt_pci_dma_ranges(blob, off, hose);
  812. }
  813. }
  814. #endif