board.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  4. *
  5. * (C) Copyright 2007-2011
  6. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  7. * Tom Cubie <tangliang@allwinnertech.com>
  8. *
  9. * Some init for sunxi platform.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <init.h>
  14. #include <log.h>
  15. #include <mmc.h>
  16. #include <i2c.h>
  17. #include <serial.h>
  18. #include <spl.h>
  19. #include <asm/cache.h>
  20. #include <asm/gpio.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/arch/spl.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <asm/arch/timer.h>
  27. #include <asm/arch/tzpc.h>
  28. #include <asm/arch/mmc.h>
  29. #include <linux/compiler.h>
  30. struct fel_stash {
  31. uint32_t sp;
  32. uint32_t lr;
  33. uint32_t cpsr;
  34. uint32_t sctlr;
  35. uint32_t vbar;
  36. uint32_t cr;
  37. };
  38. struct fel_stash fel_stash __section(".data");
  39. #ifdef CONFIG_ARM64
  40. #include <asm/armv8/mmu.h>
  41. static struct mm_region sunxi_mem_map[] = {
  42. {
  43. /* SRAM, MMIO regions */
  44. .virt = 0x0UL,
  45. .phys = 0x0UL,
  46. .size = 0x40000000UL,
  47. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  48. PTE_BLOCK_NON_SHARE
  49. }, {
  50. /* RAM */
  51. .virt = 0x40000000UL,
  52. .phys = 0x40000000UL,
  53. .size = 0xC0000000UL,
  54. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  55. PTE_BLOCK_INNER_SHARE
  56. }, {
  57. /* List terminator */
  58. 0,
  59. }
  60. };
  61. struct mm_region *mem_map = sunxi_mem_map;
  62. #endif
  63. static int gpio_init(void)
  64. {
  65. __maybe_unused uint val;
  66. #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
  67. #if defined(CONFIG_MACH_SUN4I) || \
  68. defined(CONFIG_MACH_SUN7I) || \
  69. defined(CONFIG_MACH_SUN8I_R40)
  70. /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
  71. sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
  72. sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
  73. #endif
  74. #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
  75. sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
  76. sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
  77. #else
  78. sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
  79. sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
  80. #endif
  81. sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
  82. #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
  83. defined(CONFIG_MACH_SUN7I) || \
  84. defined(CONFIG_MACH_SUN8I_R40))
  85. sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
  86. sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
  87. sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
  88. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
  89. sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
  90. sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
  91. sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
  92. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
  93. sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
  94. sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
  95. sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
  96. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
  97. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
  98. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
  99. sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
  100. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
  101. sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
  102. sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
  103. sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
  104. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
  105. sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
  106. sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
  107. sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
  108. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
  109. sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
  110. sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
  111. sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
  112. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
  113. sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
  114. sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
  115. sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
  116. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
  117. sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
  118. sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
  119. sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
  120. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
  121. sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
  122. sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
  123. sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
  124. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
  125. sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
  126. sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
  127. sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
  128. #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
  129. sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
  130. sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
  131. sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
  132. #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
  133. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
  134. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
  135. sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
  136. #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
  137. sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
  138. sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
  139. sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
  140. #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
  141. !defined(CONFIG_MACH_SUN8I_R40)
  142. sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
  143. sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
  144. sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
  145. #else
  146. #error Unsupported console port number. Please fix pin mux settings in board.c
  147. #endif
  148. #ifdef CONFIG_SUN50I_GEN_H6
  149. /* Update PIO power bias configuration by copy hardware detected value */
  150. val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
  151. writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
  152. val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
  153. writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
  154. #endif
  155. return 0;
  156. }
  157. #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
  158. static int spl_board_load_image(struct spl_image_info *spl_image,
  159. struct spl_boot_device *bootdev)
  160. {
  161. debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
  162. return_to_fel(fel_stash.sp, fel_stash.lr);
  163. return 0;
  164. }
  165. SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
  166. #endif
  167. void s_init(void)
  168. {
  169. /*
  170. * Undocumented magic taken from boot0, without this DRAM
  171. * access gets messed up (seems cache related).
  172. * The boot0 sources describe this as: "config ema for cache sram"
  173. */
  174. #if defined CONFIG_MACH_SUN6I
  175. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
  176. #elif defined CONFIG_MACH_SUN8I
  177. __maybe_unused uint version;
  178. /* Unlock sram version info reg, read it, relock */
  179. setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  180. version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
  181. clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  182. /*
  183. * Ideally this would be a switch case, but we do not know exactly
  184. * which versions there are and which version needs which settings,
  185. * so reproduce the per SoC code from the BSP.
  186. */
  187. #if defined CONFIG_MACH_SUN8I_A23
  188. if (version == 0x1650)
  189. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
  190. else /* 0x1661 ? */
  191. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
  192. #elif defined CONFIG_MACH_SUN8I_A33
  193. if (version != 0x1667)
  194. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
  195. #endif
  196. /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
  197. /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
  198. #endif
  199. #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
  200. /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
  201. asm volatile(
  202. "mrc p15, 0, r0, c1, c0, 1\n"
  203. "orr r0, r0, #1 << 6\n"
  204. "mcr p15, 0, r0, c1, c0, 1\n"
  205. ::: "r0");
  206. #endif
  207. #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
  208. /* Enable non-secure access to some peripherals */
  209. tzpc_init();
  210. #endif
  211. clock_init();
  212. timer_init();
  213. gpio_init();
  214. #if !CONFIG_IS_ENABLED(DM_I2C)
  215. i2c_init_board();
  216. #endif
  217. eth_init_board();
  218. }
  219. #define SUNXI_INVALID_BOOT_SOURCE -1
  220. static int sunxi_get_boot_source(void)
  221. {
  222. if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
  223. return SUNXI_INVALID_BOOT_SOURCE;
  224. return readb(SPL_ADDR + 0x28);
  225. }
  226. /* The sunxi internal brom will try to loader external bootloader
  227. * from mmc0, nand flash, mmc2.
  228. */
  229. uint32_t sunxi_get_boot_device(void)
  230. {
  231. int boot_source = sunxi_get_boot_source();
  232. /*
  233. * When booting from the SD card or NAND memory, the "eGON.BT0"
  234. * signature is expected to be found in memory at the address 0x0004
  235. * (see the "mksunxiboot" tool, which generates this header).
  236. *
  237. * When booting in the FEL mode over USB, this signature is patched in
  238. * memory and replaced with something else by the 'fel' tool. This other
  239. * signature is selected in such a way, that it can't be present in a
  240. * valid bootable SD card image (because the BROM would refuse to
  241. * execute the SPL in this case).
  242. *
  243. * This checks for the signature and if it is not found returns to
  244. * the FEL code in the BROM to wait and receive the main u-boot
  245. * binary over USB. If it is found, it determines where SPL was
  246. * read from.
  247. */
  248. switch (boot_source) {
  249. case SUNXI_INVALID_BOOT_SOURCE:
  250. return BOOT_DEVICE_BOARD;
  251. case SUNXI_BOOTED_FROM_MMC0:
  252. case SUNXI_BOOTED_FROM_MMC0_HIGH:
  253. return BOOT_DEVICE_MMC1;
  254. case SUNXI_BOOTED_FROM_NAND:
  255. return BOOT_DEVICE_NAND;
  256. case SUNXI_BOOTED_FROM_MMC2:
  257. case SUNXI_BOOTED_FROM_MMC2_HIGH:
  258. return BOOT_DEVICE_MMC2;
  259. case SUNXI_BOOTED_FROM_SPI:
  260. return BOOT_DEVICE_SPI;
  261. }
  262. panic("Unknown boot source %d\n", boot_source);
  263. return -1; /* Never reached */
  264. }
  265. #ifdef CONFIG_SPL_BUILD
  266. static u32 sunxi_get_spl_size(void)
  267. {
  268. if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
  269. return 0;
  270. return readl(SPL_ADDR + 0x10);
  271. }
  272. /*
  273. * The eGON SPL image can be located at 8KB or at 128KB into an SD card or
  274. * an eMMC device. The boot source has bit 4 set in the latter case.
  275. * By adding 120KB to the normal offset when booting from a "high" location
  276. * we can support both cases.
  277. * Also U-Boot proper is located at least 32KB after the SPL, but will
  278. * immediately follow the SPL if that is bigger than that.
  279. */
  280. unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
  281. unsigned long raw_sect)
  282. {
  283. unsigned long spl_size = sunxi_get_spl_size();
  284. unsigned long sector;
  285. sector = max(raw_sect, spl_size / 512);
  286. switch (sunxi_get_boot_source()) {
  287. case SUNXI_BOOTED_FROM_MMC0_HIGH:
  288. case SUNXI_BOOTED_FROM_MMC2_HIGH:
  289. sector += (128 - 8) * 2;
  290. break;
  291. }
  292. return sector;
  293. }
  294. u32 spl_boot_device(void)
  295. {
  296. return sunxi_get_boot_device();
  297. }
  298. void board_init_f(ulong dummy)
  299. {
  300. spl_init();
  301. preloader_console_init();
  302. #ifdef CONFIG_SPL_I2C_SUPPORT
  303. /* Needed early by sunxi_board_init if PMU is enabled */
  304. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  305. #endif
  306. sunxi_board_init();
  307. }
  308. #endif
  309. void reset_cpu(void)
  310. {
  311. #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
  312. static const struct sunxi_wdog *wdog =
  313. &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
  314. /* Set the watchdog for its shortest interval (.5s) and wait */
  315. writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
  316. writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
  317. while (1) {
  318. /* sun5i sometimes gets stuck without this */
  319. writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
  320. }
  321. #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
  322. #if defined(CONFIG_MACH_SUN50I_H6)
  323. /* WDOG is broken for some H6 rev. use the R_WDOG instead */
  324. static const struct sunxi_wdog *wdog =
  325. (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
  326. #else
  327. static const struct sunxi_wdog *wdog =
  328. ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
  329. #endif
  330. /* Set the watchdog for its shortest interval (.5s) and wait */
  331. writel(WDT_CFG_RESET, &wdog->cfg);
  332. writel(WDT_MODE_EN, &wdog->mode);
  333. writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
  334. while (1) { }
  335. #endif
  336. }
  337. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  338. void enable_caches(void)
  339. {
  340. /* Enable D-cache. I-cache is already enabled in start.S */
  341. dcache_enable();
  342. }
  343. #endif