mbus.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
  4. * 370/XP, Dove, Orion5x and MV78xx0)
  5. *
  6. * Ported from the Barebox version to U-Boot by:
  7. * Stefan Roese <sr@denx.de>
  8. *
  9. * The Barebox version is:
  10. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  11. *
  12. * based on mbus driver from Linux
  13. * (C) Copyright 2008 Marvell Semiconductor
  14. *
  15. * The Marvell EBU SoCs have a configurable physical address space:
  16. * the physical address at which certain devices (PCIe, NOR, NAND,
  17. * etc.) sit can be configured. The configuration takes place through
  18. * two sets of registers:
  19. *
  20. * - One to configure the access of the CPU to the devices. Depending
  21. * on the families, there are between 8 and 20 configurable windows,
  22. * each can be use to create a physical memory window that maps to a
  23. * specific device. Devices are identified by a tuple (target,
  24. * attribute).
  25. *
  26. * - One to configure the access to the CPU to the SDRAM. There are
  27. * either 2 (for Dove) or 4 (for other families) windows to map the
  28. * SDRAM into the physical address space.
  29. *
  30. * This driver:
  31. *
  32. * - Reads out the SDRAM address decoding windows at initialization
  33. * time, and fills the mbus_dram_info structure with these
  34. * informations. The exported function mv_mbus_dram_info() allow
  35. * device drivers to get those informations related to the SDRAM
  36. * address decoding windows. This is because devices also have their
  37. * own windows (configured through registers that are part of each
  38. * device register space), and therefore the drivers for Marvell
  39. * devices have to configure those device -> SDRAM windows to ensure
  40. * that DMA works properly.
  41. *
  42. * - Provides an API for platform code or device drivers to
  43. * dynamically add or remove address decoding windows for the CPU ->
  44. * device accesses. This API is mvebu_mbus_add_window_by_id(),
  45. * mvebu_mbus_add_window_remap_by_id() and
  46. * mvebu_mbus_del_window().
  47. */
  48. #include <common.h>
  49. #include <malloc.h>
  50. #include <linux/bitops.h>
  51. #include <linux/errno.h>
  52. #include <asm/io.h>
  53. #include <asm/arch/cpu.h>
  54. #include <asm/arch/soc.h>
  55. #include <linux/log2.h>
  56. #include <linux/mbus.h>
  57. /* DDR target is the same on all platforms */
  58. #define TARGET_DDR 0
  59. /* CPU Address Decode Windows registers */
  60. #define WIN_CTRL_OFF 0x0000
  61. #define WIN_CTRL_ENABLE BIT(0)
  62. #define WIN_CTRL_TGT_MASK 0xf0
  63. #define WIN_CTRL_TGT_SHIFT 4
  64. #define WIN_CTRL_ATTR_MASK 0xff00
  65. #define WIN_CTRL_ATTR_SHIFT 8
  66. #define WIN_CTRL_SIZE_MASK 0xffff0000
  67. #define WIN_CTRL_SIZE_SHIFT 16
  68. #define WIN_BASE_OFF 0x0004
  69. #define WIN_BASE_LOW 0xffff0000
  70. #define WIN_BASE_HIGH 0xf
  71. #define WIN_REMAP_LO_OFF 0x0008
  72. #define WIN_REMAP_LOW 0xffff0000
  73. #define WIN_REMAP_HI_OFF 0x000c
  74. #define ATTR_HW_COHERENCY (0x1 << 4)
  75. #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
  76. #define DDR_BASE_CS_HIGH_MASK 0xf
  77. #define DDR_BASE_CS_LOW_MASK 0xff000000
  78. #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
  79. #define DDR_SIZE_ENABLED BIT(0)
  80. #define DDR_SIZE_CS_MASK 0x1c
  81. #define DDR_SIZE_CS_SHIFT 2
  82. #define DDR_SIZE_MASK 0xff000000
  83. #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
  84. struct mvebu_mbus_state;
  85. struct mvebu_mbus_soc_data {
  86. unsigned int num_wins;
  87. unsigned int num_remappable_wins;
  88. unsigned int (*win_cfg_offset)(const int win);
  89. void (*setup_cpu_target)(struct mvebu_mbus_state *s);
  90. };
  91. struct mvebu_mbus_state mbus_state
  92. __section(".data");
  93. static struct mbus_dram_target_info mbus_dram_info
  94. __section(".data");
  95. /*
  96. * Functions to manipulate the address decoding windows
  97. */
  98. static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
  99. int win, int *enabled, u64 *base,
  100. u32 *size, u8 *target, u8 *attr,
  101. u64 *remap)
  102. {
  103. void __iomem *addr = mbus->mbuswins_base +
  104. mbus->soc->win_cfg_offset(win);
  105. u32 basereg = readl(addr + WIN_BASE_OFF);
  106. u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
  107. if (!(ctrlreg & WIN_CTRL_ENABLE)) {
  108. *enabled = 0;
  109. return;
  110. }
  111. *enabled = 1;
  112. *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
  113. *base |= (basereg & WIN_BASE_LOW);
  114. *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
  115. if (target)
  116. *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
  117. if (attr)
  118. *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
  119. if (remap) {
  120. if (win < mbus->soc->num_remappable_wins) {
  121. u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
  122. u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
  123. *remap = ((u64)remap_hi << 32) | remap_low;
  124. } else {
  125. *remap = 0;
  126. }
  127. }
  128. }
  129. static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
  130. int win)
  131. {
  132. void __iomem *addr;
  133. addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
  134. writel(0, addr + WIN_BASE_OFF);
  135. writel(0, addr + WIN_CTRL_OFF);
  136. if (win < mbus->soc->num_remappable_wins) {
  137. writel(0, addr + WIN_REMAP_LO_OFF);
  138. writel(0, addr + WIN_REMAP_HI_OFF);
  139. }
  140. }
  141. /* Checks whether the given window number is available */
  142. static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
  143. const int win)
  144. {
  145. void __iomem *addr = mbus->mbuswins_base +
  146. mbus->soc->win_cfg_offset(win);
  147. u32 ctrl = readl(addr + WIN_CTRL_OFF);
  148. return !(ctrl & WIN_CTRL_ENABLE);
  149. }
  150. /*
  151. * Checks whether the given (base, base+size) area doesn't overlap an
  152. * existing region
  153. */
  154. static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
  155. phys_addr_t base, size_t size,
  156. u8 target, u8 attr)
  157. {
  158. u64 end = (u64)base + size;
  159. int win;
  160. for (win = 0; win < mbus->soc->num_wins; win++) {
  161. u64 wbase, wend;
  162. u32 wsize;
  163. u8 wtarget, wattr;
  164. int enabled;
  165. mvebu_mbus_read_window(mbus, win,
  166. &enabled, &wbase, &wsize,
  167. &wtarget, &wattr, NULL);
  168. if (!enabled)
  169. continue;
  170. wend = wbase + wsize;
  171. /*
  172. * Check if the current window overlaps with the
  173. * proposed physical range
  174. */
  175. if ((u64)base < wend && end > wbase)
  176. return 0;
  177. /*
  178. * Check if target/attribute conflicts
  179. */
  180. if (target == wtarget && attr == wattr)
  181. return 0;
  182. }
  183. return 1;
  184. }
  185. static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
  186. phys_addr_t base, size_t size)
  187. {
  188. int win;
  189. for (win = 0; win < mbus->soc->num_wins; win++) {
  190. u64 wbase;
  191. u32 wsize;
  192. int enabled;
  193. mvebu_mbus_read_window(mbus, win,
  194. &enabled, &wbase, &wsize,
  195. NULL, NULL, NULL);
  196. if (!enabled)
  197. continue;
  198. if (base == wbase && size == wsize)
  199. return win;
  200. }
  201. return -ENODEV;
  202. }
  203. static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
  204. int win, phys_addr_t base, size_t size,
  205. phys_addr_t remap, u8 target,
  206. u8 attr)
  207. {
  208. void __iomem *addr = mbus->mbuswins_base +
  209. mbus->soc->win_cfg_offset(win);
  210. u32 ctrl, remap_addr;
  211. ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
  212. (attr << WIN_CTRL_ATTR_SHIFT) |
  213. (target << WIN_CTRL_TGT_SHIFT) |
  214. WIN_CTRL_ENABLE;
  215. writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
  216. writel(ctrl, addr + WIN_CTRL_OFF);
  217. if (win < mbus->soc->num_remappable_wins) {
  218. if (remap == MVEBU_MBUS_NO_REMAP)
  219. remap_addr = base;
  220. else
  221. remap_addr = remap;
  222. writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
  223. writel(0, addr + WIN_REMAP_HI_OFF);
  224. }
  225. return 0;
  226. }
  227. static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
  228. phys_addr_t base, size_t size,
  229. phys_addr_t remap, u8 target,
  230. u8 attr)
  231. {
  232. int win;
  233. if (remap == MVEBU_MBUS_NO_REMAP) {
  234. for (win = mbus->soc->num_remappable_wins;
  235. win < mbus->soc->num_wins; win++)
  236. if (mvebu_mbus_window_is_free(mbus, win))
  237. return mvebu_mbus_setup_window(mbus, win, base,
  238. size, remap,
  239. target, attr);
  240. }
  241. for (win = 0; win < mbus->soc->num_wins; win++)
  242. if (mvebu_mbus_window_is_free(mbus, win))
  243. return mvebu_mbus_setup_window(mbus, win, base, size,
  244. remap, target, attr);
  245. return -ENOMEM;
  246. }
  247. /*
  248. * SoC-specific functions and definitions
  249. */
  250. static unsigned int armada_370_xp_mbus_win_offset(int win)
  251. {
  252. /* The register layout is a bit annoying and the below code
  253. * tries to cope with it.
  254. * - At offset 0x0, there are the registers for the first 8
  255. * windows, with 4 registers of 32 bits per window (ctrl,
  256. * base, remap low, remap high)
  257. * - Then at offset 0x80, there is a hole of 0x10 bytes for
  258. * the internal registers base address and internal units
  259. * sync barrier register.
  260. * - Then at offset 0x90, there the registers for 12
  261. * windows, with only 2 registers of 32 bits per window
  262. * (ctrl, base).
  263. */
  264. if (win < 8)
  265. return win << 4;
  266. else
  267. return 0x90 + ((win - 8) << 3);
  268. }
  269. static unsigned int orion5x_mbus_win_offset(int win)
  270. {
  271. return win << 4;
  272. }
  273. static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
  274. {
  275. int i;
  276. int cs;
  277. mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
  278. for (i = 0, cs = 0; i < 4; i++) {
  279. u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
  280. u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
  281. /*
  282. * We only take care of entries for which the chip
  283. * select is enabled, and that don't have high base
  284. * address bits set (devices can only access the first
  285. * 32 bits of the memory).
  286. */
  287. if ((size & DDR_SIZE_ENABLED) &&
  288. !(base & DDR_BASE_CS_HIGH_MASK)) {
  289. struct mbus_dram_window *w;
  290. w = &mbus_dram_info.cs[cs++];
  291. w->cs_index = i;
  292. w->mbus_attr = 0xf & ~(1 << i);
  293. w->base = base & DDR_BASE_CS_LOW_MASK;
  294. w->size = (size | ~DDR_SIZE_MASK) + 1;
  295. }
  296. }
  297. mbus_dram_info.num_cs = cs;
  298. #if defined(CONFIG_ARMADA_MSYS)
  299. /* Disable MBUS Err Prop - in order to avoid data aborts */
  300. clrbits_le32(mbus->mbuswins_base + 0x200, BIT(8));
  301. #endif
  302. }
  303. static const struct mvebu_mbus_soc_data
  304. armada_370_xp_mbus_data __maybe_unused = {
  305. .num_wins = 20,
  306. .num_remappable_wins = 8,
  307. .win_cfg_offset = armada_370_xp_mbus_win_offset,
  308. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  309. };
  310. static const struct mvebu_mbus_soc_data
  311. kirkwood_mbus_data __maybe_unused = {
  312. .num_wins = 8,
  313. .num_remappable_wins = 4,
  314. .win_cfg_offset = orion5x_mbus_win_offset,
  315. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  316. };
  317. /*
  318. * Public API of the driver
  319. */
  320. const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
  321. {
  322. return &mbus_dram_info;
  323. }
  324. int mvebu_mbus_add_window_remap_by_id(unsigned int target,
  325. unsigned int attribute,
  326. phys_addr_t base, size_t size,
  327. phys_addr_t remap)
  328. {
  329. struct mvebu_mbus_state *s = &mbus_state;
  330. if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
  331. printf("Cannot add window '%x:%x', conflicts with another window\n",
  332. target, attribute);
  333. return -EINVAL;
  334. }
  335. return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
  336. }
  337. int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
  338. phys_addr_t base, size_t size)
  339. {
  340. return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
  341. size, MVEBU_MBUS_NO_REMAP);
  342. }
  343. int mvebu_mbus_del_window(phys_addr_t base, size_t size)
  344. {
  345. int win;
  346. win = mvebu_mbus_find_window(&mbus_state, base, size);
  347. if (win < 0)
  348. return win;
  349. mvebu_mbus_disable_window(&mbus_state, win);
  350. return 0;
  351. }
  352. #ifndef CONFIG_ARCH_KIRKWOOD
  353. static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus,
  354. phys_addr_t *base)
  355. {
  356. int win;
  357. *base = 0xffffffff;
  358. for (win = 0; win < mbus->soc->num_wins; win++) {
  359. u64 wbase;
  360. u32 wsize;
  361. u8 wtarget, wattr;
  362. int enabled;
  363. mvebu_mbus_read_window(mbus, win,
  364. &enabled, &wbase, &wsize,
  365. &wtarget, &wattr, NULL);
  366. if (!enabled)
  367. continue;
  368. if (wbase < *base)
  369. *base = wbase;
  370. }
  371. }
  372. static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus)
  373. {
  374. phys_addr_t base;
  375. u32 val;
  376. u32 size;
  377. /* Set MBUS bridge base/ctrl */
  378. mvebu_mbus_get_lowest_base(&mbus_state, &base);
  379. size = 0xffffffff - base + 1;
  380. if (!is_power_of_2(size)) {
  381. /* Round up to next power of 2 */
  382. size = 1 << (ffs(base) + 1);
  383. base = 0xffffffff - size + 1;
  384. }
  385. /* Now write base and size */
  386. writel(base, MBUS_BRIDGE_WIN_BASE_REG);
  387. /* Align window size to 64KiB */
  388. val = (size / (64 << 10)) - 1;
  389. writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG);
  390. }
  391. #endif
  392. int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
  393. u32 base, u32 size, u8 target, u8 attr)
  394. {
  395. if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
  396. printf("Cannot add window '%04x:%04x', conflicts with another window\n",
  397. target, attr);
  398. return -EBUSY;
  399. }
  400. /*
  401. * In U-Boot we first try to add the mbus window to the remap windows.
  402. * If this fails, lets try to add the windows to the non-remap windows.
  403. */
  404. if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
  405. if (mvebu_mbus_alloc_window(mbus, base, size,
  406. MVEBU_MBUS_NO_REMAP, target, attr))
  407. return -ENOMEM;
  408. }
  409. #ifndef CONFIG_ARCH_KIRKWOOD
  410. /*
  411. * Re-configure the mbus bridge registers each time this function
  412. * is called. Since it may get called from the board code in
  413. * later boot stages as well.
  414. */
  415. mvebu_config_mbus_bridge(mbus);
  416. #endif
  417. return 0;
  418. }
  419. int mvebu_mbus_probe(struct mbus_win windows[], int count)
  420. {
  421. int win;
  422. int ret;
  423. int i;
  424. #if defined(CONFIG_ARCH_KIRKWOOD)
  425. mbus_state.soc = &kirkwood_mbus_data;
  426. #endif
  427. #if defined(CONFIG_ARCH_MVEBU)
  428. mbus_state.soc = &armada_370_xp_mbus_data;
  429. #endif
  430. mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
  431. mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
  432. for (win = 0; win < mbus_state.soc->num_wins; win++)
  433. mvebu_mbus_disable_window(&mbus_state, win);
  434. mbus_state.soc->setup_cpu_target(&mbus_state);
  435. /* Setup statically declared windows in the DT */
  436. for (i = 0; i < count; i++) {
  437. u32 base, size;
  438. u8 target, attr;
  439. target = windows[i].target;
  440. attr = windows[i].attr;
  441. base = windows[i].base;
  442. size = windows[i].size;
  443. ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);
  444. if (ret < 0)
  445. return ret;
  446. }
  447. return 0;
  448. }