ls102xa_psci.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
  5. * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
  6. */
  7. #include <config.h>
  8. #include <cpu_func.h>
  9. #include <asm/io.h>
  10. #include <asm/psci.h>
  11. #include <asm/arch/immap_ls102xa.h>
  12. #include <fsl_immap.h>
  13. #include "fsl_epu.h"
  14. #define __secure __section("._secure.text")
  15. #define CCSR_GICD_CTLR 0x1000
  16. #define CCSR_GICC_CTLR 0x2000
  17. #define DCSR_RCPM_CG1CR0 0x31c
  18. #define DCSR_RCPM_CSTTACR0 0xb00
  19. #define DCFG_CRSTSR_WDRFR 0x8
  20. #define DDR_RESV_LEN 128
  21. #ifdef CONFIG_LS1_DEEP_SLEEP
  22. /*
  23. * DDR controller initialization training breaks the first 128 bytes of DDR,
  24. * save them so that the bootloader can restore them while resuming.
  25. */
  26. static void __secure ls1_save_ddr_head(void)
  27. {
  28. const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
  29. char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
  30. struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  31. int i;
  32. out_le32(&scfg->sparecr[2], dest);
  33. for (i = 0; i < DDR_RESV_LEN; i++)
  34. *dest++ = *src++;
  35. }
  36. static void __secure ls1_fsm_setup(void)
  37. {
  38. void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
  39. void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
  40. out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
  41. out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
  42. fsl_epu_setup((void *)dcsr_epu_base);
  43. /* Pull MCKE signal low before enabling deep sleep signal in FPGA */
  44. out_be32(dcsr_epu_base + EPECR0, 0x5);
  45. out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
  46. }
  47. static void __secure ls1_deepsleep_irq_cfg(void)
  48. {
  49. struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  50. struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
  51. u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
  52. /* Mask interrupts from GIC */
  53. out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
  54. out_be32(&rcpm->nirqoutr, 0x0ffffffff);
  55. /* Mask deep sleep wake-up interrupts while entering deep sleep */
  56. out_be32(&rcpm->dsimskr, 0x0ffffffff);
  57. ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
  58. /*
  59. * Workaround of errata A-008646
  60. * Errata states that read to register ippdexpcr1 always returns
  61. * zero irrespective of what value is written into it. So its value
  62. * is first saved to a spare register and then read from it
  63. */
  64. ippdexpcr1 = in_be32(&scfg->sparecr[7]);
  65. /*
  66. * To allow OCRAM to be used as wakeup source in deep sleep,
  67. * do not power it down.
  68. */
  69. out_be32(&rcpm->ippdexpcr1, ippdexpcr1 | RCPM_IPPDEXPCR1_OCRAM1);
  70. if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
  71. pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
  72. SCFG_PMCINTECR_ETSECRXG1 |
  73. SCFG_PMCINTECR_ETSECERRG0 |
  74. SCFG_PMCINTECR_ETSECERRG1;
  75. if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
  76. pmcintecr |= SCFG_PMCINTECR_GPIO;
  77. if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
  78. pmcintecr |= SCFG_PMCINTECR_LPUART;
  79. if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
  80. pmcintecr |= SCFG_PMCINTECR_FTM;
  81. /* Always set external IRQ pins as wakeup source */
  82. pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
  83. out_be32(&scfg->pmcintlecr, 0);
  84. /* Clear PMC interrupt status */
  85. out_be32(&scfg->pmcintsr, 0xffffffff);
  86. /* Enable wakeup interrupt during deep sleep */
  87. out_be32(&scfg->pmcintecr, pmcintecr);
  88. }
  89. static void __secure ls1_delay(unsigned int loop)
  90. {
  91. while (loop--) {
  92. int i = 1000;
  93. while (i--)
  94. ;
  95. }
  96. }
  97. static void __secure ls1_start_fsm(void)
  98. {
  99. void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
  100. void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
  101. struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  102. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  103. /* Set HRSTCR */
  104. setbits_be32(&scfg->hrstcr, 0x80000000);
  105. /* Place DDR controller in self refresh mode */
  106. setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
  107. ls1_delay(2000);
  108. /* Set EVT4_B to lock the signal MCKE down */
  109. out_be32(dcsr_epu_base + EPECR0, 0x0);
  110. ls1_delay(2000);
  111. out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
  112. out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
  113. /* Enable all EPU Counters */
  114. setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
  115. /* Enable SCU15 */
  116. setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
  117. /* Enter WFI mode, and EPU FSM will start */
  118. __asm__ __volatile__ ("wfi" : : : "memory");
  119. /* NEVER ENTER HERE */
  120. while (1)
  121. ;
  122. }
  123. static void __secure ls1_deep_sleep(u32 entry_point)
  124. {
  125. struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  126. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  127. struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
  128. #ifdef QIXIS_BASE
  129. u32 tmp;
  130. void *qixis_base = (void *)QIXIS_BASE;
  131. #endif
  132. /* Enable cluster to enter the PCL10 state */
  133. out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
  134. /* Save the first 128 bytes of DDR data */
  135. ls1_save_ddr_head();
  136. /* Save the kernel resume entry */
  137. out_le32(&scfg->sparecr[3], entry_point);
  138. /* Request to put cluster 0 in PCL10 state */
  139. setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
  140. /* Setup the registers of the EPU FSM for deep sleep */
  141. ls1_fsm_setup();
  142. #ifdef QIXIS_BASE
  143. /* Connect the EVENT button to IRQ in FPGA */
  144. tmp = in_8(qixis_base + QIXIS_CTL_SYS);
  145. tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
  146. tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
  147. out_8(qixis_base + QIXIS_CTL_SYS, tmp);
  148. /* Enable deep sleep signals in FPGA */
  149. tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
  150. tmp |= QIXIS_PWR_CTL2_PCTL;
  151. out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
  152. /* Pull down PCIe RST# */
  153. tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
  154. tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
  155. out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
  156. #endif
  157. /* Enable Warm Device Reset */
  158. setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
  159. setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
  160. /* Disable QE */
  161. setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE);
  162. ls1_deepsleep_irq_cfg();
  163. psci_v7_flush_dcache_all();
  164. ls1_start_fsm();
  165. }
  166. #else
  167. static void __secure ls1_sleep(void)
  168. {
  169. struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  170. struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
  171. #ifdef QIXIS_BASE
  172. u32 tmp;
  173. void *qixis_base = (void *)QIXIS_BASE;
  174. /* Connect the EVENT button to IRQ in FPGA */
  175. tmp = in_8(qixis_base + QIXIS_CTL_SYS);
  176. tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
  177. tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
  178. out_8(qixis_base + QIXIS_CTL_SYS, tmp);
  179. #endif
  180. /* Enable cluster to enter the PCL10 state */
  181. out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
  182. setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
  183. __asm__ __volatile__ ("wfi" : : : "memory");
  184. }
  185. #endif
  186. void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
  187. {
  188. #ifdef CONFIG_LS1_DEEP_SLEEP
  189. ls1_deep_sleep(entry_point);
  190. #else
  191. ls1_sleep();
  192. #endif
  193. }