cpu_spl.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Google LLC
  4. *
  5. * Portions taken from coreboot
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <ec_commands.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <spi_flash.h>
  13. #include <spl.h>
  14. #include <syscon.h>
  15. #include <acpi/acpi_s3.h>
  16. #include <asm/cpu.h>
  17. #include <asm/cpu_common.h>
  18. #include <asm/cpu_x86.h>
  19. #include <asm/fast_spi.h>
  20. #include <asm/global_data.h>
  21. #include <asm/intel_pinctrl.h>
  22. #include <asm/intel_regs.h>
  23. #include <asm/io.h>
  24. #include <asm/msr.h>
  25. #include <asm/mtrr.h>
  26. #include <asm/pci.h>
  27. #include <asm/arch/cpu.h>
  28. #include <asm/arch/gpio.h>
  29. #include <asm/arch/iomap.h>
  30. #include <asm/arch/lpc.h>
  31. #include <asm/arch/pch.h>
  32. #include <asm/arch/systemagent.h>
  33. #include <asm/arch/uart.h>
  34. #include <asm/fsp2/fsp_api.h>
  35. #include <linux/sizes.h>
  36. #include <power/acpi_pmc.h>
  37. /* Define this here to avoid referencing any drivers for the debug UART 1 */
  38. #define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0)
  39. static void pch_uart_init(void)
  40. {
  41. /*
  42. * Set up the pinmux so that the UART rx/tx signals are connected
  43. * outside the SoC.
  44. *
  45. * There are about 500 lines of code required to program the GPIO
  46. * configuration for the UARTs. But it boils down to four writes, and
  47. * for the debug UART we want the minimum possible amount of code before
  48. * the UART is running. So just add the magic writes here. See
  49. * apl_hostbridge_early_init_pinctrl() for the full horror.
  50. */
  51. if (PCI_FUNC(PCH_DEV_UART) == 1) {
  52. writel(0x40000402, 0xd0c50650);
  53. writel(0x3c47, 0xd0c50654);
  54. writel(0x40000400, 0xd0c50658);
  55. writel(0x3c48, 0xd0c5065c);
  56. } else { /* UART2 */
  57. writel(0x40000402, 0xd0c50670);
  58. writel(0x3c4b, 0xd0c50674);
  59. writel(0x40000400, 0xd0c50678);
  60. writel(0x3c4c, 0xd0c5067c);
  61. }
  62. #ifdef CONFIG_DEBUG_UART
  63. apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
  64. #endif
  65. }
  66. static void p2sb_enable_bar(ulong bar)
  67. {
  68. /* Enable PCR Base address in PCH */
  69. pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
  70. PCI_SIZE_32);
  71. pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
  72. /* Enable P2SB MSE */
  73. pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
  74. PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
  75. PCI_SIZE_8);
  76. }
  77. /*
  78. * board_debug_uart_init() - Init the debug UART ready for use
  79. *
  80. * This is the minimum init needed to get the UART running. It avoids any
  81. * drivers or complex code, so that the UART is running as soon as possible.
  82. */
  83. void board_debug_uart_init(void)
  84. {
  85. p2sb_enable_bar(IOMAP_P2SB_BAR);
  86. pch_uart_init();
  87. }
  88. static int fast_spi_cache_bios_region(void)
  89. {
  90. uint map_size, offset;
  91. ulong map_base, base;
  92. int ret;
  93. ret = fast_spi_early_init(PCH_DEV_SPI, IOMAP_SPI_BASE);
  94. if (ret)
  95. return log_msg_ret("early_init", ret);
  96. ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
  97. &offset);
  98. if (ret)
  99. return log_msg_ret("get_mmap", ret);
  100. base = SZ_4G - map_size;
  101. mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
  102. log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
  103. return 0;
  104. }
  105. static void google_chromeec_ioport_range(uint *out_basep, uint *out_sizep)
  106. {
  107. uint base;
  108. uint size;
  109. if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
  110. base = MEC_EMI_BASE;
  111. size = MEC_EMI_SIZE;
  112. } else {
  113. base = EC_HOST_CMD_REGION0;
  114. size = 2 * EC_HOST_CMD_REGION_SIZE;
  115. /* Make sure MEMMAP region follows host cmd region */
  116. assert(base + size == EC_LPC_ADDR_MEMMAP);
  117. size += EC_MEMMAP_SIZE;
  118. }
  119. *out_basep = base;
  120. *out_sizep = size;
  121. }
  122. static void early_ec_init(void)
  123. {
  124. uint base, size;
  125. /*
  126. * Set up LPC decoding for the Chrome OS EC I/O port ranges:
  127. * - Ports 62/66, 60/64, and 200->208
  128. * - Chrome OS EC communication I/O ports
  129. */
  130. lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 |
  131. LPC_IOE_LGE_200);
  132. google_chromeec_ioport_range(&base, &size);
  133. lpc_open_pmio_window(base, size);
  134. }
  135. static int arch_cpu_init_tpl(void)
  136. {
  137. struct udevice *pmc, *sa, *p2sb, *serial, *spi, *lpc;
  138. int ret;
  139. ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
  140. if (ret)
  141. return log_msg_ret("PMC", ret);
  142. /* Clear global reset promotion bit */
  143. ret = pmc_global_reset_set_enable(pmc, false);
  144. if (ret)
  145. return log_msg_ret("disable global reset", ret);
  146. enable_pm_timer_emulation(pmc);
  147. ret = uclass_first_device_err(UCLASS_P2SB, &p2sb);
  148. if (ret)
  149. return log_msg_ret("p2sb", ret);
  150. ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa);
  151. if (ret)
  152. return log_msg_ret("northbridge", ret);
  153. gd->baudrate = CONFIG_BAUDRATE;
  154. ret = uclass_first_device_err(UCLASS_SERIAL, &serial);
  155. if (ret)
  156. return log_msg_ret("serial", ret);
  157. if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
  158. ret = uclass_first_device_err(UCLASS_SPI, &spi);
  159. if (ret)
  160. return log_msg_ret("SPI", ret);
  161. } else {
  162. /* Alternative code if we don't have SPI in TPL */
  163. if (IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH))
  164. printf("Warning: Enable APL_SPI_FLASHBOOT to use SPI-flash driver in TPL");
  165. ret = fast_spi_cache_bios_region();
  166. if (ret)
  167. return log_msg_ret("BIOS cache", ret);
  168. }
  169. ret = pmc_disable_tco(pmc);
  170. if (ret)
  171. return log_msg_ret("disable TCO", ret);
  172. ret = pmc_gpe_init(pmc);
  173. if (ret)
  174. return log_msg_ret("pmc_gpe", ret);
  175. ret = uclass_first_device_err(UCLASS_LPC, &lpc);
  176. if (ret)
  177. return log_msg_ret("lpc", ret);
  178. early_ec_init();
  179. return 0;
  180. }
  181. /*
  182. * Enables several BARs and devices which are needed for memory init
  183. * - MCH_BASE_ADDR is needed in order to talk to the memory controller
  184. * - HPET is enabled because FSP wants to store a pointer to global data in the
  185. * HPET comparator register
  186. */
  187. static int arch_cpu_init_spl(void)
  188. {
  189. struct udevice *pmc, *p2sb;
  190. int ret;
  191. ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
  192. if (ret)
  193. return log_msg_ret("Could not probe PMC", ret);
  194. ret = uclass_first_device_err(UCLASS_P2SB, &p2sb);
  195. if (ret)
  196. return log_msg_ret("Cannot set up p2sb", ret);
  197. lpc_io_setup_comm_a_b();
  198. /* TODO(sjg@chromium.org): Enable upper RTC bank here */
  199. ret = pmc_init(pmc);
  200. if (ret < 0)
  201. return log_msg_ret("Could not init PMC", ret);
  202. if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
  203. ret = pmc_prev_sleep_state(pmc);
  204. if (ret < 0)
  205. return log_msg_ret("Could not get PMC sleep state",
  206. ret);
  207. gd->arch.prev_sleep_state = ret;
  208. }
  209. return 0;
  210. }
  211. int arch_cpu_init(void)
  212. {
  213. int ret = 0;
  214. if (spl_phase() == PHASE_TPL)
  215. ret = arch_cpu_init_tpl();
  216. else if (spl_phase() == PHASE_SPL)
  217. ret = arch_cpu_init_spl();
  218. if (ret)
  219. printf("%s: Error %d\n", __func__, ret);
  220. return ret;
  221. }