immap_85xx.h 105 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * MPC85xx Internal Memory Map
  4. *
  5. * Copyright 2007-2012 Freescale Semiconductor, Inc.
  6. *
  7. * Copyright(c) 2002,2003 Motorola Inc.
  8. * Xianghua Xiao (x.xiao@motorola.com)
  9. */
  10. #ifndef __IMMAP_85xx__
  11. #define __IMMAP_85xx__
  12. #include <asm/types.h>
  13. #include <asm/fsl_dma.h>
  14. #include <asm/fsl_i2c.h>
  15. #include <fsl_ifc.h>
  16. #include <fsl_sec.h>
  17. #include <fsl_sfp.h>
  18. #include <asm/fsl_lbc.h>
  19. #include <fsl_fman.h>
  20. #include <fsl_immap.h>
  21. typedef struct ccsr_local {
  22. u32 ccsrbarh; /* CCSR Base Addr High */
  23. u32 ccsrbarl; /* CCSR Base Addr Low */
  24. u32 ccsrar; /* CCSR Attr */
  25. #define CCSRAR_C 0x80000000 /* Commit */
  26. u8 res1[4];
  27. u32 altcbarh; /* Alternate Configuration Base Addr High */
  28. u32 altcbarl; /* Alternate Configuration Base Addr Low */
  29. u32 altcar; /* Alternate Configuration Attr */
  30. u8 res2[4];
  31. u32 bstrh; /* Boot space translation high */
  32. u32 bstrl; /* Boot space translation Low */
  33. u32 bstrar; /* Boot space translation attributes */
  34. u8 res3[0xbd4];
  35. struct {
  36. u32 lawbarh; /* LAWn base addr high */
  37. u32 lawbarl; /* LAWn base addr low */
  38. u32 lawar; /* LAWn attributes */
  39. u8 res4[4];
  40. } law[32];
  41. u8 res35[0x204];
  42. } ccsr_local_t;
  43. /* Local-Access Registers & ECM Registers */
  44. typedef struct ccsr_local_ecm {
  45. u32 ccsrbar; /* CCSR Base Addr */
  46. u8 res1[4];
  47. u32 altcbar; /* Alternate Configuration Base Addr */
  48. u8 res2[4];
  49. u32 altcar; /* Alternate Configuration Attr */
  50. u8 res3[12];
  51. u32 bptr; /* Boot Page Translation */
  52. u8 res4[3044];
  53. u32 lawbar0; /* Local Access Window 0 Base Addr */
  54. u8 res5[4];
  55. u32 lawar0; /* Local Access Window 0 Attrs */
  56. u8 res6[20];
  57. u32 lawbar1; /* Local Access Window 1 Base Addr */
  58. u8 res7[4];
  59. u32 lawar1; /* Local Access Window 1 Attrs */
  60. u8 res8[20];
  61. u32 lawbar2; /* Local Access Window 2 Base Addr */
  62. u8 res9[4];
  63. u32 lawar2; /* Local Access Window 2 Attrs */
  64. u8 res10[20];
  65. u32 lawbar3; /* Local Access Window 3 Base Addr */
  66. u8 res11[4];
  67. u32 lawar3; /* Local Access Window 3 Attrs */
  68. u8 res12[20];
  69. u32 lawbar4; /* Local Access Window 4 Base Addr */
  70. u8 res13[4];
  71. u32 lawar4; /* Local Access Window 4 Attrs */
  72. u8 res14[20];
  73. u32 lawbar5; /* Local Access Window 5 Base Addr */
  74. u8 res15[4];
  75. u32 lawar5; /* Local Access Window 5 Attrs */
  76. u8 res16[20];
  77. u32 lawbar6; /* Local Access Window 6 Base Addr */
  78. u8 res17[4];
  79. u32 lawar6; /* Local Access Window 6 Attrs */
  80. u8 res18[20];
  81. u32 lawbar7; /* Local Access Window 7 Base Addr */
  82. u8 res19[4];
  83. u32 lawar7; /* Local Access Window 7 Attrs */
  84. u8 res19_8a[20];
  85. u32 lawbar8; /* Local Access Window 8 Base Addr */
  86. u8 res19_8b[4];
  87. u32 lawar8; /* Local Access Window 8 Attrs */
  88. u8 res19_9a[20];
  89. u32 lawbar9; /* Local Access Window 9 Base Addr */
  90. u8 res19_9b[4];
  91. u32 lawar9; /* Local Access Window 9 Attrs */
  92. u8 res19_10a[20];
  93. u32 lawbar10; /* Local Access Window 10 Base Addr */
  94. u8 res19_10b[4];
  95. u32 lawar10; /* Local Access Window 10 Attrs */
  96. u8 res19_11a[20];
  97. u32 lawbar11; /* Local Access Window 11 Base Addr */
  98. u8 res19_11b[4];
  99. u32 lawar11; /* Local Access Window 11 Attrs */
  100. u8 res20[652];
  101. u32 eebacr; /* ECM CCB Addr Configuration */
  102. u8 res21[12];
  103. u32 eebpcr; /* ECM CCB Port Configuration */
  104. u8 res22[3564];
  105. u32 eedr; /* ECM Error Detect */
  106. u8 res23[4];
  107. u32 eeer; /* ECM Error Enable */
  108. u32 eeatr; /* ECM Error Attrs Capture */
  109. u32 eeadr; /* ECM Error Addr Capture */
  110. u8 res24[492];
  111. } ccsr_local_ecm_t;
  112. #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
  113. #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
  114. /* I2C Registers */
  115. typedef struct ccsr_i2c {
  116. struct fsl_i2c_base i2c[1];
  117. u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
  118. } ccsr_i2c_t;
  119. #if defined(CONFIG_ARCH_MPC8540) || \
  120. defined(CONFIG_ARCH_MPC8541) || \
  121. defined(CONFIG_ARCH_MPC8548) || \
  122. defined(CONFIG_ARCH_MPC8555)
  123. /* DUART Registers */
  124. typedef struct ccsr_duart {
  125. u8 res1[1280];
  126. /* URBR1, UTHR1, UDLB1 with the same addr */
  127. u8 urbr1_uthr1_udlb1;
  128. /* UIER1, UDMB1 with the same addr01 */
  129. u8 uier1_udmb1;
  130. /* UIIR1, UFCR1, UAFR1 with the same addr */
  131. u8 uiir1_ufcr1_uafr1;
  132. u8 ulcr1; /* UART1 Line Control */
  133. u8 umcr1; /* UART1 Modem Control */
  134. u8 ulsr1; /* UART1 Line Status */
  135. u8 umsr1; /* UART1 Modem Status */
  136. u8 uscr1; /* UART1 Scratch */
  137. u8 res2[8];
  138. u8 udsr1; /* UART1 DMA Status */
  139. u8 res3[239];
  140. /* URBR2, UTHR2, UDLB2 with the same addr */
  141. u8 urbr2_uthr2_udlb2;
  142. /* UIER2, UDMB2 with the same addr */
  143. u8 uier2_udmb2;
  144. /* UIIR2, UFCR2, UAFR2 with the same addr */
  145. u8 uiir2_ufcr2_uafr2;
  146. u8 ulcr2; /* UART2 Line Control */
  147. u8 umcr2; /* UART2 Modem Control */
  148. u8 ulsr2; /* UART2 Line Status */
  149. u8 umsr2; /* UART2 Modem Status */
  150. u8 uscr2; /* UART2 Scratch */
  151. u8 res4[8];
  152. u8 udsr2; /* UART2 DMA Status */
  153. u8 res5[2543];
  154. } ccsr_duart_t;
  155. #else /* MPC8560 uses UART on its CPM */
  156. typedef struct ccsr_duart {
  157. u8 res[4096];
  158. } ccsr_duart_t;
  159. #endif
  160. /* eSPI Registers */
  161. typedef struct ccsr_espi {
  162. u32 mode; /* eSPI mode */
  163. u32 event; /* eSPI event */
  164. u32 mask; /* eSPI mask */
  165. u32 com; /* eSPI command */
  166. u32 tx; /* eSPI transmit FIFO access */
  167. u32 rx; /* eSPI receive FIFO access */
  168. u8 res1[8]; /* reserved */
  169. u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
  170. u8 res2[4048]; /* fill up to 0x1000 */
  171. } ccsr_espi_t;
  172. /* PCI Registers */
  173. typedef struct ccsr_pcix {
  174. u32 cfg_addr; /* PCIX Configuration Addr */
  175. u32 cfg_data; /* PCIX Configuration Data */
  176. u32 int_ack; /* PCIX IRQ Acknowledge */
  177. u8 res000c[52];
  178. u32 liodn_base; /* PCIX LIODN base register */
  179. u8 res0044[2996];
  180. u32 ipver1; /* PCIX IP block revision register 1 */
  181. u32 ipver2; /* PCIX IP block revision register 2 */
  182. u32 potar0; /* PCIX Outbound Transaction Addr 0 */
  183. u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
  184. u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
  185. u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
  186. u32 powar0; /* PCIX Outbound Window Attrs 0 */
  187. u8 res2[12];
  188. u32 potar1; /* PCIX Outbound Transaction Addr 1 */
  189. u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
  190. u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
  191. u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
  192. u32 powar1; /* PCIX Outbound Window Attrs 1 */
  193. u8 res3[12];
  194. u32 potar2; /* PCIX Outbound Transaction Addr 2 */
  195. u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
  196. u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
  197. u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
  198. u32 powar2; /* PCIX Outbound Window Attrs 2 */
  199. u8 res4[12];
  200. u32 potar3; /* PCIX Outbound Transaction Addr 3 */
  201. u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
  202. u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
  203. u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
  204. u32 powar3; /* PCIX Outbound Window Attrs 3 */
  205. u8 res5[12];
  206. u32 potar4; /* PCIX Outbound Transaction Addr 4 */
  207. u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
  208. u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
  209. u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
  210. u32 powar4; /* PCIX Outbound Window Attrs 4 */
  211. u8 res6[268];
  212. u32 pitar3; /* PCIX Inbound Translation Addr 3 */
  213. u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
  214. u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
  215. u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
  216. u32 piwar3; /* PCIX Inbound Window Attrs 3 */
  217. u8 res7[12];
  218. u32 pitar2; /* PCIX Inbound Translation Addr 2 */
  219. u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
  220. u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
  221. u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
  222. u32 piwar2; /* PCIX Inbound Window Attrs 2 */
  223. u8 res8[12];
  224. u32 pitar1; /* PCIX Inbound Translation Addr 1 */
  225. u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
  226. u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
  227. u8 res9[4];
  228. u32 piwar1; /* PCIX Inbound Window Attrs 1 */
  229. u8 res10[12];
  230. u32 pedr; /* PCIX Error Detect */
  231. u32 pecdr; /* PCIX Error Capture Disable */
  232. u32 peer; /* PCIX Error Enable */
  233. u32 peattrcr; /* PCIX Error Attrs Capture */
  234. u32 peaddrcr; /* PCIX Error Addr Capture */
  235. u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
  236. u32 pedlcr; /* PCIX Error Data Low Capture */
  237. u32 pedhcr; /* PCIX Error Error Data High Capture */
  238. u32 gas_timr; /* PCIX Gasket Timer */
  239. u8 res11[476];
  240. } ccsr_pcix_t;
  241. #define PCIX_COMMAND 0x62
  242. #define POWAR_EN 0x80000000
  243. #define POWAR_IO_READ 0x00080000
  244. #define POWAR_MEM_READ 0x00040000
  245. #define POWAR_IO_WRITE 0x00008000
  246. #define POWAR_MEM_WRITE 0x00004000
  247. #define POWAR_MEM_512M 0x0000001c
  248. #define POWAR_IO_1M 0x00000013
  249. #define PIWAR_EN 0x80000000
  250. #define PIWAR_PF 0x20000000
  251. #define PIWAR_LOCAL 0x00f00000
  252. #define PIWAR_READ_SNOOP 0x00050000
  253. #define PIWAR_WRITE_SNOOP 0x00005000
  254. #define PIWAR_MEM_2G 0x0000001e
  255. #ifndef CONFIG_MPC85XX_GPIO
  256. typedef struct ccsr_gpio {
  257. u32 gpdir;
  258. u32 gpodr;
  259. u32 gpdat;
  260. u32 gpier;
  261. u32 gpimr;
  262. u32 gpicr;
  263. u32 gpibe;
  264. } ccsr_gpio_t;
  265. #endif
  266. /* L2 Cache Registers */
  267. typedef struct ccsr_l2cache {
  268. u32 l2ctl; /* L2 configuration 0 */
  269. u8 res1[12];
  270. u32 l2cewar0; /* L2 cache external write addr 0 */
  271. u8 res2[4];
  272. u32 l2cewcr0; /* L2 cache external write control 0 */
  273. u8 res3[4];
  274. u32 l2cewar1; /* L2 cache external write addr 1 */
  275. u8 res4[4];
  276. u32 l2cewcr1; /* L2 cache external write control 1 */
  277. u8 res5[4];
  278. u32 l2cewar2; /* L2 cache external write addr 2 */
  279. u8 res6[4];
  280. u32 l2cewcr2; /* L2 cache external write control 2 */
  281. u8 res7[4];
  282. u32 l2cewar3; /* L2 cache external write addr 3 */
  283. u8 res8[4];
  284. u32 l2cewcr3; /* L2 cache external write control 3 */
  285. u8 res9[180];
  286. u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
  287. u8 res10[4];
  288. u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
  289. u8 res11[3316];
  290. u32 l2errinjhi; /* L2 error injection mask high */
  291. u32 l2errinjlo; /* L2 error injection mask low */
  292. u32 l2errinjctl; /* L2 error injection tag/ECC control */
  293. u8 res12[20];
  294. u32 l2captdatahi; /* L2 error data high capture */
  295. u32 l2captdatalo; /* L2 error data low capture */
  296. u32 l2captecc; /* L2 error ECC capture */
  297. u8 res13[20];
  298. u32 l2errdet; /* L2 error detect */
  299. u32 l2errdis; /* L2 error disable */
  300. u32 l2errinten; /* L2 error interrupt enable */
  301. u32 l2errattr; /* L2 error attributes capture */
  302. u32 l2erraddr; /* L2 error addr capture */
  303. u8 res14[4];
  304. u32 l2errctl; /* L2 error control */
  305. u8 res15[420];
  306. } ccsr_l2cache_t;
  307. #define MPC85xx_L2CTL_L2E 0x80000000
  308. #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
  309. #define MPC85xx_L2ERRDIS_MBECC 0x00000008
  310. #define MPC85xx_L2ERRDIS_SBECC 0x00000004
  311. /* DMA Registers */
  312. typedef struct ccsr_dma {
  313. u8 res1[256];
  314. struct fsl_dma dma[4];
  315. u32 dgsr; /* DMA General Status */
  316. u8 res2[11516];
  317. } ccsr_dma_t;
  318. /* tsec */
  319. typedef struct ccsr_tsec {
  320. u8 res1[16];
  321. u32 ievent; /* IRQ Event */
  322. u32 imask; /* IRQ Mask */
  323. u32 edis; /* Error Disabled */
  324. u8 res2[4];
  325. u32 ecntrl; /* Ethernet Control */
  326. u32 minflr; /* Minimum Frame Len */
  327. u32 ptv; /* Pause Time Value */
  328. u32 dmactrl; /* DMA Control */
  329. u32 tbipa; /* TBI PHY Addr */
  330. u8 res3[88];
  331. u32 fifo_tx_thr; /* FIFO transmit threshold */
  332. u8 res4[8];
  333. u32 fifo_tx_starve; /* FIFO transmit starve */
  334. u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
  335. u8 res5[96];
  336. u32 tctrl; /* TX Control */
  337. u32 tstat; /* TX Status */
  338. u8 res6[4];
  339. u32 tbdlen; /* TX Buffer Desc Data Len */
  340. u8 res7[16];
  341. u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
  342. u32 ctbptr; /* Current TX Buffer Desc Ptr */
  343. u8 res8[88];
  344. u32 tbptrh; /* TX Buffer Desc Ptr High */
  345. u32 tbptr; /* TX Buffer Desc Ptr Low */
  346. u8 res9[120];
  347. u32 tbaseh; /* TX Desc Base Addr High */
  348. u32 tbase; /* TX Desc Base Addr */
  349. u8 res10[168];
  350. u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
  351. u32 ostbdp; /* OOS TX Data Buffer Ptr */
  352. u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
  353. u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
  354. u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
  355. u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
  356. u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
  357. u8 res11[52];
  358. u32 rctrl; /* RX Control */
  359. u32 rstat; /* RX Status */
  360. u8 res12[4];
  361. u32 rbdlen; /* RxBD Data Len */
  362. u8 res13[16];
  363. u32 crbptrh; /* Current RX Buffer Desc Ptr High */
  364. u32 crbptr; /* Current RX Buffer Desc Ptr */
  365. u8 res14[24];
  366. u32 mrblr; /* Maximum RX Buffer Len */
  367. u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
  368. u8 res15[56];
  369. u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
  370. u32 rbptr; /* RX Buffer Desc Ptr */
  371. u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
  372. u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
  373. u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
  374. u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
  375. u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
  376. u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
  377. u8 res16[96];
  378. u32 rbaseh; /* RX Desc Base Addr High 0 */
  379. u32 rbase; /* RX Desc Base Addr */
  380. u32 rbaseh1; /* RX Desc Base Addr High 1 */
  381. u32 rbasel1; /* RX Desc Base Addr Low 1 */
  382. u32 rbaseh2; /* RX Desc Base Addr High 2 */
  383. u32 rbasel2; /* RX Desc Base Addr Low 2 */
  384. u32 rbaseh3; /* RX Desc Base Addr High 3 */
  385. u32 rbasel3; /* RX Desc Base Addr Low 3 */
  386. u8 res17[224];
  387. u32 maccfg1; /* MAC Configuration 1 */
  388. u32 maccfg2; /* MAC Configuration 2 */
  389. u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
  390. u32 hafdup; /* Half Duplex */
  391. u32 maxfrm; /* Maximum Frame Len */
  392. u8 res18[12];
  393. u32 miimcfg; /* MII Management Configuration */
  394. u32 miimcom; /* MII Management Cmd */
  395. u32 miimadd; /* MII Management Addr */
  396. u32 miimcon; /* MII Management Control */
  397. u32 miimstat; /* MII Management Status */
  398. u32 miimind; /* MII Management Indicator */
  399. u8 res19[4];
  400. u32 ifstat; /* Interface Status */
  401. u32 macstnaddr1; /* Station Addr Part 1 */
  402. u32 macstnaddr2; /* Station Addr Part 2 */
  403. u8 res20[312];
  404. u32 tr64; /* TX & RX 64-byte Frame Counter */
  405. u32 tr127; /* TX & RX 65-127 byte Frame Counter */
  406. u32 tr255; /* TX & RX 128-255 byte Frame Counter */
  407. u32 tr511; /* TX & RX 256-511 byte Frame Counter */
  408. u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
  409. u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
  410. u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
  411. u32 rbyt; /* RX Byte Counter */
  412. u32 rpkt; /* RX Packet Counter */
  413. u32 rfcs; /* RX FCS Error Counter */
  414. u32 rmca; /* RX Multicast Packet Counter */
  415. u32 rbca; /* RX Broadcast Packet Counter */
  416. u32 rxcf; /* RX Control Frame Packet Counter */
  417. u32 rxpf; /* RX Pause Frame Packet Counter */
  418. u32 rxuo; /* RX Unknown OP Code Counter */
  419. u32 raln; /* RX Alignment Error Counter */
  420. u32 rflr; /* RX Frame Len Error Counter */
  421. u32 rcde; /* RX Code Error Counter */
  422. u32 rcse; /* RX Carrier Sense Error Counter */
  423. u32 rund; /* RX Undersize Packet Counter */
  424. u32 rovr; /* RX Oversize Packet Counter */
  425. u32 rfrg; /* RX Fragments Counter */
  426. u32 rjbr; /* RX Jabber Counter */
  427. u32 rdrp; /* RX Drop Counter */
  428. u32 tbyt; /* TX Byte Counter Counter */
  429. u32 tpkt; /* TX Packet Counter */
  430. u32 tmca; /* TX Multicast Packet Counter */
  431. u32 tbca; /* TX Broadcast Packet Counter */
  432. u32 txpf; /* TX Pause Control Frame Counter */
  433. u32 tdfr; /* TX Deferral Packet Counter */
  434. u32 tedf; /* TX Excessive Deferral Packet Counter */
  435. u32 tscl; /* TX Single Collision Packet Counter */
  436. u32 tmcl; /* TX Multiple Collision Packet Counter */
  437. u32 tlcl; /* TX Late Collision Packet Counter */
  438. u32 txcl; /* TX Excessive Collision Packet Counter */
  439. u32 tncl; /* TX Total Collision Counter */
  440. u8 res21[4];
  441. u32 tdrp; /* TX Drop Frame Counter */
  442. u32 tjbr; /* TX Jabber Frame Counter */
  443. u32 tfcs; /* TX FCS Error Counter */
  444. u32 txcf; /* TX Control Frame Counter */
  445. u32 tovr; /* TX Oversize Frame Counter */
  446. u32 tund; /* TX Undersize Frame Counter */
  447. u32 tfrg; /* TX Fragments Frame Counter */
  448. u32 car1; /* Carry One */
  449. u32 car2; /* Carry Two */
  450. u32 cam1; /* Carry Mask One */
  451. u32 cam2; /* Carry Mask Two */
  452. u8 res22[192];
  453. u32 iaddr0; /* Indivdual addr 0 */
  454. u32 iaddr1; /* Indivdual addr 1 */
  455. u32 iaddr2; /* Indivdual addr 2 */
  456. u32 iaddr3; /* Indivdual addr 3 */
  457. u32 iaddr4; /* Indivdual addr 4 */
  458. u32 iaddr5; /* Indivdual addr 5 */
  459. u32 iaddr6; /* Indivdual addr 6 */
  460. u32 iaddr7; /* Indivdual addr 7 */
  461. u8 res23[96];
  462. u32 gaddr0; /* Global addr 0 */
  463. u32 gaddr1; /* Global addr 1 */
  464. u32 gaddr2; /* Global addr 2 */
  465. u32 gaddr3; /* Global addr 3 */
  466. u32 gaddr4; /* Global addr 4 */
  467. u32 gaddr5; /* Global addr 5 */
  468. u32 gaddr6; /* Global addr 6 */
  469. u32 gaddr7; /* Global addr 7 */
  470. u8 res24[96];
  471. u32 pmd0; /* Pattern Match Data */
  472. u8 res25[4];
  473. u32 pmask0; /* Pattern Mask */
  474. u8 res26[4];
  475. u32 pcntrl0; /* Pattern Match Control */
  476. u8 res27[4];
  477. u32 pattrb0; /* Pattern Match Attrs */
  478. u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
  479. u32 pmd1; /* Pattern Match Data */
  480. u8 res28[4];
  481. u32 pmask1; /* Pattern Mask */
  482. u8 res29[4];
  483. u32 pcntrl1; /* Pattern Match Control */
  484. u8 res30[4];
  485. u32 pattrb1; /* Pattern Match Attrs */
  486. u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
  487. u32 pmd2; /* Pattern Match Data */
  488. u8 res31[4];
  489. u32 pmask2; /* Pattern Mask */
  490. u8 res32[4];
  491. u32 pcntrl2; /* Pattern Match Control */
  492. u8 res33[4];
  493. u32 pattrb2; /* Pattern Match Attrs */
  494. u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
  495. u32 pmd3; /* Pattern Match Data */
  496. u8 res34[4];
  497. u32 pmask3; /* Pattern Mask */
  498. u8 res35[4];
  499. u32 pcntrl3; /* Pattern Match Control */
  500. u8 res36[4];
  501. u32 pattrb3; /* Pattern Match Attrs */
  502. u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
  503. u32 pmd4; /* Pattern Match Data */
  504. u8 res37[4];
  505. u32 pmask4; /* Pattern Mask */
  506. u8 res38[4];
  507. u32 pcntrl4; /* Pattern Match Control */
  508. u8 res39[4];
  509. u32 pattrb4; /* Pattern Match Attrs */
  510. u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
  511. u32 pmd5; /* Pattern Match Data */
  512. u8 res40[4];
  513. u32 pmask5; /* Pattern Mask */
  514. u8 res41[4];
  515. u32 pcntrl5; /* Pattern Match Control */
  516. u8 res42[4];
  517. u32 pattrb5; /* Pattern Match Attrs */
  518. u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
  519. u32 pmd6; /* Pattern Match Data */
  520. u8 res43[4];
  521. u32 pmask6; /* Pattern Mask */
  522. u8 res44[4];
  523. u32 pcntrl6; /* Pattern Match Control */
  524. u8 res45[4];
  525. u32 pattrb6; /* Pattern Match Attrs */
  526. u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
  527. u32 pmd7; /* Pattern Match Data */
  528. u8 res46[4];
  529. u32 pmask7; /* Pattern Mask */
  530. u8 res47[4];
  531. u32 pcntrl7; /* Pattern Match Control */
  532. u8 res48[4];
  533. u32 pattrb7; /* Pattern Match Attrs */
  534. u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
  535. u32 pmd8; /* Pattern Match Data */
  536. u8 res49[4];
  537. u32 pmask8; /* Pattern Mask */
  538. u8 res50[4];
  539. u32 pcntrl8; /* Pattern Match Control */
  540. u8 res51[4];
  541. u32 pattrb8; /* Pattern Match Attrs */
  542. u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
  543. u32 pmd9; /* Pattern Match Data */
  544. u8 res52[4];
  545. u32 pmask9; /* Pattern Mask */
  546. u8 res53[4];
  547. u32 pcntrl9; /* Pattern Match Control */
  548. u8 res54[4];
  549. u32 pattrb9; /* Pattern Match Attrs */
  550. u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
  551. u32 pmd10; /* Pattern Match Data */
  552. u8 res55[4];
  553. u32 pmask10; /* Pattern Mask */
  554. u8 res56[4];
  555. u32 pcntrl10; /* Pattern Match Control */
  556. u8 res57[4];
  557. u32 pattrb10; /* Pattern Match Attrs */
  558. u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
  559. u32 pmd11; /* Pattern Match Data */
  560. u8 res58[4];
  561. u32 pmask11; /* Pattern Mask */
  562. u8 res59[4];
  563. u32 pcntrl11; /* Pattern Match Control */
  564. u8 res60[4];
  565. u32 pattrb11; /* Pattern Match Attrs */
  566. u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
  567. u32 pmd12; /* Pattern Match Data */
  568. u8 res61[4];
  569. u32 pmask12; /* Pattern Mask */
  570. u8 res62[4];
  571. u32 pcntrl12; /* Pattern Match Control */
  572. u8 res63[4];
  573. u32 pattrb12; /* Pattern Match Attrs */
  574. u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
  575. u32 pmd13; /* Pattern Match Data */
  576. u8 res64[4];
  577. u32 pmask13; /* Pattern Mask */
  578. u8 res65[4];
  579. u32 pcntrl13; /* Pattern Match Control */
  580. u8 res66[4];
  581. u32 pattrb13; /* Pattern Match Attrs */
  582. u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
  583. u32 pmd14; /* Pattern Match Data */
  584. u8 res67[4];
  585. u32 pmask14; /* Pattern Mask */
  586. u8 res68[4];
  587. u32 pcntrl14; /* Pattern Match Control */
  588. u8 res69[4];
  589. u32 pattrb14; /* Pattern Match Attrs */
  590. u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
  591. u32 pmd15; /* Pattern Match Data */
  592. u8 res70[4];
  593. u32 pmask15; /* Pattern Mask */
  594. u8 res71[4];
  595. u32 pcntrl15; /* Pattern Match Control */
  596. u8 res72[4];
  597. u32 pattrb15; /* Pattern Match Attrs */
  598. u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
  599. u8 res73[248];
  600. u32 attr; /* Attrs */
  601. u32 attreli; /* Attrs Extract Len & Idx */
  602. u8 res74[1024];
  603. } ccsr_tsec_t;
  604. /* PIC Registers */
  605. typedef struct ccsr_pic {
  606. u8 res1[64];
  607. u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
  608. u8 res2[12];
  609. u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
  610. u8 res3[12];
  611. u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
  612. u8 res4[12];
  613. u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
  614. u8 res5[12];
  615. u32 ctpr; /* Current Task Priority */
  616. u8 res6[12];
  617. u32 whoami; /* Who Am I */
  618. u8 res7[12];
  619. u32 iack; /* IRQ Acknowledge */
  620. u8 res8[12];
  621. u32 eoi; /* End Of IRQ */
  622. u8 res9[3916];
  623. u32 frr; /* Feature Reporting */
  624. u8 res10[28];
  625. u32 gcr; /* Global Configuration */
  626. #define MPC85xx_PICGCR_RST 0x80000000
  627. #define MPC85xx_PICGCR_M 0x20000000
  628. u8 res11[92];
  629. u32 vir; /* Vendor Identification */
  630. u8 res12[12];
  631. u32 pir; /* Processor Initialization */
  632. u8 res13[12];
  633. u32 ipivpr0; /* IPI Vector/Priority 0 */
  634. u8 res14[12];
  635. u32 ipivpr1; /* IPI Vector/Priority 1 */
  636. u8 res15[12];
  637. u32 ipivpr2; /* IPI Vector/Priority 2 */
  638. u8 res16[12];
  639. u32 ipivpr3; /* IPI Vector/Priority 3 */
  640. u8 res17[12];
  641. u32 svr; /* Spurious Vector */
  642. u8 res18[12];
  643. u32 tfrr; /* Timer Frequency Reporting */
  644. u8 res19[12];
  645. u32 gtccr0; /* Global Timer Current Count 0 */
  646. u8 res20[12];
  647. u32 gtbcr0; /* Global Timer Base Count 0 */
  648. u8 res21[12];
  649. u32 gtvpr0; /* Global Timer Vector/Priority 0 */
  650. u8 res22[12];
  651. u32 gtdr0; /* Global Timer Destination 0 */
  652. u8 res23[12];
  653. u32 gtccr1; /* Global Timer Current Count 1 */
  654. u8 res24[12];
  655. u32 gtbcr1; /* Global Timer Base Count 1 */
  656. u8 res25[12];
  657. u32 gtvpr1; /* Global Timer Vector/Priority 1 */
  658. u8 res26[12];
  659. u32 gtdr1; /* Global Timer Destination 1 */
  660. u8 res27[12];
  661. u32 gtccr2; /* Global Timer Current Count 2 */
  662. u8 res28[12];
  663. u32 gtbcr2; /* Global Timer Base Count 2 */
  664. u8 res29[12];
  665. u32 gtvpr2; /* Global Timer Vector/Priority 2 */
  666. u8 res30[12];
  667. u32 gtdr2; /* Global Timer Destination 2 */
  668. u8 res31[12];
  669. u32 gtccr3; /* Global Timer Current Count 3 */
  670. u8 res32[12];
  671. u32 gtbcr3; /* Global Timer Base Count 3 */
  672. u8 res33[12];
  673. u32 gtvpr3; /* Global Timer Vector/Priority 3 */
  674. u8 res34[12];
  675. u32 gtdr3; /* Global Timer Destination 3 */
  676. u8 res35[268];
  677. u32 tcr; /* Timer Control */
  678. u8 res36[12];
  679. u32 irqsr0; /* IRQ_OUT Summary 0 */
  680. u8 res37[12];
  681. u32 irqsr1; /* IRQ_OUT Summary 1 */
  682. u8 res38[12];
  683. u32 cisr0; /* Critical IRQ Summary 0 */
  684. u8 res39[12];
  685. u32 cisr1; /* Critical IRQ Summary 1 */
  686. u8 res40[188];
  687. u32 msgr0; /* Message 0 */
  688. u8 res41[12];
  689. u32 msgr1; /* Message 1 */
  690. u8 res42[12];
  691. u32 msgr2; /* Message 2 */
  692. u8 res43[12];
  693. u32 msgr3; /* Message 3 */
  694. u8 res44[204];
  695. u32 mer; /* Message Enable */
  696. u8 res45[12];
  697. u32 msr; /* Message Status */
  698. u8 res46[60140];
  699. u32 eivpr0; /* External IRQ Vector/Priority 0 */
  700. u8 res47[12];
  701. u32 eidr0; /* External IRQ Destination 0 */
  702. u8 res48[12];
  703. u32 eivpr1; /* External IRQ Vector/Priority 1 */
  704. u8 res49[12];
  705. u32 eidr1; /* External IRQ Destination 1 */
  706. u8 res50[12];
  707. u32 eivpr2; /* External IRQ Vector/Priority 2 */
  708. u8 res51[12];
  709. u32 eidr2; /* External IRQ Destination 2 */
  710. u8 res52[12];
  711. u32 eivpr3; /* External IRQ Vector/Priority 3 */
  712. u8 res53[12];
  713. u32 eidr3; /* External IRQ Destination 3 */
  714. u8 res54[12];
  715. u32 eivpr4; /* External IRQ Vector/Priority 4 */
  716. u8 res55[12];
  717. u32 eidr4; /* External IRQ Destination 4 */
  718. u8 res56[12];
  719. u32 eivpr5; /* External IRQ Vector/Priority 5 */
  720. u8 res57[12];
  721. u32 eidr5; /* External IRQ Destination 5 */
  722. u8 res58[12];
  723. u32 eivpr6; /* External IRQ Vector/Priority 6 */
  724. u8 res59[12];
  725. u32 eidr6; /* External IRQ Destination 6 */
  726. u8 res60[12];
  727. u32 eivpr7; /* External IRQ Vector/Priority 7 */
  728. u8 res61[12];
  729. u32 eidr7; /* External IRQ Destination 7 */
  730. u8 res62[12];
  731. u32 eivpr8; /* External IRQ Vector/Priority 8 */
  732. u8 res63[12];
  733. u32 eidr8; /* External IRQ Destination 8 */
  734. u8 res64[12];
  735. u32 eivpr9; /* External IRQ Vector/Priority 9 */
  736. u8 res65[12];
  737. u32 eidr9; /* External IRQ Destination 9 */
  738. u8 res66[12];
  739. u32 eivpr10; /* External IRQ Vector/Priority 10 */
  740. u8 res67[12];
  741. u32 eidr10; /* External IRQ Destination 10 */
  742. u8 res68[12];
  743. u32 eivpr11; /* External IRQ Vector/Priority 11 */
  744. u8 res69[12];
  745. u32 eidr11; /* External IRQ Destination 11 */
  746. u8 res70[140];
  747. u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
  748. u8 res71[12];
  749. u32 iidr0; /* Internal IRQ Destination 0 */
  750. u8 res72[12];
  751. u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
  752. u8 res73[12];
  753. u32 iidr1; /* Internal IRQ Destination 1 */
  754. u8 res74[12];
  755. u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
  756. u8 res75[12];
  757. u32 iidr2; /* Internal IRQ Destination 2 */
  758. u8 res76[12];
  759. u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
  760. u8 res77[12];
  761. u32 iidr3; /* Internal IRQ Destination 3 */
  762. u8 res78[12];
  763. u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
  764. u8 res79[12];
  765. u32 iidr4; /* Internal IRQ Destination 4 */
  766. u8 res80[12];
  767. u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
  768. u8 res81[12];
  769. u32 iidr5; /* Internal IRQ Destination 5 */
  770. u8 res82[12];
  771. u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
  772. u8 res83[12];
  773. u32 iidr6; /* Internal IRQ Destination 6 */
  774. u8 res84[12];
  775. u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
  776. u8 res85[12];
  777. u32 iidr7; /* Internal IRQ Destination 7 */
  778. u8 res86[12];
  779. u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
  780. u8 res87[12];
  781. u32 iidr8; /* Internal IRQ Destination 8 */
  782. u8 res88[12];
  783. u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
  784. u8 res89[12];
  785. u32 iidr9; /* Internal IRQ Destination 9 */
  786. u8 res90[12];
  787. u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
  788. u8 res91[12];
  789. u32 iidr10; /* Internal IRQ Destination 10 */
  790. u8 res92[12];
  791. u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
  792. u8 res93[12];
  793. u32 iidr11; /* Internal IRQ Destination 11 */
  794. u8 res94[12];
  795. u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
  796. u8 res95[12];
  797. u32 iidr12; /* Internal IRQ Destination 12 */
  798. u8 res96[12];
  799. u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
  800. u8 res97[12];
  801. u32 iidr13; /* Internal IRQ Destination 13 */
  802. u8 res98[12];
  803. u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
  804. u8 res99[12];
  805. u32 iidr14; /* Internal IRQ Destination 14 */
  806. u8 res100[12];
  807. u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
  808. u8 res101[12];
  809. u32 iidr15; /* Internal IRQ Destination 15 */
  810. u8 res102[12];
  811. u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
  812. u8 res103[12];
  813. u32 iidr16; /* Internal IRQ Destination 16 */
  814. u8 res104[12];
  815. u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
  816. u8 res105[12];
  817. u32 iidr17; /* Internal IRQ Destination 17 */
  818. u8 res106[12];
  819. u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
  820. u8 res107[12];
  821. u32 iidr18; /* Internal IRQ Destination 18 */
  822. u8 res108[12];
  823. u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
  824. u8 res109[12];
  825. u32 iidr19; /* Internal IRQ Destination 19 */
  826. u8 res110[12];
  827. u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
  828. u8 res111[12];
  829. u32 iidr20; /* Internal IRQ Destination 20 */
  830. u8 res112[12];
  831. u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
  832. u8 res113[12];
  833. u32 iidr21; /* Internal IRQ Destination 21 */
  834. u8 res114[12];
  835. u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
  836. u8 res115[12];
  837. u32 iidr22; /* Internal IRQ Destination 22 */
  838. u8 res116[12];
  839. u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
  840. u8 res117[12];
  841. u32 iidr23; /* Internal IRQ Destination 23 */
  842. u8 res118[12];
  843. u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
  844. u8 res119[12];
  845. u32 iidr24; /* Internal IRQ Destination 24 */
  846. u8 res120[12];
  847. u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
  848. u8 res121[12];
  849. u32 iidr25; /* Internal IRQ Destination 25 */
  850. u8 res122[12];
  851. u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
  852. u8 res123[12];
  853. u32 iidr26; /* Internal IRQ Destination 26 */
  854. u8 res124[12];
  855. u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
  856. u8 res125[12];
  857. u32 iidr27; /* Internal IRQ Destination 27 */
  858. u8 res126[12];
  859. u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
  860. u8 res127[12];
  861. u32 iidr28; /* Internal IRQ Destination 28 */
  862. u8 res128[12];
  863. u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
  864. u8 res129[12];
  865. u32 iidr29; /* Internal IRQ Destination 29 */
  866. u8 res130[12];
  867. u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
  868. u8 res131[12];
  869. u32 iidr30; /* Internal IRQ Destination 30 */
  870. u8 res132[12];
  871. u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
  872. u8 res133[12];
  873. u32 iidr31; /* Internal IRQ Destination 31 */
  874. u8 res134[4108];
  875. u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
  876. u8 res135[12];
  877. u32 midr0; /* Messaging IRQ Destination 0 */
  878. u8 res136[12];
  879. u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
  880. u8 res137[12];
  881. u32 midr1; /* Messaging IRQ Destination 1 */
  882. u8 res138[12];
  883. u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
  884. u8 res139[12];
  885. u32 midr2; /* Messaging IRQ Destination 2 */
  886. u8 res140[12];
  887. u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
  888. u8 res141[12];
  889. u32 midr3; /* Messaging IRQ Destination 3 */
  890. u8 res142[59852];
  891. u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
  892. u8 res143[12];
  893. u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
  894. u8 res144[12];
  895. u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
  896. u8 res145[12];
  897. u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
  898. u8 res146[12];
  899. u32 ctpr0; /* Current Task Priority for Processor 0 */
  900. u8 res147[12];
  901. u32 whoami0; /* Who Am I for Processor 0 */
  902. u8 res148[12];
  903. u32 iack0; /* IRQ Acknowledge for Processor 0 */
  904. u8 res149[12];
  905. u32 eoi0; /* End Of IRQ for Processor 0 */
  906. u8 res150[130892];
  907. } ccsr_pic_t;
  908. /* CPM Block */
  909. #ifndef CONFIG_CPM2
  910. typedef struct ccsr_cpm {
  911. u8 res[262144];
  912. } ccsr_cpm_t;
  913. #else
  914. /*
  915. * DPARM
  916. * General SIU
  917. */
  918. typedef struct ccsr_cpm_siu {
  919. u8 res1[80];
  920. u32 smaer;
  921. u32 smser;
  922. u32 smevr;
  923. u8 res2[4];
  924. u32 lmaer;
  925. u32 lmser;
  926. u32 lmevr;
  927. u8 res3[2964];
  928. } ccsr_cpm_siu_t;
  929. /* IRQ Controller */
  930. typedef struct ccsr_cpm_intctl {
  931. u16 sicr;
  932. u8 res1[2];
  933. u32 sivec;
  934. u32 sipnrh;
  935. u32 sipnrl;
  936. u32 siprr;
  937. u32 scprrh;
  938. u32 scprrl;
  939. u32 simrh;
  940. u32 simrl;
  941. u32 siexr;
  942. u8 res2[88];
  943. u32 sccr;
  944. u8 res3[124];
  945. } ccsr_cpm_intctl_t;
  946. /* input/output port */
  947. typedef struct ccsr_cpm_iop {
  948. u32 pdira;
  949. u32 ppara;
  950. u32 psora;
  951. u32 podra;
  952. u32 pdata;
  953. u8 res1[12];
  954. u32 pdirb;
  955. u32 pparb;
  956. u32 psorb;
  957. u32 podrb;
  958. u32 pdatb;
  959. u8 res2[12];
  960. u32 pdirc;
  961. u32 pparc;
  962. u32 psorc;
  963. u32 podrc;
  964. u32 pdatc;
  965. u8 res3[12];
  966. u32 pdird;
  967. u32 ppard;
  968. u32 psord;
  969. u32 podrd;
  970. u32 pdatd;
  971. u8 res4[12];
  972. } ccsr_cpm_iop_t;
  973. /* CPM timers */
  974. typedef struct ccsr_cpm_timer {
  975. u8 tgcr1;
  976. u8 res1[3];
  977. u8 tgcr2;
  978. u8 res2[11];
  979. u16 tmr1;
  980. u16 tmr2;
  981. u16 trr1;
  982. u16 trr2;
  983. u16 tcr1;
  984. u16 tcr2;
  985. u16 tcn1;
  986. u16 tcn2;
  987. u16 tmr3;
  988. u16 tmr4;
  989. u16 trr3;
  990. u16 trr4;
  991. u16 tcr3;
  992. u16 tcr4;
  993. u16 tcn3;
  994. u16 tcn4;
  995. u16 ter1;
  996. u16 ter2;
  997. u16 ter3;
  998. u16 ter4;
  999. u8 res3[608];
  1000. } ccsr_cpm_timer_t;
  1001. /* SDMA */
  1002. typedef struct ccsr_cpm_sdma {
  1003. u8 sdsr;
  1004. u8 res1[3];
  1005. u8 sdmr;
  1006. u8 res2[739];
  1007. } ccsr_cpm_sdma_t;
  1008. /* FCC1 */
  1009. typedef struct ccsr_cpm_fcc1 {
  1010. u32 gfmr;
  1011. u32 fpsmr;
  1012. u16 ftodr;
  1013. u8 res1[2];
  1014. u16 fdsr;
  1015. u8 res2[2];
  1016. u16 fcce;
  1017. u8 res3[2];
  1018. u16 fccm;
  1019. u8 res4[2];
  1020. u8 fccs;
  1021. u8 res5[3];
  1022. u8 ftirr_phy[4];
  1023. } ccsr_cpm_fcc1_t;
  1024. /* FCC2 */
  1025. typedef struct ccsr_cpm_fcc2 {
  1026. u32 gfmr;
  1027. u32 fpsmr;
  1028. u16 ftodr;
  1029. u8 res1[2];
  1030. u16 fdsr;
  1031. u8 res2[2];
  1032. u16 fcce;
  1033. u8 res3[2];
  1034. u16 fccm;
  1035. u8 res4[2];
  1036. u8 fccs;
  1037. u8 res5[3];
  1038. u8 ftirr_phy[4];
  1039. } ccsr_cpm_fcc2_t;
  1040. /* FCC3 */
  1041. typedef struct ccsr_cpm_fcc3 {
  1042. u32 gfmr;
  1043. u32 fpsmr;
  1044. u16 ftodr;
  1045. u8 res1[2];
  1046. u16 fdsr;
  1047. u8 res2[2];
  1048. u16 fcce;
  1049. u8 res3[2];
  1050. u16 fccm;
  1051. u8 res4[2];
  1052. u8 fccs;
  1053. u8 res5[3];
  1054. u8 res[36];
  1055. } ccsr_cpm_fcc3_t;
  1056. /* FCC1 extended */
  1057. typedef struct ccsr_cpm_fcc1_ext {
  1058. u32 firper;
  1059. u32 firer;
  1060. u32 firsr_h;
  1061. u32 firsr_l;
  1062. u8 gfemr;
  1063. u8 res[15];
  1064. } ccsr_cpm_fcc1_ext_t;
  1065. /* FCC2 extended */
  1066. typedef struct ccsr_cpm_fcc2_ext {
  1067. u32 firper;
  1068. u32 firer;
  1069. u32 firsr_h;
  1070. u32 firsr_l;
  1071. u8 gfemr;
  1072. u8 res[31];
  1073. } ccsr_cpm_fcc2_ext_t;
  1074. /* FCC3 extended */
  1075. typedef struct ccsr_cpm_fcc3_ext {
  1076. u8 gfemr;
  1077. u8 res[47];
  1078. } ccsr_cpm_fcc3_ext_t;
  1079. /* TC layers */
  1080. typedef struct ccsr_cpm_tmp1 {
  1081. u8 res[496];
  1082. } ccsr_cpm_tmp1_t;
  1083. /* BRGs:5,6,7,8 */
  1084. typedef struct ccsr_cpm_brg2 {
  1085. u32 brgc5;
  1086. u32 brgc6;
  1087. u32 brgc7;
  1088. u32 brgc8;
  1089. u8 res[608];
  1090. } ccsr_cpm_brg2_t;
  1091. /* I2C */
  1092. typedef struct ccsr_cpm_i2c {
  1093. u8 i2mod;
  1094. u8 res1[3];
  1095. u8 i2add;
  1096. u8 res2[3];
  1097. u8 i2brg;
  1098. u8 res3[3];
  1099. u8 i2com;
  1100. u8 res4[3];
  1101. u8 i2cer;
  1102. u8 res5[3];
  1103. u8 i2cmr;
  1104. u8 res6[331];
  1105. } ccsr_cpm_i2c_t;
  1106. /* CPM core */
  1107. typedef struct ccsr_cpm_cp {
  1108. u32 cpcr;
  1109. u32 rccr;
  1110. u8 res1[14];
  1111. u16 rter;
  1112. u8 res2[2];
  1113. u16 rtmr;
  1114. u16 rtscr;
  1115. u8 res3[2];
  1116. u32 rtsr;
  1117. u8 res4[12];
  1118. } ccsr_cpm_cp_t;
  1119. /* BRGs:1,2,3,4 */
  1120. typedef struct ccsr_cpm_brg1 {
  1121. u32 brgc1;
  1122. u32 brgc2;
  1123. u32 brgc3;
  1124. u32 brgc4;
  1125. } ccsr_cpm_brg1_t;
  1126. /* SCC1-SCC4 */
  1127. typedef struct ccsr_cpm_scc {
  1128. u32 gsmrl;
  1129. u32 gsmrh;
  1130. u16 psmr;
  1131. u8 res1[2];
  1132. u16 todr;
  1133. u16 dsr;
  1134. u16 scce;
  1135. u8 res2[2];
  1136. u16 sccm;
  1137. u8 res3;
  1138. u8 sccs;
  1139. u8 res4[8];
  1140. } ccsr_cpm_scc_t;
  1141. typedef struct ccsr_cpm_tmp2 {
  1142. u8 res[32];
  1143. } ccsr_cpm_tmp2_t;
  1144. /* SPI */
  1145. typedef struct ccsr_cpm_spi {
  1146. u16 spmode;
  1147. u8 res1[4];
  1148. u8 spie;
  1149. u8 res2[3];
  1150. u8 spim;
  1151. u8 res3[2];
  1152. u8 spcom;
  1153. u8 res4[82];
  1154. } ccsr_cpm_spi_t;
  1155. /* CPM MUX */
  1156. typedef struct ccsr_cpm_mux {
  1157. u8 cmxsi1cr;
  1158. u8 res1;
  1159. u8 cmxsi2cr;
  1160. u8 res2;
  1161. u32 cmxfcr;
  1162. u32 cmxscr;
  1163. u8 res3[2];
  1164. u16 cmxuar;
  1165. u8 res4[16];
  1166. } ccsr_cpm_mux_t;
  1167. /* SI,MCC,etc */
  1168. typedef struct ccsr_cpm_tmp3 {
  1169. u8 res[58592];
  1170. } ccsr_cpm_tmp3_t;
  1171. typedef struct ccsr_cpm_iram {
  1172. u32 iram[8192];
  1173. u8 res[98304];
  1174. } ccsr_cpm_iram_t;
  1175. typedef struct ccsr_cpm {
  1176. /* Some references are into the unique & known dpram spaces,
  1177. * others are from the generic base.
  1178. */
  1179. #define im_dprambase im_dpram1
  1180. u8 im_dpram1[16*1024];
  1181. u8 res1[16*1024];
  1182. u8 im_dpram2[16*1024];
  1183. u8 res2[16*1024];
  1184. ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
  1185. ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
  1186. ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
  1187. ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
  1188. ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
  1189. ccsr_cpm_fcc1_t im_cpm_fcc1;
  1190. ccsr_cpm_fcc2_t im_cpm_fcc2;
  1191. ccsr_cpm_fcc3_t im_cpm_fcc3;
  1192. ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
  1193. ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
  1194. ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
  1195. ccsr_cpm_tmp1_t im_cpm_tmp1;
  1196. ccsr_cpm_brg2_t im_cpm_brg2;
  1197. ccsr_cpm_i2c_t im_cpm_i2c;
  1198. ccsr_cpm_cp_t im_cpm_cp;
  1199. ccsr_cpm_brg1_t im_cpm_brg1;
  1200. ccsr_cpm_scc_t im_cpm_scc[4];
  1201. ccsr_cpm_tmp2_t im_cpm_tmp2;
  1202. ccsr_cpm_spi_t im_cpm_spi;
  1203. ccsr_cpm_mux_t im_cpm_mux;
  1204. ccsr_cpm_tmp3_t im_cpm_tmp3;
  1205. ccsr_cpm_iram_t im_cpm_iram;
  1206. } ccsr_cpm_t;
  1207. #endif
  1208. #ifdef CONFIG_SYS_SRIO
  1209. /* Architectural regsiters */
  1210. struct rio_arch {
  1211. u32 didcar; /* Device Identity CAR */
  1212. u32 dicar; /* Device Information CAR */
  1213. u32 aidcar; /* Assembly Identity CAR */
  1214. u32 aicar; /* Assembly Information CAR */
  1215. u32 pefcar; /* Processing Element Features CAR */
  1216. u8 res0[4];
  1217. u32 socar; /* Source Operations CAR */
  1218. u32 docar; /* Destination Operations CAR */
  1219. u8 res1[32];
  1220. u32 mcsr; /* Mailbox CSR */
  1221. u32 pwdcsr; /* Port-Write and Doorbell CSR */
  1222. u8 res2[4];
  1223. u32 pellccsr; /* Processing Element Logic Layer CCSR */
  1224. u8 res3[12];
  1225. u32 lcsbacsr; /* Local Configuration Space BACSR */
  1226. u32 bdidcsr; /* Base Device ID CSR */
  1227. u8 res4[4];
  1228. u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
  1229. u32 ctcsr; /* Component Tag CSR */
  1230. };
  1231. /* Extended Features Space: 1x/4x LP-Serial Port registers */
  1232. struct rio_lp_serial_port {
  1233. u32 plmreqcsr; /* Port Link Maintenance Request CSR */
  1234. u32 plmrespcsr; /* Port Link Maintenance Response CS */
  1235. u32 plascsr; /* Port Local Ackid Status CSR */
  1236. u8 res0[12];
  1237. u32 pescsr; /* Port Error and Status CSR */
  1238. u32 pccsr; /* Port Control CSR */
  1239. };
  1240. /* Extended Features Space: 1x/4x LP-Serial registers */
  1241. struct rio_lp_serial {
  1242. u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
  1243. u8 res0[28];
  1244. u32 pltoccsr; /* Port Link Time-out CCSR */
  1245. u32 prtoccsr; /* Port Response Time-out CCSR */
  1246. u8 res1[20];
  1247. u32 pgccsr; /* Port General CSR */
  1248. struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
  1249. };
  1250. /* Logical error reporting registers */
  1251. struct rio_logical_err {
  1252. u32 erbh; /* Error Reporting Block Header Register */
  1253. u8 res0[4];
  1254. u32 ltledcsr; /* Logical/Transport layer error DCSR */
  1255. u32 ltleecsr; /* Logical/Transport layer error ECSR */
  1256. u8 res1[4];
  1257. u32 ltlaccsr; /* Logical/Transport layer ACCSR */
  1258. u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
  1259. u32 ltlcccsr; /* Logical/Transport layer control CCSR */
  1260. };
  1261. /* Physical error reporting port registers */
  1262. struct rio_phys_err_port {
  1263. u32 edcsr; /* Port error detect CSR */
  1264. u32 erecsr; /* Port error rate enable CSR */
  1265. u32 ecacsr; /* Port error capture attributes CSR */
  1266. u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
  1267. u32 peccsr[3]; /* Port error capture CSR */
  1268. u8 res0[12];
  1269. u32 ercsr; /* Port error rate CSR */
  1270. u32 ertcsr; /* Port error rate threshold CSR */
  1271. u8 res1[16];
  1272. };
  1273. /* Physical error reporting registers */
  1274. struct rio_phys_err {
  1275. struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
  1276. };
  1277. /* Implementation Space: General Port-Common */
  1278. struct rio_impl_common {
  1279. u8 res0[4];
  1280. u32 llcr; /* Logical Layer Configuration Register */
  1281. u8 res1[8];
  1282. u32 epwisr; /* Error / Port-Write Interrupt SR */
  1283. u8 res2[12];
  1284. u32 lretcr; /* Logical Retry Error Threshold CR */
  1285. u8 res3[92];
  1286. u32 pretcr; /* Physical Retry Erorr Threshold CR */
  1287. u8 res4[124];
  1288. };
  1289. /* Implementation Space: Port Specific */
  1290. struct rio_impl_port_spec {
  1291. u32 adidcsr; /* Port Alt. Device ID CSR */
  1292. u8 res0[28];
  1293. u32 ptaacr; /* Port Pass-Through/Accept-All CR */
  1294. u32 lopttlcr;
  1295. u8 res1[8];
  1296. u32 iecsr; /* Port Implementation Error CSR */
  1297. u8 res2[12];
  1298. u32 pcr; /* Port Phsyical Configuration Register */
  1299. u8 res3[20];
  1300. u32 slcsr; /* Port Serial Link CSR */
  1301. u8 res4[4];
  1302. u32 sleicr; /* Port Serial Link Error Injection */
  1303. u32 a0txcr; /* Port Arbitration 0 Tx CR */
  1304. u32 a1txcr; /* Port Arbitration 1 Tx CR */
  1305. u32 a2txcr; /* Port Arbitration 2 Tx CR */
  1306. u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
  1307. u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
  1308. };
  1309. /* Implementation Space: register */
  1310. struct rio_implement {
  1311. struct rio_impl_common com;
  1312. struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
  1313. };
  1314. /* Revision Control Register */
  1315. struct rio_rev_ctrl {
  1316. u32 ipbrr[2]; /* IP Block Revision Register */
  1317. };
  1318. struct rio_atmu_row {
  1319. u32 rowtar; /* RapidIO Outbound Window TAR */
  1320. u32 rowtear; /* RapidIO Outbound Window TEAR */
  1321. u32 rowbar;
  1322. u8 res0[4];
  1323. u32 rowar; /* RapidIO Outbound Attributes Register */
  1324. u32 rowsr[3]; /* Port RapidIO outbound window segment register */
  1325. };
  1326. struct rio_atmu_riw {
  1327. u32 riwtar; /* RapidIO Inbound Window Translation AR */
  1328. u8 res0[4];
  1329. u32 riwbar; /* RapidIO Inbound Window Base AR */
  1330. u8 res1[4];
  1331. u32 riwar; /* RapidIO Inbound Attributes Register */
  1332. u8 res2[12];
  1333. };
  1334. /* ATMU window registers */
  1335. struct rio_atmu_win {
  1336. struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
  1337. u8 res0[64];
  1338. struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
  1339. };
  1340. struct rio_atmu {
  1341. struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
  1342. };
  1343. #ifdef CONFIG_SYS_FSL_RMU
  1344. struct rio_msg {
  1345. u32 omr; /* Outbound Mode Register */
  1346. u32 osr; /* Outbound Status Register */
  1347. u32 eodqdpar; /* Extended Outbound DQ DPAR */
  1348. u32 odqdpar; /* Outbound Descriptor Queue DPAR */
  1349. u32 eosar; /* Extended Outbound Unit Source AR */
  1350. u32 osar; /* Outbound Unit Source AR */
  1351. u32 odpr; /* Outbound Destination Port Register */
  1352. u32 odatr; /* Outbound Destination Attributes Register */
  1353. u32 odcr; /* Outbound Doubleword Count Register */
  1354. u32 eodqepar; /* Extended Outbound DQ EPAR */
  1355. u32 odqepar; /* Outbound Descriptor Queue EPAR */
  1356. u32 oretr; /* Outbound Retry Error Threshold Register */
  1357. u32 omgr; /* Outbound Multicast Group Register */
  1358. u32 omlr; /* Outbound Multicast List Register */
  1359. u8 res0[40];
  1360. u32 imr; /* Outbound Mode Register */
  1361. u32 isr; /* Inbound Status Register */
  1362. u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
  1363. u32 idqdpar; /* Inbound Descriptor Queue DPAR */
  1364. u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
  1365. u32 ifqepar; /* Inbound Frame Queue EPAR */
  1366. u32 imirir; /* Inbound Maximum Interrutp RIR */
  1367. u8 res1[4];
  1368. u32 eihqepar; /* Extended inbound message header queue EPAR */
  1369. u32 ihqepar; /* Inbound message header queue EPAR */
  1370. u8 res2[120];
  1371. };
  1372. struct rio_dbell {
  1373. u32 odmr; /* Outbound Doorbell Mode Register */
  1374. u32 odsr; /* Outbound Doorbell Status Register */
  1375. u8 res0[16];
  1376. u32 oddpr; /* Outbound Doorbell Destination Port */
  1377. u32 oddatr; /* Outbound Doorbell Destination AR */
  1378. u8 res1[12];
  1379. u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
  1380. u8 res2[48];
  1381. u32 idmr; /* Inbound Doorbell Mode Register */
  1382. u32 idsr; /* Inbound Doorbell Status Register */
  1383. u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
  1384. u32 iqdpar; /* Inbound Doorbell Queue DPAR */
  1385. u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
  1386. u32 idqepar; /* Inbound Doorbell Queue EPAR */
  1387. u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
  1388. };
  1389. struct rio_pw {
  1390. u32 pwmr; /* Port-Write Mode Register */
  1391. u32 pwsr; /* Port-Write Status Register */
  1392. u32 epwqbar; /* Extended Port-Write Queue BAR */
  1393. u32 pwqbar; /* Port-Write Queue Base Address Register */
  1394. };
  1395. #endif
  1396. #ifdef CONFIG_SYS_FSL_SRIO_LIODN
  1397. struct rio_liodn {
  1398. u32 plbr;
  1399. u8 res0[28];
  1400. u32 plaor;
  1401. u8 res1[12];
  1402. u32 pludr;
  1403. u32 plldr;
  1404. u8 res2[456];
  1405. };
  1406. #endif
  1407. /* RapidIO Registers */
  1408. struct ccsr_rio {
  1409. struct rio_arch arch;
  1410. u8 res0[144];
  1411. struct rio_lp_serial lp_serial;
  1412. u8 res1[1152];
  1413. struct rio_logical_err logical_err;
  1414. u8 res2[32];
  1415. struct rio_phys_err phys_err;
  1416. u8 res3[63808];
  1417. struct rio_implement impl;
  1418. u8 res4[2552];
  1419. struct rio_rev_ctrl rev;
  1420. struct rio_atmu atmu;
  1421. #ifdef CONFIG_SYS_FSL_RMU
  1422. u8 res5[8192];
  1423. struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
  1424. u8 res6[512];
  1425. struct rio_dbell dbell;
  1426. u8 res7[100];
  1427. struct rio_pw pw;
  1428. #endif
  1429. #ifdef CONFIG_SYS_FSL_SRIO_LIODN
  1430. u8 res5[8192];
  1431. struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
  1432. #endif
  1433. };
  1434. #endif
  1435. /* Quick Engine Block Pin Muxing Registers */
  1436. typedef struct par_io {
  1437. u32 cpodr;
  1438. u32 cpdat;
  1439. u32 cpdir1;
  1440. u32 cpdir2;
  1441. u32 cppar1;
  1442. u32 cppar2;
  1443. u8 res[8];
  1444. } par_io_t;
  1445. #ifdef CONFIG_SYS_FSL_CPC
  1446. /*
  1447. * Define a single offset that is the start of all the CPC register
  1448. * blocks - if there is more than one CPC, we expect these to be
  1449. * contiguous 4k regions
  1450. */
  1451. typedef struct cpc_corenet {
  1452. u32 cpccsr0; /* Config/status reg */
  1453. u32 res1;
  1454. u32 cpccfg0; /* Configuration register */
  1455. u32 res2;
  1456. u32 cpcewcr0; /* External Write reg 0 */
  1457. u32 cpcewabr0; /* External write base reg 0 */
  1458. u32 res3[2];
  1459. u32 cpcewcr1; /* External Write reg 1 */
  1460. u32 cpcewabr1; /* External write base reg 1 */
  1461. u32 res4[54];
  1462. u32 cpcsrcr1; /* SRAM control reg 1 */
  1463. u32 cpcsrcr0; /* SRAM control reg 0 */
  1464. u32 res5[62];
  1465. struct {
  1466. u32 id; /* partition ID */
  1467. u32 res;
  1468. u32 alloc; /* partition allocation */
  1469. u32 way; /* partition way */
  1470. } partition_regs[16];
  1471. u32 res6[704];
  1472. u32 cpcerrinjhi; /* Error injection high */
  1473. u32 cpcerrinjlo; /* Error injection lo */
  1474. u32 cpcerrinjctl; /* Error injection control */
  1475. u32 res7[5];
  1476. u32 cpccaptdatahi; /* capture data high */
  1477. u32 cpccaptdatalo; /* capture data low */
  1478. u32 cpcaptecc; /* capture ECC */
  1479. u32 res8[5];
  1480. u32 cpcerrdet; /* error detect */
  1481. u32 cpcerrdis; /* error disable */
  1482. u32 cpcerrinten; /* errir interrupt enable */
  1483. u32 cpcerrattr; /* error attribute */
  1484. u32 cpcerreaddr; /* error extended address */
  1485. u32 cpcerraddr; /* error address */
  1486. u32 cpcerrctl; /* error control */
  1487. u32 res9[41]; /* pad out to 4k */
  1488. u32 cpchdbcr0; /* hardware debug control register 0 */
  1489. u32 res10[63]; /* pad out to 4k */
  1490. } cpc_corenet_t;
  1491. #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
  1492. #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
  1493. #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
  1494. #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
  1495. #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
  1496. #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
  1497. #define CPC_CFG0_SZ_MASK 0x00003fff
  1498. #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
  1499. #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
  1500. #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
  1501. #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
  1502. #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
  1503. & CPC_SRCR1_SRBARU_MASK)
  1504. #define CPC_SRCR0_SRBARL_MASK 0xffff8000
  1505. #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
  1506. #define CPC_SRCR0_INTLVEN 0x00000100
  1507. #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
  1508. #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
  1509. #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
  1510. #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
  1511. #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
  1512. #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
  1513. #define CPC_SRCR0_SRAMEN 0x00000001
  1514. #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
  1515. #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
  1516. #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
  1517. #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
  1518. #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000
  1519. #endif /* CONFIG_SYS_FSL_CPC */
  1520. /* Global Utilities Block */
  1521. #ifdef CONFIG_FSL_CORENET
  1522. typedef struct ccsr_gur {
  1523. u32 porsr1; /* POR status 1 */
  1524. u32 porsr2; /* POR status 2 */
  1525. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  1526. #define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
  1527. #define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
  1528. #define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
  1529. #define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
  1530. #endif
  1531. u8 res_008[0x20-0x8];
  1532. u32 gpporcr1; /* General-purpose POR configuration */
  1533. u32 gpporcr2; /* General-purpose POR configuration 2 */
  1534. u32 dcfg_fusesr; /* Fuse status register */
  1535. #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
  1536. #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
  1537. #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
  1538. #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
  1539. u8 res_02c[0x70-0x2c];
  1540. u32 devdisr; /* Device disable control */
  1541. u32 devdisr2; /* Device disable control 2 */
  1542. u32 devdisr3; /* Device disable control 3 */
  1543. u32 devdisr4; /* Device disable control 4 */
  1544. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  1545. u32 devdisr5; /* Device disable control 5 */
  1546. #define FSL_CORENET_DEVDISR_PBL 0x80000000
  1547. #define FSL_CORENET_DEVDISR_PMAN 0x40000000
  1548. #define FSL_CORENET_DEVDISR_ESDHC 0x20000000
  1549. #define FSL_CORENET_DEVDISR_DMA1 0x00800000
  1550. #define FSL_CORENET_DEVDISR_DMA2 0x00400000
  1551. #define FSL_CORENET_DEVDISR_USB1 0x00080000
  1552. #define FSL_CORENET_DEVDISR_USB2 0x00040000
  1553. #define FSL_CORENET_DEVDISR_SATA1 0x00008000
  1554. #define FSL_CORENET_DEVDISR_SATA2 0x00004000
  1555. #define FSL_CORENET_DEVDISR_PME 0x00000800
  1556. #define FSL_CORENET_DEVDISR_SEC 0x00000200
  1557. #define FSL_CORENET_DEVDISR_RMU 0x00000080
  1558. #define FSL_CORENET_DEVDISR_DCE 0x00000040
  1559. #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
  1560. #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
  1561. #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
  1562. #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
  1563. #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
  1564. #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
  1565. #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
  1566. #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
  1567. #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  1568. #define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
  1569. #define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
  1570. #else
  1571. #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
  1572. #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
  1573. #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
  1574. #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
  1575. #endif
  1576. #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
  1577. #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
  1578. #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
  1579. #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
  1580. #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
  1581. #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
  1582. #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
  1583. #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
  1584. #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
  1585. #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
  1586. #define FSL_CORENET_DEVDISR2_FM1 0x00000080
  1587. #define FSL_CORENET_DEVDISR2_FM2 0x00000040
  1588. #define FSL_CORENET_DEVDISR2_CPRI 0x00000008
  1589. #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
  1590. #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
  1591. #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
  1592. #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
  1593. #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
  1594. #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
  1595. #define FSL_CORENET_DEVDISR3_QMAN 0x00080000
  1596. #define FSL_CORENET_DEVDISR3_BMAN 0x00040000
  1597. #define FSL_CORENET_DEVDISR3_LA1 0x00008000
  1598. #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
  1599. #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
  1600. #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
  1601. #define FSL_CORENET_DEVDISR4_I2C1 0x80000000
  1602. #define FSL_CORENET_DEVDISR4_I2C2 0x40000000
  1603. #define FSL_CORENET_DEVDISR4_DUART1 0x20000000
  1604. #define FSL_CORENET_DEVDISR4_DUART2 0x10000000
  1605. #define FSL_CORENET_DEVDISR4_ESPI 0x08000000
  1606. #define FSL_CORENET_DEVDISR5_DDR1 0x80000000
  1607. #define FSL_CORENET_DEVDISR5_DDR2 0x40000000
  1608. #define FSL_CORENET_DEVDISR5_DDR3 0x20000000
  1609. #define FSL_CORENET_DEVDISR5_CPC1 0x08000000
  1610. #define FSL_CORENET_DEVDISR5_CPC2 0x04000000
  1611. #define FSL_CORENET_DEVDISR5_CPC3 0x02000000
  1612. #define FSL_CORENET_DEVDISR5_IFC 0x00800000
  1613. #define FSL_CORENET_DEVDISR5_GPIO 0x00400000
  1614. #define FSL_CORENET_DEVDISR5_DBG 0x00200000
  1615. #define FSL_CORENET_DEVDISR5_NAL 0x00100000
  1616. #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
  1617. #define FSL_CORENET_NUM_DEVDISR 5
  1618. #else
  1619. #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
  1620. #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
  1621. #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
  1622. #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
  1623. #define FSL_CORENET_DEVDISR_RMU 0x08000000
  1624. #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
  1625. #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
  1626. #define FSL_CORENET_DEVDISR_DMA1 0x00400000
  1627. #define FSL_CORENET_DEVDISR_DMA2 0x00200000
  1628. #define FSL_CORENET_DEVDISR_DDR1 0x00100000
  1629. #define FSL_CORENET_DEVDISR_DDR2 0x00080000
  1630. #define FSL_CORENET_DEVDISR_DBG 0x00010000
  1631. #define FSL_CORENET_DEVDISR_NAL 0x00008000
  1632. #define FSL_CORENET_DEVDISR_SATA1 0x00004000
  1633. #define FSL_CORENET_DEVDISR_SATA2 0x00002000
  1634. #define FSL_CORENET_DEVDISR_ELBC 0x00001000
  1635. #define FSL_CORENET_DEVDISR_USB1 0x00000800
  1636. #define FSL_CORENET_DEVDISR_USB2 0x00000400
  1637. #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
  1638. #define FSL_CORENET_DEVDISR_GPIO 0x00000080
  1639. #define FSL_CORENET_DEVDISR_ESPI 0x00000040
  1640. #define FSL_CORENET_DEVDISR_I2C1 0x00000020
  1641. #define FSL_CORENET_DEVDISR_I2C2 0x00000010
  1642. #define FSL_CORENET_DEVDISR_DUART1 0x00000002
  1643. #define FSL_CORENET_DEVDISR_DUART2 0x00000001
  1644. #define FSL_CORENET_DEVDISR2_PME 0x80000000
  1645. #define FSL_CORENET_DEVDISR2_SEC 0x40000000
  1646. #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
  1647. #define FSL_CORENET_DEVDISR2_FM1 0x02000000
  1648. #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
  1649. #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
  1650. #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
  1651. #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
  1652. #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
  1653. #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
  1654. #define FSL_CORENET_DEVDISR2_FM2 0x00020000
  1655. #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
  1656. #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
  1657. #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
  1658. #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
  1659. #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
  1660. #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
  1661. #define FSL_CORENET_NUM_DEVDISR 2
  1662. u32 powmgtcsr; /* Power management status & control */
  1663. #endif
  1664. u8 res8[12];
  1665. u32 coredisru; /* uppper portion for support of 64 cores */
  1666. u32 coredisrl; /* lower portion for support of 64 cores */
  1667. u8 res9[8];
  1668. u32 pvr; /* Processor version */
  1669. u32 svr; /* System version */
  1670. u8 res10[8];
  1671. u32 rstcr; /* Reset control */
  1672. u32 rstrqpblsr; /* Reset request preboot loader status */
  1673. u8 res11[8];
  1674. u32 rstrqmr1; /* Reset request mask */
  1675. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  1676. #define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
  1677. #endif
  1678. u8 res12[4];
  1679. u32 rstrqsr1; /* Reset request status */
  1680. u8 res13[4];
  1681. u8 res14[4];
  1682. u32 rstrqwdtmrl; /* Reset request WDT mask */
  1683. u8 res15[4];
  1684. u32 rstrqwdtsrl; /* Reset request WDT status */
  1685. u8 res16[4];
  1686. u32 brrl; /* Boot release */
  1687. u8 res17[24];
  1688. u32 rcwsr[16]; /* Reset control word status */
  1689. #define RCW_SB_EN_REG_INDEX 7
  1690. #define RCW_SB_EN_MASK 0x00200000
  1691. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  1692. #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
  1693. /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
  1694. #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
  1695. #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
  1696. #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
  1697. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
  1698. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
  1699. #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
  1700. #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
  1701. #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
  1702. #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
  1703. #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
  1704. #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
  1705. #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
  1706. #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
  1707. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
  1708. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
  1709. #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
  1710. #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
  1711. #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
  1712. #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
  1713. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
  1714. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
  1715. #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
  1716. #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
  1717. #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
  1718. #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
  1719. #define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
  1720. #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
  1721. #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
  1722. #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
  1723. #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000
  1724. #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
  1725. #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
  1726. #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
  1727. #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
  1728. #define PXCKEN_MASK 0x80000000
  1729. #define PXCK_MASK 0x00FF0000
  1730. #define PXCK_BITS_START 16
  1731. #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
  1732. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
  1733. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
  1734. #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
  1735. #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
  1736. #define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
  1737. #define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
  1738. #define FSL_CORENET_RCWSR13_EC2 0x0c000000
  1739. #define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
  1740. #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
  1741. #define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
  1742. #define PXCKEN_MASK 0x80000000
  1743. #define PXCK_MASK 0x00FF0000
  1744. #define PXCK_BITS_START 16
  1745. #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
  1746. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
  1747. #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
  1748. #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
  1749. #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
  1750. #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
  1751. #endif
  1752. #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
  1753. #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
  1754. #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
  1755. #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
  1756. #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
  1757. #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
  1758. #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
  1759. #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
  1760. #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
  1761. #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
  1762. #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
  1763. #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  1764. #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
  1765. #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
  1766. #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
  1767. #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
  1768. #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
  1769. #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
  1770. #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
  1771. #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
  1772. #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
  1773. #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
  1774. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  1775. #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
  1776. #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
  1777. #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
  1778. #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
  1779. #ifdef CONFIG_ARCH_P4080
  1780. #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
  1781. #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
  1782. #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
  1783. #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
  1784. #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
  1785. #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
  1786. #endif
  1787. #if defined(CONFIG_ARCH_P2041) || \
  1788. defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
  1789. #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
  1790. #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
  1791. #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
  1792. #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
  1793. #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
  1794. #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
  1795. #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
  1796. #endif
  1797. #if defined(CONFIG_ARCH_P5040)
  1798. #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
  1799. #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
  1800. #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
  1801. #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
  1802. #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
  1803. #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
  1804. #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
  1805. #endif
  1806. #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
  1807. #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
  1808. #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
  1809. #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
  1810. #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
  1811. #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
  1812. #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
  1813. #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
  1814. #endif
  1815. #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
  1816. #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
  1817. #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
  1818. #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
  1819. #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
  1820. #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
  1821. #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
  1822. #define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
  1823. #endif
  1824. u8 res18[192];
  1825. u32 scratchrw[4]; /* Scratch Read/Write */
  1826. u8 res19[240];
  1827. u32 scratchw1r[4]; /* Scratch Read (Write once) */
  1828. u8 res20[240];
  1829. u32 scrtsr[8]; /* Core reset status */
  1830. u8 res21[224];
  1831. u32 pex1liodnr; /* PCI Express 1 LIODN */
  1832. u32 pex2liodnr; /* PCI Express 2 LIODN */
  1833. u32 pex3liodnr; /* PCI Express 3 LIODN */
  1834. u32 pex4liodnr; /* PCI Express 4 LIODN */
  1835. u32 rio1liodnr; /* RIO 1 LIODN */
  1836. u32 rio2liodnr; /* RIO 2 LIODN */
  1837. u32 rio3liodnr; /* RIO 3 LIODN */
  1838. u32 rio4liodnr; /* RIO 4 LIODN */
  1839. u32 usb1liodnr; /* USB 1 LIODN */
  1840. u32 usb2liodnr; /* USB 2 LIODN */
  1841. u32 usb3liodnr; /* USB 3 LIODN */
  1842. u32 usb4liodnr; /* USB 4 LIODN */
  1843. u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
  1844. u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
  1845. u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
  1846. u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
  1847. u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
  1848. u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
  1849. u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
  1850. u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
  1851. u32 sata1liodnr; /* SATA 1 LIODN */
  1852. u32 sata2liodnr; /* SATA 2 LIODN */
  1853. u32 sata3liodnr; /* SATA 3 LIODN */
  1854. u32 sata4liodnr; /* SATA 4 LIODN */
  1855. u8 res22[20];
  1856. u32 tdmliodnr; /* TDM LIODN */
  1857. u32 qeliodnr; /* QE LIODN */
  1858. u8 res_57c[4];
  1859. u32 dma1liodnr; /* DMA 1 LIODN */
  1860. u32 dma2liodnr; /* DMA 2 LIODN */
  1861. u32 dma3liodnr; /* DMA 3 LIODN */
  1862. u32 dma4liodnr; /* DMA 4 LIODN */
  1863. u8 res23[48];
  1864. u8 res24[64];
  1865. u32 pblsr; /* Preboot loader status */
  1866. u32 pamubypenr; /* PAMU bypass enable */
  1867. u32 dmacr1; /* DMA control */
  1868. u8 res25[4];
  1869. u32 gensr1; /* General status */
  1870. u8 res26[12];
  1871. u32 gencr1; /* General control */
  1872. u8 res27[12];
  1873. u8 res28[4];
  1874. u32 cgensrl; /* Core general status */
  1875. u8 res29[8];
  1876. u8 res30[4];
  1877. u32 cgencrl; /* Core general control */
  1878. u8 res31[184];
  1879. u32 sriopstecr; /* SRIO prescaler timer enable control */
  1880. u32 dcsrcr; /* DCSR Control register */
  1881. u8 res31a[56];
  1882. u32 tp_ityp[64]; /* Topology Initiator Type Register */
  1883. struct {
  1884. u32 upper;
  1885. u32 lower;
  1886. } tp_cluster[16]; /* Core Cluster n Topology Register */
  1887. u8 res32[1344];
  1888. u32 pmuxcr; /* Pin multiplexing control */
  1889. u8 res33[60];
  1890. u32 iovselsr; /* I/O voltage selection status */
  1891. u8 res34[28];
  1892. u32 ddrclkdr; /* DDR clock disable */
  1893. u8 res35;
  1894. u32 elbcclkdr; /* eLBC clock disable */
  1895. u8 res36[20];
  1896. u32 sdhcpcr; /* eSDHC polarity configuration */
  1897. u8 res37[380];
  1898. } ccsr_gur_t;
  1899. #define TP_ITYP_AV 0x00000001 /* Initiator available */
  1900. #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
  1901. #define TP_ITYP_TYPE_OTHER 0x0
  1902. #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
  1903. #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
  1904. #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
  1905. #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
  1906. #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
  1907. #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
  1908. #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
  1909. #define TP_INIT_PER_CLUSTER 4
  1910. #define FSL_CORENET_DCSR_SZ_MASK 0x00000003
  1911. #define FSL_CORENET_DCSR_SZ_4M 0x0
  1912. #define FSL_CORENET_DCSR_SZ_1G 0x3
  1913. /*
  1914. * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
  1915. * everything after has RMan thus msg unit LIODN is used for maintenance
  1916. */
  1917. #define rmuliodnr rio1maintliodnr
  1918. typedef struct ccsr_clk {
  1919. struct {
  1920. u32 clkcncsr; /* core cluster n clock control status */
  1921. u8 res_004[0x0c];
  1922. u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
  1923. u8 res_014[0x0c];
  1924. } clkcsr[12];
  1925. u8 res_100[0x680]; /* 0x100 */
  1926. struct {
  1927. u32 pllcngsr;
  1928. u8 res10[0x1c];
  1929. } pllcgsr[12];
  1930. u8 res21[0x280];
  1931. u32 pllpgsr; /* 0xc00 Platform PLL General Status */
  1932. u8 res16[0x1c];
  1933. u32 plldgsr; /* 0xc20 DDR PLL General Status */
  1934. u8 res17[0x3dc];
  1935. } ccsr_clk_t;
  1936. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  1937. typedef struct ccsr_rcpm {
  1938. u8 res_00[12];
  1939. u32 tph10sr0; /* Thread PH10 Status Register */
  1940. u8 res_10[12];
  1941. u32 tph10setr0; /* Thread PH10 Set Control Register */
  1942. u8 res_20[12];
  1943. u32 tph10clrr0; /* Thread PH10 Clear Control Register */
  1944. u8 res_30[12];
  1945. u32 tph10psr0; /* Thread PH10 Previous Status Register */
  1946. u8 res_40[12];
  1947. u32 twaitsr0; /* Thread Wait Status Register */
  1948. u8 res_50[96];
  1949. u32 pcph15sr; /* Physical Core PH15 Status Register */
  1950. u32 pcph15setr; /* Physical Core PH15 Set Control Register */
  1951. u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
  1952. u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
  1953. u8 res_c0[16];
  1954. u32 pcph20sr; /* Physical Core PH20 Status Register */
  1955. u32 pcph20setr; /* Physical Core PH20 Set Control Register */
  1956. u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
  1957. u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
  1958. u32 pcpw20sr; /* Physical Core PW20 Status Register */
  1959. u8 res_e0[12];
  1960. u32 pcph30sr; /* Physical Core PH30 Status Register */
  1961. u32 pcph30setr; /* Physical Core PH30 Set Control Register */
  1962. u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
  1963. u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
  1964. u8 res_100[32];
  1965. u32 ippwrgatecr; /* IP Power Gating Control Register */
  1966. u8 res_124[12];
  1967. u32 powmgtcsr; /* Power Management Control & Status Reg */
  1968. u8 res_134[12];
  1969. u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
  1970. u8 res_150[12];
  1971. u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
  1972. u8 res_160[12];
  1973. u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
  1974. u8 res_170[12];
  1975. u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
  1976. u8 res_180[12];
  1977. u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
  1978. u8 res_190[12];
  1979. u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
  1980. u32 pctbenr; /* Physical Core Time Base Enable Reg */
  1981. u32 pctbclkselr; /* Physical Core Time Base Clock Select */
  1982. u32 tbclkdivr; /* Time Base Clock Divider Register */
  1983. u8 res_1ac[4];
  1984. u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
  1985. u32 clpcl10sr; /* Cluster PCL10 Status Register */
  1986. u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
  1987. u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
  1988. u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
  1989. u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
  1990. u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
  1991. u32 cdpwroksetr; /* Core Domain Power OK Set Register */
  1992. u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
  1993. u32 cdpwrensr; /* Core Domain Power Enable Status Register */
  1994. u32 cddslsr; /* Core Domain Deep Sleep Status Register */
  1995. u8 res_1e8[8];
  1996. u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
  1997. u8 res_300[3568];
  1998. } ccsr_rcpm_t;
  1999. #define ctbenrl pctbenr
  2000. #else
  2001. typedef struct ccsr_rcpm {
  2002. u8 res1[4];
  2003. u32 cdozsrl; /* Core Doze Status */
  2004. u8 res2[4];
  2005. u32 cdozcrl; /* Core Doze Control */
  2006. u8 res3[4];
  2007. u32 cnapsrl; /* Core Nap Status */
  2008. u8 res4[4];
  2009. u32 cnapcrl; /* Core Nap Control */
  2010. u8 res5[4];
  2011. u32 cdozpsrl; /* Core Doze Previous Status */
  2012. u8 res6[4];
  2013. u32 cdozpcrl; /* Core Doze Previous Control */
  2014. u8 res7[4];
  2015. u32 cwaitsrl; /* Core Wait Status */
  2016. u8 res8[8];
  2017. u32 powmgtcsr; /* Power Mangement Control & Status */
  2018. u8 res9[12];
  2019. u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
  2020. u8 res10[12];
  2021. u8 res11[4];
  2022. u32 cpmimrl; /* Core PM IRQ Masking */
  2023. u8 res12[4];
  2024. u32 cpmcimrl; /* Core PM Critical IRQ Masking */
  2025. u8 res13[4];
  2026. u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
  2027. u8 res14[4];
  2028. u32 cpmnmimrl; /* Core PM NMI Masking */
  2029. u8 res15[4];
  2030. u32 ctbenrl; /* Core Time Base Enable */
  2031. u8 res16[4];
  2032. u32 ctbclkselrl; /* Core Time Base Clock Select */
  2033. u8 res17[4];
  2034. u32 ctbhltcrl; /* Core Time Base Halt Control */
  2035. u8 res18[0xf68];
  2036. } ccsr_rcpm_t;
  2037. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  2038. #else
  2039. typedef struct ccsr_gur {
  2040. u32 porpllsr; /* POR PLL ratio status */
  2041. #ifdef CONFIG_ARCH_MPC8536
  2042. #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
  2043. #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
  2044. #elif defined(CONFIG_ARCH_C29X)
  2045. #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
  2046. #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
  2047. & MPC85xx_PORDEVSR2_DDR_SPD_0) \
  2048. >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
  2049. #else
  2050. #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
  2051. #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
  2052. #else
  2053. #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
  2054. #endif
  2055. #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
  2056. #endif
  2057. #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
  2058. #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
  2059. #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
  2060. #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
  2061. u32 porbmsr; /* POR boot mode status */
  2062. #define MPC85xx_PORBMSR_HA 0x00070000
  2063. #define MPC85xx_PORBMSR_HA_SHIFT 16
  2064. #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
  2065. #define PORBMSR_ROMLOC_SPI 0x6
  2066. #define PORBMSR_ROMLOC_SDHC 0x7
  2067. #define PORBMSR_ROMLOC_NAND_2K 0x9
  2068. #define PORBMSR_ROMLOC_NOR 0xf
  2069. u32 porimpscr; /* POR I/O impedance status & control */
  2070. u32 pordevsr; /* POR I/O device status regsiter */
  2071. #if defined(CONFIG_ARCH_P1023)
  2072. #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
  2073. #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
  2074. #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
  2075. #else
  2076. #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
  2077. #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
  2078. #endif
  2079. #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
  2080. #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
  2081. #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
  2082. #define MPC85xx_PORDEVSR_PCI1 0x00800000
  2083. #if defined(CONFIG_ARCH_P1022)
  2084. #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
  2085. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
  2086. #elif defined(CONFIG_ARCH_P1023)
  2087. #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
  2088. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
  2089. #else
  2090. #if defined(CONFIG_ARCH_P1010)
  2091. #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
  2092. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
  2093. #elif defined(CONFIG_ARCH_BSC9132)
  2094. #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
  2095. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
  2096. #elif defined(CONFIG_ARCH_C29X)
  2097. #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
  2098. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
  2099. #else
  2100. #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
  2101. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
  2102. #endif /* if defined(CONFIG_ARCH_P1010) */
  2103. #endif
  2104. #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
  2105. #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
  2106. #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
  2107. #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
  2108. #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
  2109. #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
  2110. #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
  2111. #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
  2112. u32 pordbgmsr; /* POR debug mode status */
  2113. u32 pordevsr2; /* POR I/O device status 2 */
  2114. #if defined(CONFIG_ARCH_C29X)
  2115. #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
  2116. #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
  2117. #endif
  2118. #define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
  2119. /* The 8544 RM says this is bit 26, but it's really bit 24 */
  2120. #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
  2121. u8 res1[8];
  2122. u32 gpporcr; /* General-purpose POR configuration */
  2123. u8 res2[12];
  2124. #if defined(CONFIG_ARCH_MPC8536)
  2125. u32 gencfgr; /* General Configuration Register */
  2126. #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
  2127. #else
  2128. u32 gpiocr; /* GPIO control */
  2129. #endif
  2130. u8 res3[12];
  2131. u32 gpoutdr; /* General-purpose output data */
  2132. u8 res4[12];
  2133. u32 gpindr; /* General-purpose input data */
  2134. u8 res5[12];
  2135. u32 pmuxcr; /* Alt. function signal multiplex control */
  2136. #if defined(CONFIG_ARCH_P1010)
  2137. #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
  2138. #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
  2139. #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
  2140. #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
  2141. #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
  2142. #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
  2143. #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
  2144. #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
  2145. #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
  2146. #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
  2147. #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
  2148. #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
  2149. #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
  2150. #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
  2151. #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
  2152. #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
  2153. #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
  2154. #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
  2155. #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
  2156. #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
  2157. #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
  2158. #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
  2159. #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
  2160. #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
  2161. #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
  2162. #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
  2163. #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
  2164. #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
  2165. #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
  2166. #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
  2167. #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
  2168. #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
  2169. #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
  2170. #define MPC85xx_PMUXCR_LCLK_RES 0x00000040
  2171. #define MPC85xx_PMUXCR_LCLK_USB 0x00000080
  2172. #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
  2173. #define MPC85xx_PMUXCR_SPI_RES 0x00000030
  2174. #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
  2175. #define MPC85xx_PMUXCR_CAN1_UART 0x00000004
  2176. #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
  2177. #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
  2178. #define MPC85xx_PMUXCR_CAN2_UART 0x00000001
  2179. #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
  2180. #define MPC85xx_PMUXCR_CAN2_RES 0x00000003
  2181. #endif
  2182. #if defined(CONFIG_ARCH_P1023)
  2183. #define MPC85xx_PMUXCR_TSEC1_1 0x10000000
  2184. #else
  2185. #define MPC85xx_PMUXCR_SD_DATA 0x80000000
  2186. #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
  2187. #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
  2188. #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
  2189. #define MPC85xx_PMUXCR_TDM_ENA 0x00800000
  2190. #define MPC85xx_PMUXCR_QE0 0x00008000
  2191. #define MPC85xx_PMUXCR_QE1 0x00004000
  2192. #define MPC85xx_PMUXCR_QE2 0x00002000
  2193. #define MPC85xx_PMUXCR_QE3 0x00001000
  2194. #define MPC85xx_PMUXCR_QE4 0x00000800
  2195. #define MPC85xx_PMUXCR_QE5 0x00000400
  2196. #define MPC85xx_PMUXCR_QE6 0x00000200
  2197. #define MPC85xx_PMUXCR_QE7 0x00000100
  2198. #define MPC85xx_PMUXCR_QE8 0x00000080
  2199. #define MPC85xx_PMUXCR_QE9 0x00000040
  2200. #define MPC85xx_PMUXCR_QE10 0x00000020
  2201. #define MPC85xx_PMUXCR_QE11 0x00000010
  2202. #define MPC85xx_PMUXCR_QE12 0x00000008
  2203. #endif
  2204. #if defined(CONFIG_ARCH_P1022)
  2205. #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
  2206. #define MPC85xx_PMUXCR_TDM 0x00014800
  2207. #define MPC85xx_PMUXCR_SPI_MASK 0x00600000
  2208. #define MPC85xx_PMUXCR_SPI 0x00000000
  2209. #endif
  2210. #if defined(CONFIG_ARCH_BSC9131)
  2211. #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
  2212. #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
  2213. #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
  2214. #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
  2215. #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
  2216. #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
  2217. #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
  2218. #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
  2219. #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
  2220. #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
  2221. #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
  2222. #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
  2223. #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
  2224. #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
  2225. #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
  2226. #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
  2227. #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
  2228. #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
  2229. #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
  2230. #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
  2231. #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
  2232. #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
  2233. #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
  2234. #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
  2235. #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
  2236. #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
  2237. #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
  2238. #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
  2239. #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
  2240. #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
  2241. #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
  2242. #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
  2243. #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
  2244. #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
  2245. #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
  2246. #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
  2247. #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
  2248. #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
  2249. #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
  2250. #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
  2251. #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
  2252. #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
  2253. #endif
  2254. #ifdef CONFIG_ARCH_BSC9132
  2255. #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
  2256. #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
  2257. #endif
  2258. #if defined(CONFIG_ARCH_C29X)
  2259. #define MPC85xx_PMUXCR_SPI_MASK 0x00000300
  2260. #define MPC85xx_PMUXCR_SPI 0x00000000
  2261. #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
  2262. #endif
  2263. u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
  2264. #if defined(CONFIG_ARCH_P1010)
  2265. #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
  2266. #define MPC85xx_PMUXCR2_UART_TDM 0x80000000
  2267. #define MPC85xx_PMUXCR2_UART_RES 0xC0000000
  2268. #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
  2269. #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
  2270. #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
  2271. #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
  2272. #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
  2273. #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
  2274. #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
  2275. #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
  2276. #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
  2277. #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
  2278. #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
  2279. #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
  2280. #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
  2281. #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
  2282. #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
  2283. #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
  2284. #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
  2285. #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
  2286. #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
  2287. #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
  2288. #endif
  2289. #if defined(CONFIG_ARCH_P1022)
  2290. #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
  2291. #define MPC85xx_PMUXCR2_USB 0x00150000
  2292. #endif
  2293. #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
  2294. #if defined(CONFIG_ARCH_BSC9131)
  2295. #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
  2296. #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
  2297. #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
  2298. #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
  2299. #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
  2300. #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
  2301. #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
  2302. #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
  2303. #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
  2304. #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
  2305. #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
  2306. #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
  2307. #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
  2308. #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
  2309. #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
  2310. #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
  2311. #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
  2312. #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
  2313. #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
  2314. #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
  2315. #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
  2316. #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
  2317. #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
  2318. #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
  2319. #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
  2320. #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
  2321. #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
  2322. #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
  2323. #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
  2324. #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
  2325. #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
  2326. #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
  2327. #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
  2328. #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
  2329. #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
  2330. #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
  2331. #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
  2332. #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
  2333. #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
  2334. #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
  2335. #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
  2336. #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
  2337. #endif
  2338. u32 pmuxcr3;
  2339. #if defined(CONFIG_ARCH_BSC9131)
  2340. #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
  2341. #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
  2342. #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
  2343. #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
  2344. #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
  2345. #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
  2346. #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
  2347. #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
  2348. #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
  2349. #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
  2350. #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
  2351. #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
  2352. #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
  2353. #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
  2354. #endif
  2355. #ifdef CONFIG_ARCH_BSC9132
  2356. #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
  2357. #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
  2358. #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
  2359. #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
  2360. #endif
  2361. u32 pmuxcr4;
  2362. #else
  2363. u8 res6[8];
  2364. #endif
  2365. u32 devdisr; /* Device disable control */
  2366. #define MPC85xx_DEVDISR_PCI1 0x80000000
  2367. #define MPC85xx_DEVDISR_PCI2 0x40000000
  2368. #define MPC85xx_DEVDISR_PCIE 0x20000000
  2369. #define MPC85xx_DEVDISR_LBC 0x08000000
  2370. #define MPC85xx_DEVDISR_PCIE2 0x04000000
  2371. #define MPC85xx_DEVDISR_PCIE3 0x02000000
  2372. #define MPC85xx_DEVDISR_SEC 0x01000000
  2373. #define MPC85xx_DEVDISR_SRIO 0x00080000
  2374. #define MPC85xx_DEVDISR_RMSG 0x00040000
  2375. #define MPC85xx_DEVDISR_DDR 0x00010000
  2376. #define MPC85xx_DEVDISR_CPU 0x00008000
  2377. #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
  2378. #define MPC85xx_DEVDISR_TB 0x00004000
  2379. #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
  2380. #define MPC85xx_DEVDISR_CPU1 0x00002000
  2381. #define MPC85xx_DEVDISR_TB1 0x00001000
  2382. #define MPC85xx_DEVDISR_DMA 0x00000400
  2383. #define MPC85xx_DEVDISR_TSEC1 0x00000080
  2384. #define MPC85xx_DEVDISR_TSEC2 0x00000040
  2385. #define MPC85xx_DEVDISR_TSEC3 0x00000020
  2386. #define MPC85xx_DEVDISR_TSEC4 0x00000010
  2387. #define MPC85xx_DEVDISR_I2C 0x00000004
  2388. #define MPC85xx_DEVDISR_DUART 0x00000002
  2389. u8 res7[12];
  2390. u32 powmgtcsr; /* Power management status & control */
  2391. u8 res8[12];
  2392. u32 mcpsumr; /* Machine check summary */
  2393. u8 res9[12];
  2394. u32 pvr; /* Processor version */
  2395. u32 svr; /* System version */
  2396. u8 res10[8];
  2397. u32 rstcr; /* Reset control */
  2398. #if defined(CONFIG_ARCH_MPC8568)
  2399. u8 res11a[76];
  2400. par_io_t qe_par_io[7];
  2401. u8 res11b[1600];
  2402. #elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  2403. u8 res11a[12];
  2404. u32 iovselsr;
  2405. u8 res11b[60];
  2406. par_io_t qe_par_io[3];
  2407. u8 res11c[1496];
  2408. #else
  2409. u8 res11a[1868];
  2410. #endif
  2411. u32 clkdvdr; /* Clock Divide register */
  2412. u8 res12[1532];
  2413. u32 clkocr; /* Clock out select */
  2414. u8 res13[12];
  2415. u32 ddrdllcr; /* DDR DLL control */
  2416. u8 res14[12];
  2417. u32 lbcdllcr; /* LBC DLL control */
  2418. #if defined(CONFIG_ARCH_BSC9131)
  2419. u8 res15[12];
  2420. u32 halt_req_mask;
  2421. #define HALTED_TO_HALT_REQ_MASK_0 0x80000000
  2422. u8 res18[232];
  2423. #else
  2424. u8 res15[248];
  2425. #endif
  2426. u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
  2427. u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
  2428. u32 ddrioovcr; /* DDR IO Override Control */
  2429. u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
  2430. u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
  2431. u8 res16[52];
  2432. u32 sdhcdcr; /* SDHC debug control register */
  2433. u8 res17[61592];
  2434. } ccsr_gur_t;
  2435. #endif
  2436. #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
  2437. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  2438. #define MAX_SERDES 4
  2439. #if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
  2440. #define SRDS_MAX_LANES 4
  2441. #else
  2442. #define SRDS_MAX_LANES 8
  2443. #endif
  2444. #define SRDS_MAX_BANK 2
  2445. typedef struct serdes_corenet {
  2446. struct {
  2447. u32 rstctl; /* Reset Control Register */
  2448. #define SRDS_RSTCTL_RST 0x80000000
  2449. #define SRDS_RSTCTL_RSTDONE 0x40000000
  2450. #define SRDS_RSTCTL_RSTERR 0x20000000
  2451. #define SRDS_RSTCTL_SWRST 0x10000000
  2452. #define SRDS_RSTCTL_SDEN 0x00000020
  2453. #define SRDS_RSTCTL_SDRST_B 0x00000040
  2454. #define SRDS_RSTCTL_PLLRST_B 0x00000080
  2455. #define SRDS_RSTCTL_RSTERR_SHIFT 29
  2456. u32 pllcr0; /* PLL Control Register 0 */
  2457. #define SRDS_PLLCR0_POFF 0x80000000
  2458. #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
  2459. #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
  2460. #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
  2461. #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
  2462. #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
  2463. #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
  2464. #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
  2465. #define SRDS_PLLCR0_PLL_LCK 0x00800000
  2466. #define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
  2467. #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
  2468. #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
  2469. #define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
  2470. #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
  2471. #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
  2472. #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
  2473. #define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
  2474. #define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
  2475. #define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
  2476. #define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
  2477. #define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
  2478. u32 pllcr1; /* PLL Control Register 1 */
  2479. #define SRDS_PLLCR1_BCAP_EN 0x20000000
  2480. #define SRDS_PLLCR1_BCAP_OVD 0x10000000
  2481. #define SRDS_PLLCR1_PLL_FCAP 0x001F8000
  2482. #define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
  2483. #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
  2484. #define SRDS_PLLCR1_BYP_CAL 0x02000000
  2485. u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
  2486. #define SRDS_PLLSR2_BCAP_EN 0x00800000
  2487. #define SRDS_PLLSR2_BCAP_EN_SHIFT 23
  2488. #define SRDS_PLLSR2_FCAP 0x003F0000
  2489. #define SRDS_PLLSR2_FCAP_SHIFT 16
  2490. #define SRDS_PLLSR2_DCBIAS 0x000F0000
  2491. #define SRDS_PLLSR2_DCBIAS_SHIFT 16
  2492. u32 pllcr3;
  2493. u32 pllcr4;
  2494. u8 res_18[0x20-0x18];
  2495. } bank[2];
  2496. u8 res_40[0x90-0x40];
  2497. u32 srdstcalcr; /* 0x90 TX Calibration Control */
  2498. u8 res_94[0xa0-0x94];
  2499. u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
  2500. u8 res_a4[0xb0-0xa4];
  2501. u32 srdsgr0; /* 0xb0 General Register 0 */
  2502. u8 res_b4[0xe0-0xb4];
  2503. u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
  2504. u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
  2505. u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
  2506. u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
  2507. u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
  2508. u8 res_f4[0x100-0xf4];
  2509. struct {
  2510. u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
  2511. u8 res_104[0x120-0x104];
  2512. } srdslnpssr[8];
  2513. u8 res_200[0x800-0x200];
  2514. struct {
  2515. u32 gcr0; /* 0x800 General Control Register 0 */
  2516. u32 gcr1; /* 0x804 General Control Register 1 */
  2517. u32 gcr2; /* 0x808 General Control Register 2 */
  2518. u32 res_80c;
  2519. u32 recr0; /* 0x810 Receive Equalization Control */
  2520. u32 res_814;
  2521. u32 tecr0; /* 0x818 Transmit Equalization Control */
  2522. u32 res_81c;
  2523. u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
  2524. u8 res_824[0x840-0x824];
  2525. } lane[8]; /* Lane A, B, C, D, E, F, G, H */
  2526. u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
  2527. } serdes_corenet_t;
  2528. #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  2529. #define SRDS_MAX_LANES 18
  2530. #define SRDS_MAX_BANK 3
  2531. typedef struct serdes_corenet {
  2532. struct {
  2533. u32 rstctl; /* Reset Control Register */
  2534. #define SRDS_RSTCTL_RST 0x80000000
  2535. #define SRDS_RSTCTL_RSTDONE 0x40000000
  2536. #define SRDS_RSTCTL_RSTERR 0x20000000
  2537. #define SRDS_RSTCTL_SDPD 0x00000020
  2538. u32 pllcr0; /* PLL Control Register 0 */
  2539. #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
  2540. #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
  2541. #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
  2542. #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
  2543. #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
  2544. #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
  2545. #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
  2546. #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
  2547. #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
  2548. #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
  2549. u32 pllcr1; /* PLL Control Register 1 */
  2550. #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
  2551. u32 res[5];
  2552. } bank[3];
  2553. u32 res1[12];
  2554. u32 srdstcalcr; /* TX Calibration Control */
  2555. u32 res2[3];
  2556. u32 srdsrcalcr; /* RX Calibration Control */
  2557. u32 res3[3];
  2558. u32 srdsgr0; /* General Register 0 */
  2559. u32 res4[11];
  2560. u32 srdspccr0; /* Protocol Converter Config 0 */
  2561. u32 srdspccr1; /* Protocol Converter Config 1 */
  2562. u32 srdspccr2; /* Protocol Converter Config 2 */
  2563. #define SRDS_PCCR2_RST_XGMII1 0x00800000
  2564. #define SRDS_PCCR2_RST_XGMII2 0x00400000
  2565. u32 res5[197];
  2566. struct serdes_lane {
  2567. u32 gcr0; /* General Control Register 0 */
  2568. #define SRDS_GCR0_RRST 0x00400000
  2569. #define SRDS_GCR0_1STLANE 0x00010000
  2570. #define SRDS_GCR0_UOTHL 0x00100000
  2571. u32 gcr1; /* General Control Register 1 */
  2572. #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
  2573. #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
  2574. #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
  2575. #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
  2576. #define SRDS_GCR1_OPAD_CTL 0x04000000
  2577. u32 res1[4];
  2578. u32 tecr0; /* TX Equalization Control Reg 0 */
  2579. #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
  2580. #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
  2581. u32 res3;
  2582. u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
  2583. #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
  2584. #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
  2585. #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
  2586. #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
  2587. #define SRDS_TTLCR0_PM_DIS 0x00004000
  2588. #define SRDS_TTLCR0_FREQOVD_EN 0x00000001
  2589. u32 res4[7];
  2590. } lane[24];
  2591. u32 res6[384];
  2592. } serdes_corenet_t;
  2593. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  2594. enum {
  2595. FSL_SRDS_B1_LANE_A = 0,
  2596. FSL_SRDS_B1_LANE_B = 1,
  2597. FSL_SRDS_B1_LANE_C = 2,
  2598. FSL_SRDS_B1_LANE_D = 3,
  2599. FSL_SRDS_B1_LANE_E = 4,
  2600. FSL_SRDS_B1_LANE_F = 5,
  2601. FSL_SRDS_B1_LANE_G = 6,
  2602. FSL_SRDS_B1_LANE_H = 7,
  2603. FSL_SRDS_B1_LANE_I = 8,
  2604. FSL_SRDS_B1_LANE_J = 9,
  2605. FSL_SRDS_B2_LANE_A = 16,
  2606. FSL_SRDS_B2_LANE_B = 17,
  2607. FSL_SRDS_B2_LANE_C = 18,
  2608. FSL_SRDS_B2_LANE_D = 19,
  2609. FSL_SRDS_B3_LANE_A = 20,
  2610. FSL_SRDS_B3_LANE_B = 21,
  2611. FSL_SRDS_B3_LANE_C = 22,
  2612. FSL_SRDS_B3_LANE_D = 23,
  2613. };
  2614. typedef struct ccsr_pme {
  2615. u8 res0[0x804];
  2616. u32 liodnbr; /* LIODN Base Register */
  2617. u8 res1[0x1f8];
  2618. u32 srcidr; /* Source ID Register */
  2619. u8 res2[8];
  2620. u32 liodnr; /* LIODN Register */
  2621. u8 res3[0x1e8];
  2622. u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
  2623. u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
  2624. u8 res4[0x400];
  2625. } ccsr_pme_t;
  2626. struct ccsr_pamu {
  2627. u32 ppbah;
  2628. u32 ppbal;
  2629. u32 pplah;
  2630. u32 pplal;
  2631. u32 spbah;
  2632. u32 spbal;
  2633. u32 splah;
  2634. u32 splal;
  2635. u32 obah;
  2636. u32 obal;
  2637. u32 olah;
  2638. u32 olal;
  2639. };
  2640. #ifdef CONFIG_SYS_FSL_RAID_ENGINE
  2641. struct ccsr_raide {
  2642. u8 res0[0x543];
  2643. u32 liodnbr; /* LIODN Base Register */
  2644. u8 res1[0xab8];
  2645. struct {
  2646. struct {
  2647. u32 cfg0; /* cfg register 0 */
  2648. u32 cfg1; /* cfg register 1 */
  2649. u8 res1[0x3f8];
  2650. } ring[2];
  2651. u8 res[0x800];
  2652. } jq[2];
  2653. };
  2654. #endif
  2655. #ifdef CONFIG_SYS_DPAA_RMAN
  2656. struct ccsr_rman {
  2657. u8 res0[0xf64];
  2658. u32 mmliodnbr; /* Message Manager LIODN Base Register */
  2659. u32 mmitar; /* RMAN Inbound Translation Address Register */
  2660. u32 mmitdr; /* RMAN Inbound Translation Data Register */
  2661. u8 res4[0x1f090];
  2662. };
  2663. #endif
  2664. #ifdef CONFIG_SYS_PMAN
  2665. struct ccsr_pman {
  2666. u8 res_00[0x40];
  2667. u32 poes1; /* PMAN Operation Error Status Register 1 */
  2668. u32 poes2; /* PMAN Operation Error Status Register 2 */
  2669. u32 poeah; /* PMAN Operation Error Address High */
  2670. u32 poeal; /* PMAN Operation Error Address Low */
  2671. u8 res_50[0x50];
  2672. u32 pr1; /* PMAN Revision Register 1 */
  2673. u32 pr2; /* PMAN Revision Register 2 */
  2674. u8 res_a8[0x8];
  2675. u32 pcap; /* PMAN Capabilities Register */
  2676. u8 res_b4[0xc];
  2677. u32 pc1; /* PMAN Control Register 1 */
  2678. u32 pc2; /* PMAN Control Register 2 */
  2679. u32 pc3; /* PMAN Control Register 3 */
  2680. u32 pc4; /* PMAN Control Register 4 */
  2681. u32 pc5; /* PMAN Control Register 5 */
  2682. u32 pc6; /* PMAN Control Register 6 */
  2683. u8 res_d8[0x8];
  2684. u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
  2685. u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
  2686. u8 res_e8[0x8];
  2687. u32 pics; /* PMAN Interrupt Control and Status */
  2688. u8 res_f4[0xf0c];
  2689. };
  2690. #endif
  2691. #ifdef CONFIG_FSL_CORENET
  2692. #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
  2693. #ifdef CONFIG_SYS_PMAN
  2694. #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
  2695. #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
  2696. #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
  2697. #endif
  2698. #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
  2699. #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
  2700. #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
  2701. #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
  2702. #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
  2703. #ifdef CONFIG_SYS_FSL_SFP_VER_3_0
  2704. /* In SFPv3, OSPR register is now at offset 0x200.
  2705. * * So directly mapping sfp register map to this address */
  2706. #define CONFIG_SYS_OSPR_OFFSET 0x200
  2707. #define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
  2708. #else
  2709. #define CONFIG_SYS_SFP_OFFSET 0xE8000
  2710. #endif
  2711. #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
  2712. #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
  2713. #define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
  2714. #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
  2715. #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
  2716. #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
  2717. #define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
  2718. #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
  2719. #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
  2720. #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
  2721. #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
  2722. #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
  2723. #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
  2724. #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
  2725. #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
  2726. #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
  2727. #define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
  2728. #define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
  2729. #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
  2730. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
  2731. !defined(CONFIG_ARCH_B4420)
  2732. #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
  2733. #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
  2734. #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
  2735. #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
  2736. #else
  2737. #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
  2738. #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
  2739. #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
  2740. #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
  2741. #endif
  2742. #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
  2743. #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
  2744. #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
  2745. #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
  2746. #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
  2747. #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
  2748. #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
  2749. #define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
  2750. #define CONFIG_SYS_SEC_MON_OFFSET 0x314000
  2751. #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
  2752. #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
  2753. #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
  2754. #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
  2755. #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
  2756. #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
  2757. #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
  2758. #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
  2759. #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
  2760. #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
  2761. #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
  2762. #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
  2763. #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
  2764. #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
  2765. #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
  2766. #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
  2767. #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
  2768. #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
  2769. #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
  2770. #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
  2771. #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
  2772. #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
  2773. #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
  2774. #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
  2775. #else
  2776. #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
  2777. #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
  2778. #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
  2779. #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
  2780. #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
  2781. #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
  2782. #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
  2783. #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
  2784. #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
  2785. #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
  2786. #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
  2787. #if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
  2788. #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
  2789. #else
  2790. #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
  2791. #endif
  2792. #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
  2793. #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
  2794. #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
  2795. #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
  2796. #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
  2797. #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
  2798. #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
  2799. #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
  2800. #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
  2801. #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
  2802. #ifdef CONFIG_TSECV2
  2803. #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
  2804. #elif defined(CONFIG_TSECV2_1)
  2805. #define CONFIG_SYS_TSEC1_OFFSET 0x10000
  2806. #else
  2807. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  2808. #endif
  2809. #define CONFIG_SYS_MDIO1_OFFSET 0x24000
  2810. #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
  2811. #if defined(CONFIG_ARCH_C29X)
  2812. #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
  2813. #define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
  2814. #else
  2815. #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
  2816. #define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
  2817. #endif
  2818. #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
  2819. #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
  2820. #define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
  2821. #define CONFIG_SYS_SFP_OFFSET 0xE7000
  2822. #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
  2823. #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
  2824. #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
  2825. #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
  2826. #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
  2827. #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
  2828. #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
  2829. #endif
  2830. #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
  2831. #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
  2832. #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
  2833. #if defined(CONFIG_ARCH_BSC9132)
  2834. #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
  2835. #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
  2836. (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
  2837. #endif
  2838. #define CONFIG_SYS_FSL_CPC_ADDR \
  2839. (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
  2840. #define CONFIG_SYS_FSL_SCFG_ADDR \
  2841. (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
  2842. #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
  2843. (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
  2844. #define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
  2845. (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
  2846. #define CONFIG_SYS_FSL_QMAN_ADDR \
  2847. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
  2848. #define CONFIG_SYS_FSL_BMAN_ADDR \
  2849. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
  2850. #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
  2851. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
  2852. #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
  2853. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
  2854. #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
  2855. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
  2856. #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
  2857. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
  2858. #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
  2859. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
  2860. #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
  2861. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
  2862. #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
  2863. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
  2864. #define CONFIG_SYS_MPC85xx_ECM_ADDR \
  2865. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
  2866. #define CONFIG_SYS_FSL_DDR_ADDR \
  2867. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
  2868. #define CONFIG_SYS_FSL_DDR2_ADDR \
  2869. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
  2870. #define CONFIG_SYS_FSL_DDR3_ADDR \
  2871. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
  2872. #define CONFIG_SYS_LBC_ADDR \
  2873. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
  2874. #define CONFIG_SYS_IFC_ADDR \
  2875. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
  2876. #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
  2877. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
  2878. #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
  2879. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
  2880. #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
  2881. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
  2882. #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
  2883. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
  2884. #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
  2885. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
  2886. #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
  2887. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
  2888. #define CONFIG_SYS_MPC85xx_L2_ADDR \
  2889. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
  2890. #define CONFIG_SYS_MPC85xx_DMA_ADDR \
  2891. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
  2892. #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
  2893. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
  2894. #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
  2895. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
  2896. #define CONFIG_SYS_MPC85xx_CPM_ADDR \
  2897. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
  2898. #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
  2899. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
  2900. #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
  2901. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
  2902. #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
  2903. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
  2904. #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
  2905. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
  2906. #define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
  2907. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
  2908. #define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
  2909. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
  2910. #define CONFIG_SYS_MPC85xx_USB1_ADDR \
  2911. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
  2912. #define CONFIG_SYS_MPC85xx_USB2_ADDR \
  2913. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
  2914. #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
  2915. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
  2916. #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
  2917. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
  2918. #define CONFIG_SYS_FSL_SEC_ADDR \
  2919. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
  2920. #define CONFIG_SYS_FSL_JR0_ADDR \
  2921. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
  2922. #define CONFIG_SYS_FSL_FM1_ADDR \
  2923. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
  2924. #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
  2925. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
  2926. #define CONFIG_SYS_FSL_FM2_ADDR \
  2927. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
  2928. #define CONFIG_SYS_FSL_SRIO_ADDR \
  2929. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
  2930. #define CONFIG_SYS_PAMU_ADDR \
  2931. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
  2932. #define CONFIG_SYS_PCI1_ADDR \
  2933. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
  2934. #define CONFIG_SYS_PCI2_ADDR \
  2935. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
  2936. #define CONFIG_SYS_PCIE1_ADDR \
  2937. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
  2938. #define CONFIG_SYS_PCIE2_ADDR \
  2939. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
  2940. #define CONFIG_SYS_PCIE3_ADDR \
  2941. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
  2942. #define CONFIG_SYS_PCIE4_ADDR \
  2943. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
  2944. #define CONFIG_SYS_SFP_ADDR \
  2945. (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
  2946. #define CONFIG_SYS_SEC_MON_ADDR \
  2947. (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
  2948. #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  2949. #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
  2950. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  2951. struct ccsr_cluster_l2 {
  2952. u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
  2953. u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
  2954. u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
  2955. u8 res_0c[500];/* 0x00c - 0x1ff */
  2956. u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
  2957. u8 res_204[4];
  2958. u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
  2959. u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
  2960. u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
  2961. u8 res_214[4];
  2962. u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
  2963. u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
  2964. u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
  2965. u8 res_224[4];
  2966. u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
  2967. u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
  2968. u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
  2969. u8 res_234[4];
  2970. u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
  2971. u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
  2972. u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
  2973. u8 res244[4];
  2974. u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
  2975. u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
  2976. u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
  2977. u8 res_254[4];
  2978. u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
  2979. u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
  2980. u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
  2981. u8 res_264[4];
  2982. u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
  2983. u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
  2984. u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
  2985. u8 res274[4];
  2986. u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
  2987. u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
  2988. u8 res_280[0xb80]; /* 0x280 - 0xdff */
  2989. u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
  2990. u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
  2991. u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
  2992. u8 res_e0c[20]; /* 0xe0c - 0x01f */
  2993. u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
  2994. u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
  2995. u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
  2996. u8 res_e2c[20]; /* 0xe2c - 0xe3f */
  2997. u32 l2errdet; /* 0xe40 L2 cache error detect */
  2998. u32 l2errdis; /* 0xe44 L2 cache error disable */
  2999. u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
  3000. u32 l2errattr; /* 0xe4c L2 cache error attribute */
  3001. u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
  3002. u32 l2erraddr; /* 0xe54 L2 cache error address */
  3003. u32 l2errctl; /* 0xe58 L2 cache error control */
  3004. };
  3005. #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
  3006. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
  3007. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  3008. #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
  3009. struct dcsr_dcfg_regs {
  3010. u8 res_0[0x520];
  3011. u32 ecccr1;
  3012. #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
  3013. #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
  3014. u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
  3015. };
  3016. #define CONFIG_SYS_MPC85xx_SCFG \
  3017. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
  3018. #define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
  3019. /* The supplement configuration unit register */
  3020. struct ccsr_scfg {
  3021. u32 dpslpcr; /* 0x000 Deep Sleep Control register */
  3022. u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
  3023. u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
  3024. u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
  3025. u32 res1[4];
  3026. u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
  3027. u32 res2;
  3028. u32 pixclkcr; /* 0x028 Pixel Clock Control register */
  3029. u32 res3[245];
  3030. u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
  3031. u32 emiiocr; /* 0x404 EMI MDIO Control Register */
  3032. u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
  3033. u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
  3034. u32 res4[60];
  3035. u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
  3036. };
  3037. #endif /*__IMMAP_85xx__*/