cpu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
  4. * (C) Copyright 2002, 2003 Motorola Inc.
  5. * Xianghua Xiao (X.Xiao@motorola.com)
  6. *
  7. * (C) Copyright 2000
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <init.h>
  14. #include <irq_func.h>
  15. #include <log.h>
  16. #include <time.h>
  17. #include <vsprintf.h>
  18. #include <watchdog.h>
  19. #include <command.h>
  20. #include <fsl_esdhc.h>
  21. #include <asm/cache.h>
  22. #include <asm/global_data.h>
  23. #include <asm/io.h>
  24. #include <asm/mmu.h>
  25. #include <fsl_ifc.h>
  26. #include <asm/fsl_law.h>
  27. #include <asm/fsl_lbc.h>
  28. #include <post.h>
  29. #include <asm/processor.h>
  30. #include <fsl_ddr_sdram.h>
  31. #include <asm/ppc.h>
  32. #include <linux/delay.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. /*
  35. * Default board reset function
  36. */
  37. static void
  38. __board_reset(void)
  39. {
  40. /* Do nothing */
  41. }
  42. void board_reset(void) __attribute__((weak, alias("__board_reset")));
  43. int checkcpu (void)
  44. {
  45. sys_info_t sysinfo;
  46. uint pvr, svr;
  47. uint ver;
  48. uint major, minor;
  49. struct cpu_type *cpu;
  50. char buf1[32], buf2[32];
  51. #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
  52. ccsr_gur_t __iomem *gur =
  53. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  54. #endif
  55. /*
  56. * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
  57. * mode. Previous platform use ddr ratio to do the same. This
  58. * information is only for display here.
  59. */
  60. #ifdef CONFIG_FSL_CORENET
  61. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  62. u32 ddr_sync = 0; /* only async mode is supported */
  63. #else
  64. u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
  65. >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
  66. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  67. #else /* CONFIG_FSL_CORENET */
  68. #ifdef CONFIG_DDR_CLK_FREQ
  69. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  70. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  71. #else
  72. u32 ddr_ratio = 0;
  73. #endif /* CONFIG_DDR_CLK_FREQ */
  74. #endif /* CONFIG_FSL_CORENET */
  75. unsigned int i, core, nr_cores = cpu_numcores();
  76. u32 mask = cpu_mask();
  77. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  78. unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
  79. u32 dsp_mask = cpu_dsp_mask();
  80. #endif
  81. svr = get_svr();
  82. major = SVR_MAJ(svr);
  83. minor = SVR_MIN(svr);
  84. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  85. if (SVR_SOC_VER(svr) == SVR_T4080) {
  86. ccsr_rcpm_t *rcpm =
  87. (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  88. setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
  89. FSL_CORENET_DEVDISR2_DTSEC1_9);
  90. setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
  91. setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
  92. /* It needs SW to disable core4~7 as HW design sake on T4080 */
  93. for (i = 4; i < 8; i++)
  94. cpu_disable(i);
  95. /* request core4~7 into PH20 state, prior to entering PCL10
  96. * state, all cores in cluster should be placed in PH20 state.
  97. */
  98. setbits_be32(&rcpm->pcph20setr, 0xf0);
  99. /* put the 2nd cluster into PCL10 state */
  100. setbits_be32(&rcpm->clpcl10setr, 1 << 1);
  101. }
  102. #endif
  103. if (cpu_numcores() > 1) {
  104. #ifndef CONFIG_MP
  105. puts("Unicore software on multiprocessor system!!\n"
  106. "To enable mutlticore build define CONFIG_MP\n");
  107. #endif
  108. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  109. printf("CPU%d: ", pic->whoami);
  110. } else {
  111. puts("CPU: ");
  112. }
  113. cpu = gd->arch.cpu;
  114. puts(cpu->name);
  115. if (IS_E_PROCESSOR(svr))
  116. puts("E");
  117. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  118. pvr = get_pvr();
  119. ver = PVR_VER(pvr);
  120. major = PVR_MAJ(pvr);
  121. minor = PVR_MIN(pvr);
  122. printf("Core: ");
  123. switch(ver) {
  124. case PVR_VER_E500_V1:
  125. case PVR_VER_E500_V2:
  126. puts("e500");
  127. break;
  128. case PVR_VER_E500MC:
  129. puts("e500mc");
  130. break;
  131. case PVR_VER_E5500:
  132. puts("e5500");
  133. break;
  134. case PVR_VER_E6500:
  135. puts("e6500");
  136. break;
  137. default:
  138. puts("Unknown");
  139. break;
  140. }
  141. printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  142. if (nr_cores > CONFIG_MAX_CPUS) {
  143. panic("\nUnexpected number of cores: %d, max is %d\n",
  144. nr_cores, CONFIG_MAX_CPUS);
  145. }
  146. get_sys_info(&sysinfo);
  147. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  148. if (sysinfo.diff_sysclk == 1)
  149. puts("Single Source Clock Configuration\n");
  150. #endif
  151. puts("Clock Configuration:");
  152. for_each_cpu(i, core, nr_cores, mask) {
  153. if (!(i & 3))
  154. printf ("\n ");
  155. printf("CPU%d:%-4s MHz, ", core,
  156. strmhz(buf1, sysinfo.freq_processor[core]));
  157. }
  158. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  159. for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
  160. if (!(j & 3))
  161. printf("\n ");
  162. printf("DSP CPU%d:%-4s MHz, ", j,
  163. strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
  164. }
  165. #endif
  166. printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
  167. printf("\n");
  168. #ifdef CONFIG_FSL_CORENET
  169. if (ddr_sync == 1) {
  170. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  171. "(Synchronous), ",
  172. strmhz(buf1, sysinfo.freq_ddrbus/2),
  173. strmhz(buf2, sysinfo.freq_ddrbus));
  174. } else {
  175. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  176. "(Asynchronous), ",
  177. strmhz(buf1, sysinfo.freq_ddrbus/2),
  178. strmhz(buf2, sysinfo.freq_ddrbus));
  179. }
  180. #else
  181. switch (ddr_ratio) {
  182. case 0x0:
  183. printf(" DDR:%-4s MHz (%s MT/s data rate), ",
  184. strmhz(buf1, sysinfo.freq_ddrbus/2),
  185. strmhz(buf2, sysinfo.freq_ddrbus));
  186. break;
  187. case 0x7:
  188. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  189. "(Synchronous), ",
  190. strmhz(buf1, sysinfo.freq_ddrbus/2),
  191. strmhz(buf2, sysinfo.freq_ddrbus));
  192. break;
  193. default:
  194. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  195. "(Asynchronous), ",
  196. strmhz(buf1, sysinfo.freq_ddrbus/2),
  197. strmhz(buf2, sysinfo.freq_ddrbus));
  198. break;
  199. }
  200. #endif
  201. #if defined(CONFIG_FSL_LBC)
  202. if (sysinfo.freq_localbus > LCRR_CLKDIV) {
  203. printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  204. } else {
  205. printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  206. sysinfo.freq_localbus);
  207. }
  208. #endif
  209. #if defined(CONFIG_FSL_IFC)
  210. printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  211. #endif
  212. #ifdef CONFIG_CPM2
  213. printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
  214. #endif
  215. #ifdef CONFIG_QE
  216. printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
  217. #endif
  218. #if defined(CONFIG_SYS_CPRI)
  219. printf(" ");
  220. printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
  221. #endif
  222. #if defined(CONFIG_SYS_MAPLE)
  223. printf("\n ");
  224. printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
  225. printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
  226. printf("MAPLE-eTVPE:%-4s MHz\n",
  227. strmhz(buf1, sysinfo.freq_maple_etvpe));
  228. #endif
  229. #ifdef CONFIG_SYS_DPAA_FMAN
  230. for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
  231. printf(" FMAN%d: %s MHz\n", i + 1,
  232. strmhz(buf1, sysinfo.freq_fman[i]));
  233. }
  234. #endif
  235. #ifdef CONFIG_SYS_DPAA_QBMAN
  236. printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
  237. #endif
  238. #ifdef CONFIG_SYS_DPAA_PME
  239. printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
  240. #endif
  241. puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
  242. #ifdef CONFIG_FSL_CORENET
  243. /* Display the RCW, so that no one gets confused as to what RCW
  244. * we're actually using for this boot.
  245. */
  246. puts("Reset Configuration Word (RCW):");
  247. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  248. u32 rcw = in_be32(&gur->rcwsr[i]);
  249. if ((i % 4) == 0)
  250. printf("\n %08x:", i * 4);
  251. printf(" %08x", rcw);
  252. }
  253. puts("\n");
  254. #endif
  255. return 0;
  256. }
  257. /* ------------------------------------------------------------------------- */
  258. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  259. {
  260. /* Everything after the first generation of PQ3 parts has RSTCR */
  261. #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
  262. defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
  263. unsigned long val, msr;
  264. /*
  265. * Initiate hard reset in debug control register DBCR0
  266. * Make sure MSR[DE] = 1. This only resets the core.
  267. */
  268. msr = mfmsr ();
  269. msr |= MSR_DE;
  270. mtmsr (msr);
  271. val = mfspr(DBCR0);
  272. val |= 0x70000000;
  273. mtspr(DBCR0,val);
  274. #else
  275. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  276. /* Attempt board-specific reset */
  277. board_reset();
  278. /* Next try asserting HRESET_REQ */
  279. out_be32(&gur->rstcr, 0x2);
  280. udelay(100);
  281. #endif
  282. return 1;
  283. }
  284. /*
  285. * Get timebase clock frequency
  286. */
  287. #ifndef CONFIG_SYS_FSL_TBCLK_DIV
  288. #define CONFIG_SYS_FSL_TBCLK_DIV 8
  289. #endif
  290. __weak unsigned long get_tbclk(void)
  291. {
  292. unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
  293. return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
  294. }
  295. #if defined(CONFIG_WATCHDOG)
  296. #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
  297. void
  298. init_85xx_watchdog(void)
  299. {
  300. mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
  301. TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
  302. }
  303. void
  304. reset_85xx_watchdog(void)
  305. {
  306. /*
  307. * Clear TSR(WIS) bit by writing 1
  308. */
  309. mtspr(SPRN_TSR, TSR_WIS);
  310. }
  311. void
  312. watchdog_reset(void)
  313. {
  314. int re_enable = disable_interrupts();
  315. reset_85xx_watchdog();
  316. if (re_enable)
  317. enable_interrupts();
  318. }
  319. #endif /* CONFIG_WATCHDOG */
  320. /*
  321. * Initializes on-chip MMC controllers.
  322. * to override, implement board_mmc_init()
  323. */
  324. int cpu_mmc_init(struct bd_info *bis)
  325. {
  326. #ifdef CONFIG_FSL_ESDHC
  327. return fsl_esdhc_mmc_init(bis);
  328. #else
  329. return 0;
  330. #endif
  331. }
  332. /*
  333. * Print out the state of various machine registers.
  334. * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
  335. * parameters for IFC and TLBs
  336. */
  337. void print_reginfo(void)
  338. {
  339. print_tlbcam();
  340. #ifdef CONFIG_FSL_LAW
  341. print_laws();
  342. #endif
  343. #if defined(CONFIG_FSL_LBC)
  344. print_lbc_regs();
  345. #endif
  346. #ifdef CONFIG_FSL_IFC
  347. print_ifc_regs();
  348. #endif
  349. }
  350. /* Common ddr init for non-corenet fsl 85xx platforms */
  351. #ifndef CONFIG_FSL_CORENET
  352. #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
  353. !defined(CONFIG_SYS_INIT_L2_ADDR)
  354. int dram_init(void)
  355. {
  356. #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
  357. defined(CONFIG_ARCH_QEMU_E500)
  358. gd->ram_size = fsl_ddr_sdram_size();
  359. #else
  360. gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  361. #endif
  362. return 0;
  363. }
  364. #else /* CONFIG_SYS_RAMBOOT */
  365. int dram_init(void)
  366. {
  367. phys_size_t dram_size = 0;
  368. #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
  369. {
  370. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  371. unsigned int x = 10;
  372. unsigned int i;
  373. /*
  374. * Work around to stabilize DDR DLL
  375. */
  376. out_be32(&gur->ddrdllcr, 0x81000000);
  377. asm("sync;isync;msync");
  378. udelay(200);
  379. while (in_be32(&gur->ddrdllcr) != 0x81000100) {
  380. setbits_be32(&gur->devdisr, 0x00010000);
  381. for (i = 0; i < x; i++)
  382. ;
  383. clrbits_be32(&gur->devdisr, 0x00010000);
  384. x++;
  385. }
  386. }
  387. #endif
  388. #if defined(CONFIG_SPD_EEPROM) || \
  389. defined(CONFIG_DDR_SPD) || \
  390. defined(CONFIG_SYS_DDR_RAW_TIMING)
  391. dram_size = fsl_ddr_sdram();
  392. #else
  393. dram_size = fixed_sdram();
  394. #endif
  395. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  396. dram_size *= 0x100000;
  397. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  398. /*
  399. * Initialize and enable DDR ECC.
  400. */
  401. ddr_enable_ecc(dram_size);
  402. #endif
  403. #if defined(CONFIG_FSL_LBC)
  404. /* Some boards also have sdram on the lbc */
  405. lbc_sdram_init();
  406. #endif
  407. debug("DDR: ");
  408. gd->ram_size = dram_size;
  409. return 0;
  410. }
  411. #endif /* CONFIG_SYS_RAMBOOT */
  412. #endif
  413. #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
  414. /* Board-specific functions defined in each board's ddr.c */
  415. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  416. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
  417. void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
  418. phys_addr_t *rpn);
  419. unsigned int
  420. setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  421. void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  422. static void dump_spd_ddr_reg(void)
  423. {
  424. int i, j, k, m;
  425. u8 *p_8;
  426. u32 *p_32;
  427. struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
  428. generic_spd_eeprom_t
  429. spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
  430. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
  431. fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
  432. puts("SPD data of all dimms (zero value is omitted)...\n");
  433. puts("Byte (hex) ");
  434. k = 1;
  435. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  436. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
  437. printf("Dimm%d ", k++);
  438. }
  439. puts("\n");
  440. for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
  441. m = 0;
  442. printf("%3d (0x%02x) ", k, k);
  443. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  444. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  445. p_8 = (u8 *) &spd[i][j];
  446. if (p_8[k]) {
  447. printf("0x%02x ", p_8[k]);
  448. m++;
  449. } else
  450. puts(" ");
  451. }
  452. }
  453. if (m)
  454. puts("\n");
  455. else
  456. puts("\r");
  457. }
  458. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  459. switch (i) {
  460. case 0:
  461. ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  462. break;
  463. #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  464. case 1:
  465. ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  466. break;
  467. #endif
  468. #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  469. case 2:
  470. ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  471. break;
  472. #endif
  473. #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  474. case 3:
  475. ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  476. break;
  477. #endif
  478. default:
  479. printf("%s unexpected controller number = %u\n",
  480. __func__, i);
  481. return;
  482. }
  483. }
  484. printf("DDR registers dump for all controllers "
  485. "(zero value is omitted)...\n");
  486. puts("Offset (hex) ");
  487. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
  488. printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
  489. puts("\n");
  490. for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
  491. m = 0;
  492. printf("%6d (0x%04x)", k * 4, k * 4);
  493. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  494. p_32 = (u32 *) ddr[i];
  495. if (p_32[k]) {
  496. printf(" 0x%08x", p_32[k]);
  497. m++;
  498. } else
  499. puts(" ");
  500. }
  501. if (m)
  502. puts("\n");
  503. else
  504. puts("\r");
  505. }
  506. puts("\n");
  507. }
  508. /* invalid the TLBs for DDR and setup new ones to cover p_addr */
  509. static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
  510. {
  511. u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  512. unsigned long epn;
  513. u32 tsize, valid, ptr;
  514. int ddr_esel;
  515. clear_ddr_tlbs_phys(p_addr, size>>20);
  516. /* Setup new tlb to cover the physical address */
  517. setup_ddr_tlbs_phys(p_addr, size>>20);
  518. ptr = vstart;
  519. ddr_esel = find_tlb_idx((void *)ptr, 1);
  520. if (ddr_esel != -1) {
  521. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
  522. } else {
  523. printf("TLB error in function %s\n", __func__);
  524. return -1;
  525. }
  526. return 0;
  527. }
  528. /*
  529. * slide the testing window up to test another area
  530. * for 32_bit system, the maximum testable memory is limited to
  531. * CONFIG_MAX_MEM_MAPPED
  532. */
  533. int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  534. {
  535. phys_addr_t test_cap, p_addr;
  536. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  537. #if !defined(CONFIG_PHYS_64BIT) || \
  538. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  539. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  540. test_cap = p_size;
  541. #else
  542. test_cap = gd->ram_size;
  543. #endif
  544. p_addr = (*vstart) + (*size) + (*phys_offset);
  545. if (p_addr < test_cap - 1) {
  546. p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
  547. if (reset_tlb(p_addr, p_size, phys_offset) == -1)
  548. return -1;
  549. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  550. *size = (u32) p_size;
  551. printf("Testing 0x%08llx - 0x%08llx\n",
  552. (u64)(*vstart) + (*phys_offset),
  553. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  554. } else
  555. return 1;
  556. return 0;
  557. }
  558. /* initialization for testing area */
  559. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  560. {
  561. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  562. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  563. *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
  564. *phys_offset = 0;
  565. #if !defined(CONFIG_PHYS_64BIT) || \
  566. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  567. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  568. if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
  569. puts("Cannot test more than ");
  570. print_size(CONFIG_MAX_MEM_MAPPED,
  571. " without proper 36BIT support.\n");
  572. }
  573. #endif
  574. printf("Testing 0x%08llx - 0x%08llx\n",
  575. (u64)(*vstart) + (*phys_offset),
  576. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  577. return 0;
  578. }
  579. /* invalid TLBs for DDR and remap as normal after testing */
  580. int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  581. {
  582. unsigned long epn;
  583. u32 tsize, valid, ptr;
  584. phys_addr_t rpn = 0;
  585. int ddr_esel;
  586. /* disable the TLBs for this testing */
  587. ptr = *vstart;
  588. while (ptr < (*vstart) + (*size)) {
  589. ddr_esel = find_tlb_idx((void *)ptr, 1);
  590. if (ddr_esel != -1) {
  591. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
  592. disable_tlb(ddr_esel);
  593. }
  594. ptr += TSIZE_TO_BYTES(tsize);
  595. }
  596. puts("Remap DDR ");
  597. setup_ddr_tlbs(gd->ram_size>>20);
  598. puts("\n");
  599. return 0;
  600. }
  601. void arch_memory_failure_handle(void)
  602. {
  603. dump_spd_ddr_reg();
  604. }
  605. #endif