system_manager.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
  4. */
  5. #ifndef _SYSTEM_MANAGER_H_
  6. #define _SYSTEM_MANAGER_H_
  7. phys_addr_t socfpga_get_sysmgr_addr(void);
  8. #if defined(CONFIG_TARGET_SOCFPGA_SOC64)
  9. #include <asm/arch/system_manager_soc64.h>
  10. #else
  11. #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
  12. #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
  13. #define SYSMGR_ECC_OCRAM_EN BIT(0)
  14. #define SYSMGR_ECC_OCRAM_SERR BIT(3)
  15. #define SYSMGR_ECC_OCRAM_DERR BIT(4)
  16. #define SYSMGR_FPGAINTF_USEFPGA 0x1
  17. #define SYSMGR_FPGAINTF_SPIM0 BIT(0)
  18. #define SYSMGR_FPGAINTF_SPIM1 BIT(1)
  19. #define SYSMGR_FPGAINTF_EMAC0 BIT(2)
  20. #define SYSMGR_FPGAINTF_EMAC1 BIT(3)
  21. #define SYSMGR_FPGAINTF_NAND BIT(4)
  22. #define SYSMGR_FPGAINTF_SDMMC BIT(5)
  23. #define SYSMGR_SDMMC_DRVSEL_SHIFT 0
  24. /* EMAC Group Bit definitions */
  25. #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
  26. #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
  27. #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
  28. #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
  29. #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
  30. #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
  31. /* For dedicated IO configuration */
  32. /* Voltage select enums */
  33. #define VOLTAGE_SEL_3V 0x0
  34. #define VOLTAGE_SEL_1P8V 0x1
  35. #define VOLTAGE_SEL_2P5V 0x2
  36. /* Input buffer enable */
  37. #define INPUT_BUF_DISABLE 0
  38. #define INPUT_BUF_1P8V 1
  39. #define INPUT_BUF_2P5V3V 2
  40. /* Weak pull up enable */
  41. #define WK_PU_DISABLE 0
  42. #define WK_PU_ENABLE 1
  43. /* Pull up slew rate control */
  44. #define PU_SLW_RT_SLOW 0
  45. #define PU_SLW_RT_FAST 1
  46. #define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW
  47. /* Pull down slew rate control */
  48. #define PD_SLW_RT_SLOW 0
  49. #define PD_SLW_RT_FAST 1
  50. #define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW
  51. /* Drive strength control */
  52. #define PU_DRV_STRG_DEFAULT 0x10
  53. #define PD_DRV_STRG_DEFAULT 0x10
  54. /* bit position */
  55. #define PD_DRV_STRG_LSB 0
  56. #define PD_SLW_RT_LSB 5
  57. #define PU_DRV_STRG_LSB 8
  58. #define PU_SLW_RT_LSB 13
  59. #define WK_PU_LSB 16
  60. #define INPUT_BUF_LSB 17
  61. #define BIAS_TRIM_LSB 19
  62. #define VOLTAGE_SEL_LSB 0
  63. #define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0)
  64. #define ALT_SYSMGR_NOC_LWH2F_SET_MSK BIT(4)
  65. #define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8)
  66. #define ALT_SYSMGR_NOC_F2SDR0_SET_MSK BIT(16)
  67. #define ALT_SYSMGR_NOC_F2SDR1_SET_MSK BIT(20)
  68. #define ALT_SYSMGR_NOC_F2SDR2_SET_MSK BIT(24)
  69. #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK BIT(0)
  70. #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1)
  71. #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1)
  72. #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  73. #include <asm/arch/system_manager_gen5.h>
  74. #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  75. #include <asm/arch/system_manager_arria10.h>
  76. #endif
  77. #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
  78. (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
  79. #include <linux/bitops.h>
  80. #endif
  81. #endif /* _SYSTEM_MANAGER_H_ */