mailbox_s10.h 6.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187
  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #ifndef _MAILBOX_S10_H_
  7. #define _MAILBOX_S10_H_
  8. /* user define Uboot ID */
  9. #include <linux/bitops.h>
  10. #define MBOX_CLIENT_ID_UBOOT 0xB
  11. #define MBOX_ID_UBOOT 0x1
  12. #define MBOX_CMD_DIRECT 0
  13. #define MBOX_CMD_INDIRECT 1
  14. #define MBOX_MAX_CMD_INDEX 2047
  15. #define MBOX_CMD_BUFFER_SIZE 32
  16. #define MBOX_RESP_BUFFER_SIZE 16
  17. #define MBOX_HDR_CMD_LSB 0
  18. #define MBOX_HDR_CMD_MSK (BIT(11) - 1)
  19. #define MBOX_HDR_I_LSB 11
  20. #define MBOX_HDR_I_MSK BIT(11)
  21. #define MBOX_HDR_LEN_LSB 12
  22. #define MBOX_HDR_LEN_MSK 0x007FF000
  23. #define MBOX_HDR_ID_LSB 24
  24. #define MBOX_HDR_ID_MSK 0x0F000000
  25. #define MBOX_HDR_CLIENT_LSB 28
  26. #define MBOX_HDR_CLIENT_MSK 0xF0000000
  27. /* Interrupt flags */
  28. #define MBOX_FLAGS_INT_COE BIT(0) /* COUT update interrupt enable */
  29. #define MBOX_FLAGS_INT_RIE BIT(1) /* RIN update interrupt enable */
  30. #define MBOX_FLAGS_INT_UAE BIT(8) /* Urgent ACK interrupt enable */
  31. #define MBOX_ALL_INTRS (MBOX_FLAGS_INT_COE | \
  32. MBOX_FLAGS_INT_RIE | \
  33. MBOX_FLAGS_INT_UAE)
  34. /* Status */
  35. #define MBOX_STATUS_UA_MSK BIT(8)
  36. #define MBOX_CMD_HEADER(client, id, len, indirect, cmd) \
  37. ((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
  38. (((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
  39. (((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
  40. (((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK) | \
  41. (((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
  42. #define MBOX_RESP_ERR_GET(resp) \
  43. (((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
  44. #define MBOX_RESP_LEN_GET(resp) \
  45. (((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
  46. #define MBOX_RESP_ID_GET(resp) \
  47. (((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
  48. #define MBOX_RESP_CLIENT_GET(resp) \
  49. (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
  50. /* Response error list */
  51. enum ALT_SDM_MBOX_RESP_CODE {
  52. /* CMD completed successfully, but check resp ARGS for any errors */
  53. MBOX_RESP_STATOK = 0,
  54. /* CMD is incorrectly formatted in some way */
  55. MBOX_RESP_INVALID_COMMAND = 1,
  56. /* BootROM Command code not undesrtood */
  57. MBOX_RESP_UNKNOWN_BR = 2,
  58. /* CMD code not recognized by firmware */
  59. MBOX_RESP_UNKNOWN = 3,
  60. /* Length setting is not a valid length for this CMD type */
  61. MBOX_RESP_INVALID_LEN = 4,
  62. /* Indirect setting is not valid for this CMD type */
  63. MBOX_RESP_INVALID_INDIRECT_SETTING = 5,
  64. /* HW source which is not allowed to send CMD type */
  65. MBOX_RESP_CMD_INVALID_ON_SRC = 6,
  66. /* Client with ID not associated with any running PR CMD tries to run
  67. * RECONFIG_DATA RECONFIG_STATUS and accessing QSPI / SDMMC using ID
  68. * without exclusive access
  69. */
  70. MBOX_RESP_CLIENT_ID_NO_MATCH = 8,
  71. /* Address provided to the system is invalid (alignment, range
  72. * permission)
  73. */
  74. MBOX_RESP_INVALID_ADDR = 0x9,
  75. /* Signature authentication failed */
  76. MBOX_RESP_AUTH_FAIL = 0xA,
  77. /* CMD timed out */
  78. MBOX_RESP_TIMEOUT = 0xB,
  79. /* HW (i.e. QSPI) is not ready (initialized or configured) */
  80. MBOX_RESP_HW_NOT_RDY = 0xC,
  81. /* Invalid license for IID registration */
  82. MBOX_RESP_PUF_ACCCES_FAILED = 0x80,
  83. MBOX_PUF_ENROLL_DISABLE = 0x81,
  84. MBOX_RESP_PUF_ENROLL_FAIL = 0x82,
  85. MBOX_RESP_PUF_RAM_TEST_FAIL = 0x83,
  86. MBOX_RESP_ATTEST_CERT_GEN_FAIL = 0x84,
  87. /* Operation not allowed under current security settings */
  88. MBOX_RESP_NOT_ALLOWED_UNDER_SECURITY_SETTINGS = 0x85,
  89. MBOX_RESP_PUF_TRNG_FAIL = 0x86,
  90. MBOX_RESP_FUSE_ALREADY_BLOWN = 0x87,
  91. MBOX_RESP_INVALID_SIGNATURE = 0x88,
  92. MBOX_RESP_INVALID_HASH = 0x8b,
  93. MBOX_RESP_INVALID_CERTIFICATE = 0x91,
  94. /* Indicates that the device (FPGA or HPS) is not configured */
  95. MBOX_RESP_NOT_CONFIGURED = 0x100,
  96. /* Indicates that the device is busy */
  97. MBOX_RESP_DEVICE_BUSY = 0x1FF,
  98. /* Indicates that there is no valid response available */
  99. MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
  100. /* General Error */
  101. MBOX_RESP_ERROR = 0x3FF,
  102. };
  103. /* Mailbox command list */
  104. #define MBOX_RESTART 2
  105. #define MBOX_CONFIG_STATUS 4
  106. #define MBOX_RECONFIG 6
  107. #define MBOX_RECONFIG_MSEL 7
  108. #define MBOX_RECONFIG_DATA 8
  109. #define MBOX_RECONFIG_STATUS 9
  110. #define MBOX_VAB_SRC_CERT 11
  111. #define MBOX_QSPI_OPEN 50
  112. #define MBOX_QSPI_CLOSE 51
  113. #define MBOX_QSPI_DIRECT 59
  114. #define MBOX_REBOOT_HPS 71
  115. /* Mailbox registers */
  116. #define MBOX_CIN 0 /* command valid offset */
  117. #define MBOX_ROUT 4 /* response output offset */
  118. #define MBOX_URG 8 /* urgent command */
  119. #define MBOX_FLAGS 0x0c /* interrupt enables */
  120. #define MBOX_COUT 0x20 /* command free offset */
  121. #define MBOX_RIN 0x24 /* respond valid offset */
  122. #define MBOX_STATUS 0x2c /* mailbox status */
  123. #define MBOX_CMD_BUF 0x40 /* circular command buffer */
  124. #define MBOX_RESP_BUF 0xc0 /* circular response buffer */
  125. #define MBOX_DOORBELL_TO_SDM 0x400 /* Doorbell to SDM */
  126. #define MBOX_DOORBELL_FROM_SDM 0x480 /* Doorbell from SDM */
  127. /* Status and bit information returned by RECONFIG_STATUS */
  128. #define RECONFIG_STATUS_RESPONSE_LEN 6
  129. #define RECONFIG_STATUS_STATE 0
  130. #define RECONFIG_STATUS_PIN_STATUS 2
  131. #define RECONFIG_STATUS_SOFTFUNC_STATUS 3
  132. /* Macros for specifying number of arguments in mailbox command */
  133. #define MBOX_NUM_ARGS(n, b) (((n) & 0xFF) << (b))
  134. #define MBOX_DIRECT_COUNT(n) MBOX_NUM_ARGS((n), 0)
  135. #define MBOX_ARG_DESC_COUNT(n) MBOX_NUM_ARGS((n), 8)
  136. #define MBOX_RESP_DESC_COUNT(n) MBOX_NUM_ARGS((n), 16)
  137. #define MBOX_CFGSTAT_STATE_IDLE 0x00000000
  138. #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
  139. #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
  140. #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
  141. #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
  142. #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003
  143. #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004
  144. #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005
  145. #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006
  146. #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
  147. #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
  148. #define RCF_SOFTFUNC_STATUS_CONF_DONE BIT(0)
  149. #define RCF_SOFTFUNC_STATUS_INIT_DONE BIT(1)
  150. #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3)
  151. #define RCF_PIN_STATUS_NSTATUS BIT(31)
  152. int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
  153. u32 *resp_buf_len, u32 *resp_buf);
  154. int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
  155. u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
  156. int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
  157. int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
  158. int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
  159. int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
  160. int mbox_init(void);
  161. #ifdef CONFIG_CADENCE_QSPI
  162. int mbox_qspi_close(void);
  163. int mbox_qspi_open(void);
  164. #endif
  165. int mbox_reset_cold(void);
  166. int mbox_get_fpga_config_status(u32 cmd);
  167. int mbox_get_fpga_config_status_psci(u32 cmd);
  168. #endif /* _MAILBOX_S10_H_ */