Kconfig 6.6 KB

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  1. if ARCH_SOCFPGA
  2. config ERR_PTR_OFFSET
  3. default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
  4. config NR_DRAM_BANKS
  5. default 1
  6. config SOCFPGA_SECURE_VAB_AUTH
  7. bool "Enable boot image authentication with Secure Device Manager"
  8. depends on TARGET_SOCFPGA_AGILEX
  9. select FIT_IMAGE_POST_PROCESS
  10. select SHA384
  11. select SHA512_ALGO
  12. select SPL_FIT_IMAGE_POST_PROCESS
  13. help
  14. All images loaded from FIT will be authenticated by Secure Device
  15. Manager.
  16. config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
  17. bool "Allow non-FIT VAB signed images"
  18. depends on SOCFPGA_SECURE_VAB_AUTH
  19. config SPL_SIZE_LIMIT
  20. default 0x10000 if TARGET_SOCFPGA_GEN5
  21. config SPL_SIZE_LIMIT_PROVIDE_STACK
  22. default 0x200 if TARGET_SOCFPGA_GEN5
  23. config SPL_STACK_R_ADDR
  24. default 0x00800000 if TARGET_SOCFPGA_GEN5
  25. config SPL_SYS_MALLOC_F_LEN
  26. default 0x800 if TARGET_SOCFPGA_GEN5
  27. config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  28. default 0xa2
  29. config SYS_MALLOC_F_LEN
  30. default 0x2000 if TARGET_SOCFPGA_ARRIA10
  31. default 0x2000 if TARGET_SOCFPGA_GEN5
  32. config SYS_TEXT_BASE
  33. default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  34. default 0x01000040 if TARGET_SOCFPGA_GEN5
  35. config TARGET_SOCFPGA_AGILEX
  36. bool
  37. select ARMV8_MULTIENTRY
  38. select ARMV8_SET_SMPEN
  39. select BINMAN if SPL_ATF
  40. select CLK
  41. select FPGA_INTEL_SDM_MAILBOX
  42. select NCORE_CACHE
  43. select SPL_CLK if SPL
  44. select TARGET_SOCFPGA_SOC64
  45. config TARGET_SOCFPGA_ARRIA5
  46. bool
  47. select TARGET_SOCFPGA_GEN5
  48. config TARGET_SOCFPGA_ARRIA10
  49. bool
  50. select SPL_ALTERA_SDRAM
  51. select SPL_BOARD_INIT if SPL
  52. select SPL_CACHE if SPL
  53. select CLK
  54. select SPL_CLK if SPL
  55. select DM_I2C
  56. select DM_RESET
  57. select SPL_DM_RESET if SPL
  58. select REGMAP
  59. select SPL_REGMAP if SPL
  60. select SYSCON
  61. select SPL_SYSCON if SPL
  62. select ETH_DESIGNWARE_SOCFPGA
  63. imply FPGA_SOCFPGA
  64. imply SPL_USE_TINY_PRINTF
  65. config TARGET_SOCFPGA_CYCLONE5
  66. bool
  67. select TARGET_SOCFPGA_GEN5
  68. config TARGET_SOCFPGA_GEN5
  69. bool
  70. select SPL_ALTERA_SDRAM
  71. imply FPGA_SOCFPGA
  72. imply SPL_SIZE_LIMIT_SUBTRACT_GD
  73. imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
  74. imply SPL_STACK_R
  75. imply SPL_SYS_MALLOC_SIMPLE
  76. imply SPL_USE_TINY_PRINTF
  77. config TARGET_SOCFPGA_SOC64
  78. bool
  79. config TARGET_SOCFPGA_STRATIX10
  80. bool
  81. select ARMV8_MULTIENTRY
  82. select ARMV8_SET_SMPEN
  83. select BINMAN if SPL_ATF
  84. select FPGA_INTEL_SDM_MAILBOX
  85. select TARGET_SOCFPGA_SOC64
  86. choice
  87. prompt "Altera SOCFPGA board select"
  88. optional
  89. config TARGET_SOCFPGA_AGILEX_SOCDK
  90. bool "Intel SOCFPGA SoCDK (Agilex)"
  91. select TARGET_SOCFPGA_AGILEX
  92. config TARGET_SOCFPGA_ARIES_MCVEVK
  93. bool "Aries MCVEVK (Cyclone V)"
  94. select TARGET_SOCFPGA_CYCLONE5
  95. config TARGET_SOCFPGA_ARRIA10_SOCDK
  96. bool "Altera SOCFPGA SoCDK (Arria 10)"
  97. select TARGET_SOCFPGA_ARRIA10
  98. config TARGET_SOCFPGA_ARRIA5_SECU1
  99. bool "ABB SECU1 (Arria V)"
  100. select TARGET_SOCFPGA_ARRIA5
  101. select VENDOR_KM
  102. config TARGET_SOCFPGA_ARRIA5_SOCDK
  103. bool "Altera SOCFPGA SoCDK (Arria V)"
  104. select TARGET_SOCFPGA_ARRIA5
  105. config TARGET_SOCFPGA_CYCLONE5_SOCDK
  106. bool "Altera SOCFPGA SoCDK (Cyclone V)"
  107. select TARGET_SOCFPGA_CYCLONE5
  108. config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  109. bool "Devboards DBM-SoC1 (Cyclone V)"
  110. select TARGET_SOCFPGA_CYCLONE5
  111. config TARGET_SOCFPGA_EBV_SOCRATES
  112. bool "EBV SoCrates (Cyclone V)"
  113. select TARGET_SOCFPGA_CYCLONE5
  114. config TARGET_SOCFPGA_IS1
  115. bool "IS1 (Cyclone V)"
  116. select TARGET_SOCFPGA_CYCLONE5
  117. config TARGET_SOCFPGA_SOFTING_VINING_FPGA
  118. bool "Softing VIN|ING FPGA (Cyclone V)"
  119. select BOARD_LATE_INIT
  120. select TARGET_SOCFPGA_CYCLONE5
  121. config TARGET_SOCFPGA_SR1500
  122. bool "SR1500 (Cyclone V)"
  123. select TARGET_SOCFPGA_CYCLONE5
  124. config TARGET_SOCFPGA_STRATIX10_SOCDK
  125. bool "Intel SOCFPGA SoCDK (Stratix 10)"
  126. select TARGET_SOCFPGA_STRATIX10
  127. config TARGET_SOCFPGA_TERASIC_DE0_NANO
  128. bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  129. select TARGET_SOCFPGA_CYCLONE5
  130. config TARGET_SOCFPGA_TERASIC_DE10_NANO
  131. bool "Terasic DE10-Nano (Cyclone V)"
  132. select TARGET_SOCFPGA_CYCLONE5
  133. config TARGET_SOCFPGA_TERASIC_DE1_SOC
  134. bool "Terasic DE1-SoC (Cyclone V)"
  135. select TARGET_SOCFPGA_CYCLONE5
  136. config TARGET_SOCFPGA_TERASIC_SOCKIT
  137. bool "Terasic SoCkit (Cyclone V)"
  138. select TARGET_SOCFPGA_CYCLONE5
  139. endchoice
  140. config SYS_BOARD
  141. default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
  142. default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  143. default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  144. default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  145. default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  146. default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  147. default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  148. default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  149. default "is1" if TARGET_SOCFPGA_IS1
  150. default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
  151. default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
  152. default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  153. default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  154. default "sr1500" if TARGET_SOCFPGA_SR1500
  155. default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  156. default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  157. config SYS_VENDOR
  158. default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
  159. default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
  160. default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
  161. default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  162. default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
  163. default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
  164. default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  165. default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
  166. default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
  167. default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  168. default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  169. default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  170. default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  171. default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
  172. config SYS_SOC
  173. default "socfpga"
  174. config SYS_CONFIG_NAME
  175. default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
  176. default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
  177. default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  178. default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  179. default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  180. default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  181. default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  182. default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  183. default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  184. default "socfpga_is1" if TARGET_SOCFPGA_IS1
  185. default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
  186. default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  187. default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  188. default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
  189. default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  190. default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  191. source "board/keymile/Kconfig"
  192. endif