lowlevel_init.S 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Board specific setup info
  4. *
  5. * (C) Copyright 2008
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Initial Code by:
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Syed Mohammed Khasim <khasim@ti.com>
  11. */
  12. #include <config.h>
  13. #include <asm/arch/mem.h>
  14. #include <asm/arch/clocks_omap3.h>
  15. #include <linux/linkage.h>
  16. /*
  17. * Funtion for making PPA HAL API calls in secure devices
  18. * Input:
  19. * R0 - Service ID
  20. * R1 - paramer list
  21. */
  22. /* TODO: Re-evaluate the comment at the end regarding armv5 vs armv7 */
  23. ENTRY(do_omap3_emu_romcode_call)
  24. PUSH {r4-r12, lr} @ Save all registers from ROM code!
  25. MOV r12, r0 @ Copy the Secure Service ID in R12
  26. MOV r3, r1 @ Copy the pointer to va_list in R3
  27. MOV r1, #0 @ Process ID - 0
  28. MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
  29. @ to va_list in R3
  30. MOV r6, #0xFF @ Indicate new Task call
  31. mcr p15, 0, r0, c7, c10, 4 @ DSB
  32. mcr p15, 0, r0, c7, c10, 5 @ DMB
  33. .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
  34. @ because we use -march=armv5
  35. POP {r4-r12, pc}
  36. ENDPROC(do_omap3_emu_romcode_call)
  37. #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
  38. /**************************************************************************
  39. * cpy_clk_code: relocates clock code into SRAM where its safer to execute
  40. * R1 = SRAM destination address.
  41. *************************************************************************/
  42. ENTRY(cpy_clk_code)
  43. /* Copy DPLL code into SRAM */
  44. adr r0, go_to_speed /* copy from start of go_to_speed... */
  45. adr r2, go_to_speed_end /* ... up to start of go_to_speed_end */
  46. next2:
  47. ldmia r0!, {r3 - r10} /* copy from source address [r0] */
  48. stmia r1!, {r3 - r10} /* copy to target address [r1] */
  49. cmp r0, r2 /* until source end address [r2] */
  50. blo next2
  51. mov pc, lr /* back to caller */
  52. ENDPROC(cpy_clk_code)
  53. /* ***************************************************************************
  54. * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
  55. * -executed from SRAM.
  56. * R0 = CM_CLKEN_PLL-bypass value
  57. * R1 = CM_CLKSEL1_PLL-m, n, and divider values
  58. * R2 = CM_CLKSEL_CORE-divider values
  59. * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
  60. *
  61. * Note: If core unlocks/relocks and SDRAM is running fast already it gets
  62. * confused. A reset of the controller gets it back. Taking away its
  63. * L3 when its not in self refresh seems bad for it. Normally, this
  64. * code runs from flash before SDR is init so that should be ok.
  65. ****************************************************************************/
  66. ENTRY(go_to_speed)
  67. stmfd sp!, {r4 - r6}
  68. /* move into fast relock bypass */
  69. ldr r4, pll_ctl_add
  70. str r0, [r4]
  71. wait1:
  72. ldr r5, [r3] /* get status */
  73. and r5, r5, #0x1 /* isolate core status */
  74. cmp r5, #0x1 /* still locked? */
  75. beq wait1 /* if lock, loop */
  76. /* set new dpll dividers _after_ in bypass */
  77. ldr r5, pll_div_add1
  78. str r1, [r5] /* set m, n, m2 */
  79. ldr r5, pll_div_add2
  80. str r2, [r5] /* set l3/l4/.. dividers*/
  81. ldr r5, pll_div_add3 /* wkup */
  82. ldr r2, pll_div_val3 /* rsm val */
  83. str r2, [r5]
  84. ldr r5, pll_div_add4 /* gfx */
  85. ldr r2, pll_div_val4
  86. str r2, [r5]
  87. ldr r5, pll_div_add5 /* emu */
  88. ldr r2, pll_div_val5
  89. str r2, [r5]
  90. /* now prepare GPMC (flash) for new dpll speed */
  91. /* flash needs to be stable when we jump back to it */
  92. ldr r5, flash_cfg3_addr
  93. ldr r2, flash_cfg3_val
  94. str r2, [r5]
  95. ldr r5, flash_cfg4_addr
  96. ldr r2, flash_cfg4_val
  97. str r2, [r5]
  98. ldr r5, flash_cfg5_addr
  99. ldr r2, flash_cfg5_val
  100. str r2, [r5]
  101. ldr r5, flash_cfg1_addr
  102. ldr r2, [r5]
  103. orr r2, r2, #0x3 /* up gpmc divider */
  104. str r2, [r5]
  105. /* lock DPLL3 and wait a bit */
  106. orr r0, r0, #0x7 /* set up for lock mode */
  107. str r0, [r4] /* lock */
  108. nop /* ARM slow at this point working at sys_clk */
  109. nop
  110. nop
  111. nop
  112. wait2:
  113. ldr r5, [r3] /* get status */
  114. and r5, r5, #0x1 /* isolate core status */
  115. cmp r5, #0x1 /* still locked? */
  116. bne wait2 /* if lock, loop */
  117. nop
  118. nop
  119. nop
  120. nop
  121. ldmfd sp!, {r4 - r6}
  122. mov pc, lr /* back to caller, locked */
  123. ENDPROC(go_to_speed)
  124. _go_to_speed: .word go_to_speed
  125. /* these constants need to be close for PIC code */
  126. /* The Nor has to be in the Flash Base CS0 for this condition to happen */
  127. flash_cfg1_addr:
  128. .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
  129. flash_cfg3_addr:
  130. .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
  131. flash_cfg3_val:
  132. .word STNOR_GPMC_CONFIG3
  133. flash_cfg4_addr:
  134. .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
  135. flash_cfg4_val:
  136. .word STNOR_GPMC_CONFIG4
  137. flash_cfg5_val:
  138. .word STNOR_GPMC_CONFIG5
  139. flash_cfg5_addr:
  140. .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
  141. pll_ctl_add:
  142. .word CM_CLKEN_PLL
  143. pll_div_add1:
  144. .word CM_CLKSEL1_PLL
  145. pll_div_add2:
  146. .word CM_CLKSEL_CORE
  147. pll_div_add3:
  148. .word CM_CLKSEL_WKUP
  149. pll_div_val3:
  150. .word (WKUP_RSM << 1)
  151. pll_div_add4:
  152. .word CM_CLKSEL_GFX
  153. pll_div_val4:
  154. .word (GFX_DIV << 0)
  155. pll_div_add5:
  156. .word CM_CLKSEL1_EMU
  157. pll_div_val5:
  158. .word CLSEL1_EMU_VAL
  159. go_to_speed_end:
  160. #endif
  161. #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
  162. !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
  163. ENTRY(lowlevel_init)
  164. ldr sp, SRAM_STACK
  165. str ip, [sp] /* stash ip register */
  166. mov ip, lr /* save link reg across call */
  167. #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
  168. /*
  169. * No need to copy/exec the clock code - DPLL adjust already done
  170. * in NAND/oneNAND Boot.
  171. */
  172. ldr r1, =SRAM_CLK_CODE
  173. bl cpy_clk_code
  174. #endif /* NAND Boot */
  175. mov lr, ip /* restore link reg */
  176. ldr ip, [sp] /* restore save ip */
  177. /* tail-call s_init to setup pll, mux, memory */
  178. b s_init
  179. ENDPROC(lowlevel_init)
  180. #endif
  181. /* the literal pools origin */
  182. .ltorg
  183. REG_CONTROL_STATUS:
  184. .word CONTROL_STATUS
  185. SRAM_STACK:
  186. .word LOW_LEVEL_SRAM_STACK
  187. /* DPLL(1-4) PARAM TABLES */
  188. /*
  189. * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
  190. * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
  191. * The values are defined for all possible sysclk and for ES1 and ES2.
  192. */
  193. mpu_dpll_param:
  194. /* 12MHz */
  195. /* ES1 */
  196. .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
  197. /* ES2 */
  198. .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
  199. /* 3410 */
  200. .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
  201. /* 13MHz */
  202. /* ES1 */
  203. .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
  204. /* ES2 */
  205. .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
  206. /* 3410 */
  207. .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
  208. /* 19.2MHz */
  209. /* ES1 */
  210. .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
  211. /* ES2 */
  212. .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
  213. /* 3410 */
  214. .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
  215. /* 26MHz */
  216. /* ES1 */
  217. .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
  218. /* ES2 */
  219. .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
  220. /* 3410 */
  221. .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
  222. /* 38.4MHz */
  223. /* ES1 */
  224. .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
  225. /* ES2 */
  226. .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
  227. /* 3410 */
  228. .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
  229. .globl get_mpu_dpll_param
  230. get_mpu_dpll_param:
  231. adr r0, mpu_dpll_param
  232. mov pc, lr
  233. iva_dpll_param:
  234. /* 12MHz */
  235. /* ES1 */
  236. .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
  237. /* ES2 */
  238. .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
  239. /* 3410 */
  240. .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
  241. /* 13MHz */
  242. /* ES1 */
  243. .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
  244. /* ES2 */
  245. .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
  246. /* 3410 */
  247. .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
  248. /* 19.2MHz */
  249. /* ES1 */
  250. .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
  251. /* ES2 */
  252. .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
  253. /* 3410 */
  254. .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
  255. /* 26MHz */
  256. /* ES1 */
  257. .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
  258. /* ES2 */
  259. .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
  260. /* 3410 */
  261. .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
  262. /* 38.4MHz */
  263. /* ES1 */
  264. .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
  265. /* ES2 */
  266. .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
  267. /* 3410 */
  268. .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
  269. .globl get_iva_dpll_param
  270. get_iva_dpll_param:
  271. adr r0, iva_dpll_param
  272. mov pc, lr
  273. /* Core DPLL targets for L3 at 166 & L133 */
  274. core_dpll_param:
  275. /* 12MHz */
  276. /* ES1 */
  277. .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
  278. /* ES2 */
  279. .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
  280. /* 3410 */
  281. .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
  282. /* 13MHz */
  283. /* ES1 */
  284. .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
  285. /* ES2 */
  286. .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
  287. /* 3410 */
  288. .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
  289. /* 19.2MHz */
  290. /* ES1 */
  291. .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
  292. /* ES2 */
  293. .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
  294. /* 3410 */
  295. .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
  296. /* 26MHz */
  297. /* ES1 */
  298. .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
  299. /* ES2 */
  300. .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
  301. /* 3410 */
  302. .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
  303. /* 38.4MHz */
  304. /* ES1 */
  305. .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
  306. /* ES2 */
  307. .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
  308. /* 3410 */
  309. .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
  310. .globl get_core_dpll_param
  311. get_core_dpll_param:
  312. adr r0, core_dpll_param
  313. mov pc, lr
  314. /* PER DPLL values are same for both ES1 and ES2 */
  315. per_dpll_param:
  316. /* 12MHz */
  317. .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
  318. /* 13MHz */
  319. .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
  320. /* 19.2MHz */
  321. .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
  322. /* 26MHz */
  323. .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
  324. /* 38.4MHz */
  325. .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
  326. .globl get_per_dpll_param
  327. get_per_dpll_param:
  328. adr r0, per_dpll_param
  329. mov pc, lr
  330. /* PER2 DPLL values */
  331. per2_dpll_param:
  332. /* 12MHz */
  333. .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
  334. /* 13MHz */
  335. .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
  336. /* 19.2MHz */
  337. .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
  338. /* 26MHz */
  339. .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
  340. /* 38.4MHz */
  341. .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
  342. .globl get_per2_dpll_param
  343. get_per2_dpll_param:
  344. adr r0, per2_dpll_param
  345. mov pc, lr
  346. /*
  347. * Tables for 36XX/37XX devices
  348. *
  349. */
  350. mpu_36x_dpll_param:
  351. /* 12MHz */
  352. .word 50, 0, 0, 1
  353. /* 13MHz */
  354. .word 600, 12, 0, 1
  355. /* 19.2MHz */
  356. .word 125, 3, 0, 1
  357. /* 26MHz */
  358. .word 300, 12, 0, 1
  359. /* 38.4MHz */
  360. .word 125, 7, 0, 1
  361. iva_36x_dpll_param:
  362. /* 12MHz */
  363. .word 130, 2, 0, 1
  364. /* 13MHz */
  365. .word 20, 0, 0, 1
  366. /* 19.2MHz */
  367. .word 325, 11, 0, 1
  368. /* 26MHz */
  369. .word 10, 0, 0, 1
  370. /* 38.4MHz */
  371. .word 325, 23, 0, 1
  372. core_36x_dpll_param:
  373. /* 12MHz */
  374. .word 100, 2, 0, 1
  375. /* 13MHz */
  376. .word 400, 12, 0, 1
  377. /* 19.2MHz */
  378. .word 375, 17, 0, 1
  379. /* 26MHz */
  380. .word 200, 12, 0, 1
  381. /* 38.4MHz */
  382. .word 375, 35, 0, 1
  383. per_36x_dpll_param:
  384. /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
  385. .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
  386. .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
  387. .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
  388. .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
  389. .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
  390. per2_36x_dpll_param:
  391. /* 12MHz */
  392. .word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
  393. /* 13MHz */
  394. .word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
  395. /* 19.2MHz */
  396. .word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
  397. /* 26MHz */
  398. .word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
  399. /* 38.4MHz */
  400. .word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
  401. ENTRY(get_36x_mpu_dpll_param)
  402. adr r0, mpu_36x_dpll_param
  403. mov pc, lr
  404. ENDPROC(get_36x_mpu_dpll_param)
  405. ENTRY(get_36x_iva_dpll_param)
  406. adr r0, iva_36x_dpll_param
  407. mov pc, lr
  408. ENDPROC(get_36x_iva_dpll_param)
  409. ENTRY(get_36x_core_dpll_param)
  410. adr r0, core_36x_dpll_param
  411. mov pc, lr
  412. ENDPROC(get_36x_core_dpll_param)
  413. ENTRY(get_36x_per_dpll_param)
  414. adr r0, per_36x_dpll_param
  415. mov pc, lr
  416. ENDPROC(get_36x_per_dpll_param)
  417. ENTRY(get_36x_per2_dpll_param)
  418. adr r0, per2_36x_dpll_param
  419. mov pc, lr
  420. ENDPROC(get_36x_per2_dpll_param)