sys_env_lib.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #ifndef _SYS_ENV_LIB_H
  6. #define _SYS_ENV_LIB_H
  7. #include "../../../drivers/ddr/marvell/a38x/ddr3_init.h"
  8. /* Serdes definitions */
  9. #define COMMON_PHY_BASE_ADDR 0x18300
  10. #define DEVICE_CONFIGURATION_REG0 0x18284
  11. #define DEVICE_CONFIGURATION_REG1 0x18288
  12. #define COMMON_PHY_CONFIGURATION1_REG 0x18300
  13. #define COMMON_PHY_CONFIGURATION2_REG 0x18304
  14. #define COMMON_PHY_CONFIGURATION4_REG 0x1830c
  15. #define COMMON_PHY_STATUS1_REG 0x18318
  16. #define COMMON_PHYS_SELECTORS_REG 0x183fc
  17. #define SOC_CONTROL_REG1 0x18204
  18. #define GENERAL_PURPOSE_RESERVED0_REG 0x182e0
  19. #define GBE_CONFIGURATION_REG 0x18460
  20. #define DEVICE_SAMPLE_AT_RESET1_REG 0x18600
  21. #define DEVICE_SAMPLE_AT_RESET2_REG 0x18604
  22. #define DEV_ID_REG 0x18238
  23. #define CORE_PLL_PARAMETERS_REG 0xe42e0
  24. #define CORE_PLL_CONFIG_REG 0xe42e4
  25. #define QSGMII_CONTROL_REG1 0x18494
  26. #define DEV_ID_REG_DEVICE_ID_OFFS 16
  27. #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
  28. #define SAR_FREQ_OFFSET 10
  29. #define SAR_FREQ_MASK 0x1f
  30. #define SAR_DEV_ID_OFFS 27
  31. #define SAR_DEV_ID_MASK 0x7
  32. #define POWER_AND_PLL_CTRL_REG 0xa0004
  33. #define CALIBRATION_CTRL_REG 0xa0008
  34. #define DFE_REG0 0xa001c
  35. #define DFE_REG3 0xa0028
  36. #define RESET_DFE_REG 0xa0148
  37. #define LOOPBACK_REG 0xa008c
  38. #define SYNC_PATTERN_REG 0xa0090
  39. #define INTERFACE_REG 0xa0094
  40. #define ISOLATE_REG 0xa0098
  41. #define MISC_REG 0xa013c
  42. #define GLUE_REG 0xa0140
  43. #define GENERATION_DIVIDER_FORCE_REG 0xa0144
  44. #define PCIE_REG0 0xa0120
  45. #define LANE_ALIGN_REG0 0xa0124
  46. #define SQUELCH_FFE_SETTING_REG 0xa0018
  47. #define G1_SETTINGS_0_REG 0xa0034
  48. #define G1_SETTINGS_1_REG 0xa0038
  49. #define G1_SETTINGS_3_REG 0xa0440
  50. #define G1_SETTINGS_4_REG 0xa0444
  51. #define G2_SETTINGS_0_REG 0xa003c
  52. #define G2_SETTINGS_1_REG 0xa0040
  53. #define G2_SETTINGS_2_REG 0xa00f8
  54. #define G2_SETTINGS_3_REG 0xa0448
  55. #define G2_SETTINGS_4_REG 0xa044c
  56. #define G3_SETTINGS_0_REG 0xa0044
  57. #define G3_SETTINGS_1_REG 0xa0048
  58. #define G3_SETTINGS_3_REG 0xa0450
  59. #define G3_SETTINGS_4_REG 0xa0454
  60. #define VTHIMPCAL_CTRL_REG 0xa0104
  61. #define REF_REG0 0xa0134
  62. #define CAL_REG6 0xa0168
  63. #define RX_REG2 0xa0184
  64. #define RX_REG3 0xa0188
  65. #define PCIE_REG1 0xa0288
  66. #define PCIE_REG3 0xa0290
  67. #define LANE_CFG0_REG 0xa0600
  68. #define LANE_CFG1_REG 0xa0604
  69. #define LANE_CFG4_REG 0xa0620
  70. #define LANE_CFG5_REG 0xa0624
  71. #define GLOBAL_CLK_CTRL 0xa0704
  72. #define GLOBAL_MISC_CTRL 0xa0718
  73. #define GLOBAL_CLK_SRC_HI 0xa0710
  74. #define GLOBAL_CLK_CTRL 0xa0704
  75. #define GLOBAL_MISC_CTRL 0xa0718
  76. #define GLOBAL_PM_CTRL 0xa0740
  77. /* SATA registers */
  78. #define SATA_CTRL_REG_IND_ADDR 0xa80a0
  79. #define SATA_CTRL_REG_IND_DATA 0xa80a4
  80. #define SATA_VENDOR_PORT_0_REG_ADDR 0xa8178
  81. #define SATA_VENDOR_PORT_1_REG_ADDR 0xa81f8
  82. #define SATA_VENDOR_PORT_0_REG_DATA 0xa817c
  83. #define SATA_VENDOR_PORT_1_REG_DATA 0xa81fc
  84. /* Reference clock values and mask */
  85. #define POWER_AND_PLL_CTRL_REG_100MHZ_VAL 0x0
  86. #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1 0x1
  87. #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2 0x2
  88. #define POWER_AND_PLL_CTRL_REG_40MHZ_VAL 0x3
  89. #define GLOBAL_PM_CTRL_REG_25MHZ_VAL 0x7
  90. #define GLOBAL_PM_CTRL_REG_40MHZ_VAL 0xc
  91. #define LANE_CFG4_REG_25MHZ_VAL 0x200
  92. #define LANE_CFG4_REG_40MHZ_VAL 0x300
  93. #define POWER_AND_PLL_CTRL_REG_MASK (~(0x1f))
  94. #define GLOBAL_PM_CTRL_REG_MASK (~(0xff))
  95. #define LANE_CFG4_REG_MASK (~(0x1f00))
  96. #define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1
  97. #define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1
  98. #define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1
  99. #define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1
  100. #define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1)
  101. #define MAX_SELECTOR_VAL 10
  102. /* TWSI addresses */
  103. /* starting from A38x A0, i2c address of EEPROM is 0x57 */
  104. #define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \
  105. MV_88F68XX_Z1_ID ? 0x50 : 0x57)
  106. #define RD_GET_MODE_ADDR 0x4c
  107. #define DB_GET_MODE_SLM1363_ADDR 0x25
  108. #define DB_GET_MODE_SLM1364_ADDR 0x24
  109. #define DB381_GET_MODE_SLM1426_1427_ADDR 0x56
  110. /* DB-BP Board 'SatR' mapping */
  111. #define SATR_DB_LANE1_MAX_OPTIONS 7
  112. #define SATR_DB_LANE1_CFG_MASK 0x7
  113. #define SATR_DB_LANE1_CFG_OFFSET 0
  114. #define SATR_DB_LANE2_MAX_OPTIONS 4
  115. #define SATR_DB_LANE2_CFG_MASK 0x38
  116. #define SATR_DB_LANE2_CFG_OFFSET 3
  117. /* GP Board 'SatR' mapping */
  118. #define SATR_GP_LANE1_CFG_MASK 0x4
  119. #define SATR_GP_LANE1_CFG_OFFSET 2
  120. #define SATR_GP_LANE2_CFG_MASK 0x8
  121. #define SATR_GP_LANE2_CFG_OFFSET 3
  122. /* For setting MPP2 and MPP3 to be TWSI mode and MPP 0,1 to UART mode */
  123. #define MPP_CTRL_REG 0x18000
  124. #define MPP_SET_MASK (~(0xffff))
  125. #define MPP_SET_DATA (0x1111)
  126. #define MPP_UART1_SET_MASK (~(0xff000))
  127. #define MPP_UART1_SET_DATA (0x66000)
  128. #define DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS 0
  129. /* DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS: Since address completion in 14bit
  130. * address mode, and given that [14:8] => [19:13], the 2 lower bits [9:8] =>
  131. * [14:13] are dismissed. hence field offset is also shifted to 10
  132. */
  133. #define DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS 10
  134. #define RTC_MEMORY_CTRL_REG_BASE 0xE6000
  135. #define RTC_MEMORY_WRAPPER_COUNT 8
  136. #define RTC_MEMORY_WRAPPER_REG(i) (RTC_MEMORY_CTRL_REG_BASE + ((i) * 0x40))
  137. #define RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS 6
  138. #define RTC_MEMORY_WRAPPER_CTRL_VAL (0x1 << RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS)
  139. #define AVS_DEBUG_CNTR_REG 0xe4124
  140. #define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073
  141. #define AVS_ENABLED_CONTROL 0xe4130
  142. #define AVS_LOW_VDD_LIMIT_OFFS 4
  143. #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS)
  144. #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS)
  145. #define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS)
  146. #define AVS_HIGH_VDD_LIMIT_OFFS 12
  147. #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS)
  148. #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS)
  149. #define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
  150. /* Board ID numbers */
  151. #define MARVELL_BOARD_ID_MASK 0x10
  152. /* Customer boards for A38x */
  153. #define A38X_CUSTOMER_BOARD_ID_BASE 0x0
  154. #define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0)
  155. #define A38X_CUSTOMER_BOARD_ID1 (A38X_CUSTOMER_BOARD_ID_BASE + 1)
  156. #define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUSTOMER_BOARD_ID_BASE + 2)
  157. #define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - \
  158. A38X_CUSTOMER_BOARD_ID_BASE)
  159. /* Marvell boards for A38x */
  160. #define A38X_MARVELL_BOARD_ID_BASE 0x10
  161. #define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0)
  162. #define DB_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 1)
  163. #define RD_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 2)
  164. #define DB_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 3)
  165. #define DB_GP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 4)
  166. #define DB_BP_6821_ID (A38X_MARVELL_BOARD_ID_BASE + 5)
  167. #define DB_AMC_6820_ID (A38X_MARVELL_BOARD_ID_BASE + 6)
  168. #define A38X_MV_MAX_MARVELL_BOARD_ID (A38X_MARVELL_BOARD_ID_BASE + 7)
  169. #define A38X_MV_MARVELL_BOARD_NUM (A38X_MV_MAX_MARVELL_BOARD_ID - \
  170. A38X_MARVELL_BOARD_ID_BASE)
  171. /* Customer boards for A39x */
  172. #define A39X_CUSTOMER_BOARD_ID_BASE 0x20
  173. #define A39X_CUSTOMER_BOARD_ID0 (A39X_CUSTOMER_BOARD_ID_BASE + 0)
  174. #define A39X_CUSTOMER_BOARD_ID1 (A39X_CUSTOMER_BOARD_ID_BASE + 1)
  175. #define A39X_MV_MAX_CUSTOMER_BOARD_ID (A39X_CUSTOMER_BOARD_ID_BASE + 2)
  176. #define A39X_MV_CUSTOMER_BOARD_NUM (A39X_MV_MAX_CUSTOMER_BOARD_ID - \
  177. A39X_CUSTOMER_BOARD_ID_BASE)
  178. /* Marvell boards for A39x */
  179. #define A39X_MARVELL_BOARD_ID_BASE 0x30
  180. #define A39X_DB_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 0)
  181. #define A39X_RD_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 1)
  182. #define A39X_MV_MAX_MARVELL_BOARD_ID (A39X_MARVELL_BOARD_ID_BASE + 2)
  183. #define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \
  184. A39X_MARVELL_BOARD_ID_BASE)
  185. #define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE
  186. #define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0
  187. #define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1
  188. #define MV_MAX_CUSTOMER_BOARD_ID A38X_MV_MAX_CUSTOMER_BOARD_ID
  189. #define MV_CUSTOMER_BOARD_NUM A38X_MV_CUSTOMER_BOARD_NUM
  190. #define MARVELL_BOARD_ID_BASE A38X_MARVELL_BOARD_ID_BASE
  191. #define MV_MAX_MARVELL_BOARD_ID A38X_MV_MAX_MARVELL_BOARD_ID
  192. #define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM
  193. #define MV_DEFAULT_BOARD_ID DB_68XX_ID
  194. #define MV_DEFAULT_DEVICE_ID MV_6811
  195. #define MV_INVALID_BOARD_ID 0xffffffff
  196. /* device revesion */
  197. #define DEV_VERSION_ID_REG 0x1823c
  198. #define REVISON_ID_OFFS 8
  199. #define REVISON_ID_MASK 0xf00
  200. /* A38x revisions */
  201. #define MV_88F68XX_Z1_ID 0x0
  202. #define MV_88F68XX_A0_ID 0x4
  203. #define MV_88F68XX_B0_ID 0xa
  204. /* A39x revisions */
  205. #define MV_88F69XX_Z1_ID 0x2
  206. #define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
  207. #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
  208. #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
  209. #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
  210. #define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40))
  211. #define MPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 8)
  212. #define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \
  213. (MPP_REG_NUM(GPIO_NUM) * 8)));
  214. #define GPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 32)
  215. #define GPP_MASK(GPIO_NUM) (1 << GPIO_NUM % 32)
  216. /* device ID */
  217. /* Armada 38x Family */
  218. #define MV_6810_DEV_ID 0x6810
  219. #define MV_6811_DEV_ID 0x6811
  220. #define MV_6820_DEV_ID 0x6820
  221. #define MV_6828_DEV_ID 0x6828
  222. /* Armada 39x Family */
  223. #define MV_6920_DEV_ID 0x6920
  224. #define MV_6928_DEV_ID 0x6928
  225. enum {
  226. MV_6810,
  227. MV_6820,
  228. MV_6811,
  229. MV_6828,
  230. MV_NONE,
  231. MV_6920,
  232. MV_6928,
  233. MV_MAX_DEV_ID,
  234. };
  235. #define MV_6820_INDEX 0
  236. #define MV_6810_INDEX 1
  237. #define MV_6811_INDEX 2
  238. #define MV_6828_INDEX 3
  239. #define MV_6920_INDEX 0
  240. #define MV_6928_INDEX 1
  241. #define MAX_DEV_ID_NUM 4
  242. #define MV_6820_INDEX 0
  243. #define MV_6810_INDEX 1
  244. #define MV_6811_INDEX 2
  245. #define MV_6828_INDEX 3
  246. #define MV_6920_INDEX 0
  247. #define MV_6928_INDEX 1
  248. enum unit_id {
  249. PEX_UNIT_ID,
  250. ETH_GIG_UNIT_ID,
  251. USB3H_UNIT_ID,
  252. USB3D_UNIT_ID,
  253. SATA_UNIT_ID,
  254. QSGMII_UNIT_ID,
  255. XAUI_UNIT_ID,
  256. RXAUI_UNIT_ID,
  257. MAX_UNITS_ID
  258. };
  259. struct board_wakeup_gpio {
  260. u32 board_id;
  261. int gpio_num;
  262. };
  263. enum suspend_wakeup_status {
  264. SUSPEND_WAKEUP_DISABLED,
  265. SUSPEND_WAKEUP_ENABLED,
  266. SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED,
  267. };
  268. /*
  269. * GPIO status indication for Suspend Wakeup:
  270. * If suspend to RAM is supported and GPIO inidcation is implemented,
  271. * set the gpio number
  272. * If suspend to RAM is supported but GPIO indication is not implemented
  273. * set '-2'
  274. * If suspend to RAM is not supported set '-1'
  275. */
  276. #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
  277. #define MV_BOARD_WAKEUP_GPIO_INFO { \
  278. {A38X_CUSTOMER_BOARD_ID0, -1 }, \
  279. {A38X_CUSTOMER_BOARD_ID0, -1 }, \
  280. };
  281. #else
  282. #define MV_BOARD_WAKEUP_GPIO_INFO { \
  283. {RD_NAS_68XX_ID, -2 }, \
  284. {DB_68XX_ID, -1 }, \
  285. {RD_AP_68XX_ID, -2 }, \
  286. {DB_AP_68XX_ID, -2 }, \
  287. {DB_GP_68XX_ID, -2 }, \
  288. {DB_BP_6821_ID, -2 }, \
  289. {DB_AMC_6820_ID, -2 }, \
  290. };
  291. #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
  292. u32 mv_board_tclk_get(void);
  293. u32 mv_board_id_get(void);
  294. u32 mv_board_id_index_get(u32 board_id);
  295. u32 sys_env_unit_max_num_get(enum unit_id unit);
  296. enum suspend_wakeup_status sys_env_suspend_wakeup_check(void);
  297. u8 sys_env_device_rev_get(void);
  298. u32 sys_env_device_id_get(void);
  299. u16 sys_env_model_get(void);
  300. struct dlb_config *sys_env_dlb_config_ptr_get(void);
  301. u32 sys_env_get_cs_ena_from_reg(void);
  302. #endif /* _SYS_ENV_LIB_H */