high_speed_env_spec.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #include <common.h>
  6. #include <spl.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/cpu.h>
  9. #include <asm/arch/soc.h>
  10. #include <linux/delay.h>
  11. #include "high_speed_env_spec.h"
  12. #include "sys_env_lib.h"
  13. #include "ctrl_pex.h"
  14. /*
  15. * serdes_seq_db - holds all serdes sequences, their size and the
  16. * relevant index in the data array initialized in serdes_seq_init
  17. */
  18. struct cfg_seq serdes_seq_db[SERDES_LAST_SEQ];
  19. #define SERDES_VERSION "2.0"
  20. #define ENDED_OK "High speed PHY - Ended Successfully\n"
  21. #define LINK_WAIT_CNTR 100
  22. #define LINK_WAIT_SLEEP 100
  23. #define MAX_UNIT_NUMB 4
  24. #define TOPOLOGY_TEST_OK 0
  25. #define WRONG_NUMBER_OF_UNITS 1
  26. #define SERDES_ALREADY_IN_USE 2
  27. #define UNIT_NUMBER_VIOLATION 3
  28. /*
  29. * serdes_lane_in_use_count contains the exact amount of serdes lanes
  30. * needed per type
  31. */
  32. u8 serdes_lane_in_use_count[MAX_UNITS_ID][MAX_UNIT_NUMB] = {
  33. /* 0 1 2 3 */
  34. { 1, 1, 1, 1 }, /* PEX */
  35. { 1, 1, 1, 1 }, /* ETH_GIG */
  36. { 1, 1, 0, 0 }, /* USB3H */
  37. { 1, 1, 1, 0 }, /* USB3D */
  38. { 1, 1, 1, 1 }, /* SATA */
  39. { 1, 0, 0, 0 }, /* QSGMII */
  40. { 4, 0, 0, 0 }, /* XAUI */
  41. { 2, 0, 0, 0 } /* RXAUI */
  42. };
  43. /*
  44. * serdes_unit_count count unit number.
  45. * (i.e a single XAUI is counted as 1 unit)
  46. */
  47. u8 serdes_unit_count[MAX_UNITS_ID] = { 0 };
  48. /* Selector mapping for A380-A0 and A390-Z1 */
  49. u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = {
  50. /* 0 1 2 3 4 5 6 */
  51. { 0x1, 0x1, NA, NA, NA, NA, NA }, /* PEX0 */
  52. { NA, NA, 0x1, NA, 0x1, NA, 0x1 }, /* PEX1 */
  53. { NA, NA, NA, NA, 0x7, 0x1, NA }, /* PEX2 */
  54. { NA, NA, NA, 0x1, NA, NA, NA }, /* PEX3 */
  55. { 0x2, 0x3, NA, NA, NA, NA, NA }, /* SATA0 */
  56. { NA, NA, 0x3, NA, NA, NA, NA }, /* SATA1 */
  57. { NA, NA, NA, NA, 0x6, 0x2, NA }, /* SATA2 */
  58. { NA, NA, NA, 0x3, NA, NA, NA }, /* SATA3 */
  59. { 0x3, 0x4, NA, NA, NA, NA, NA }, /* SGMII0 */
  60. { NA, 0x5, 0x4, NA, 0x3, NA, NA }, /* SGMII1 */
  61. { NA, NA, NA, 0x4, NA, 0x3, NA }, /* SGMII2 */
  62. { NA, 0x7, NA, NA, NA, NA, NA }, /* QSGMII */
  63. { NA, 0x6, NA, NA, 0x4, NA, NA }, /* USB3_HOST0 */
  64. { NA, NA, NA, 0x5, NA, 0x4, NA }, /* USB3_HOST1 */
  65. { NA, NA, NA, 0x6, 0x5, 0x5, NA }, /* USB3_DEVICE */
  66. { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, NA } /* DEFAULT_SERDES */
  67. };
  68. /* Selector mapping for PEX by 4 confiuration */
  69. u8 common_phys_selectors_pex_by4_lanes[] = { 0x1, 0x2, 0x2, 0x2 };
  70. static const char *const serdes_type_to_string[] = {
  71. "PCIe0",
  72. "PCIe1",
  73. "PCIe2",
  74. "PCIe3",
  75. "SATA0",
  76. "SATA1",
  77. "SATA2",
  78. "SATA3",
  79. "SGMII0",
  80. "SGMII1",
  81. "SGMII2",
  82. "QSGMII",
  83. "USB3 HOST0",
  84. "USB3 HOST1",
  85. "USB3 DEVICE",
  86. "SGMII3",
  87. "XAUI",
  88. "RXAUI",
  89. "DEFAULT SERDES",
  90. "LAST_SERDES_TYPE"
  91. };
  92. struct serdes_unit_data {
  93. u8 serdes_unit_id;
  94. u8 serdes_unit_num;
  95. };
  96. static struct serdes_unit_data serdes_type_to_unit_info[] = {
  97. {PEX_UNIT_ID, 0,},
  98. {PEX_UNIT_ID, 1,},
  99. {PEX_UNIT_ID, 2,},
  100. {PEX_UNIT_ID, 3,},
  101. {SATA_UNIT_ID, 0,},
  102. {SATA_UNIT_ID, 1,},
  103. {SATA_UNIT_ID, 2,},
  104. {SATA_UNIT_ID, 3,},
  105. {ETH_GIG_UNIT_ID, 0,},
  106. {ETH_GIG_UNIT_ID, 1,},
  107. {ETH_GIG_UNIT_ID, 2,},
  108. {QSGMII_UNIT_ID, 0,},
  109. {USB3H_UNIT_ID, 0,},
  110. {USB3H_UNIT_ID, 1,},
  111. {USB3D_UNIT_ID, 0,},
  112. {ETH_GIG_UNIT_ID, 3,},
  113. {XAUI_UNIT_ID, 0,},
  114. {RXAUI_UNIT_ID, 0,},
  115. };
  116. /* Sequences DB */
  117. /*
  118. * SATA and SGMII
  119. */
  120. struct op_params sata_port0_power_up_params[] = {
  121. /*
  122. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  123. * num_of_loops
  124. */
  125. /* Access to reg 0x48(OOB param 1) */
  126. {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0},
  127. /* OOB Com_wake and Com_reset spacing upper limit data */
  128. {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0},
  129. /* Access to reg 0xa(PHY Control) */
  130. {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0},
  131. /* Rx clk and Tx clk select non-inverted mode */
  132. {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0},
  133. /* Power Down Sata addr */
  134. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0},
  135. /* Power Down Sata Port 0 */
  136. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40040,}, 0, 0},
  137. };
  138. struct op_params sata_port1_power_up_params[] = {
  139. /*
  140. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  141. * num_of_loops
  142. */
  143. /* Access to reg 0x48(OOB param 1) */
  144. {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0},
  145. /* OOB Com_wake and Com_reset spacing upper limit data */
  146. {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0},
  147. /* Access to reg 0xa(PHY Control) */
  148. {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0},
  149. /* Rx clk and Tx clk select non-inverted mode */
  150. {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0},
  151. /* Power Down Sata addr */
  152. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0},
  153. /* Power Down Sata Port 1 */
  154. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc44000,}, 0, 0},
  155. };
  156. /* SATA and SGMII - power up seq */
  157. struct op_params sata_and_sgmii_power_up_params[] = {
  158. /*
  159. * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
  160. * wait_time, num_of_loops
  161. */
  162. /* Power Up */
  163. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x90006, {0x80002, 0x80002},
  164. 0, 0},
  165. /* Unreset */
  166. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0x6000}, 0, 0},
  167. /* Phy Selector */
  168. {POWER_AND_PLL_CTRL_REG, 0x800, 0x0e0, {0x0, 0x80}, 0, 0},
  169. /* Ref clock source select */
  170. {MISC_REG, 0x800, 0x440, {0x440, 0x400}, 0, 0}
  171. };
  172. /* SATA and SGMII - speed config seq */
  173. struct op_params sata_and_sgmii_speed_config_params[] = {
  174. /*
  175. * unit_base_reg, unit_offset, mask, SATA data,
  176. * SGMII (1.25G), SGMII (3.125G), wait_time, num_of_loops
  177. */
  178. /* Baud Rate */
  179. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000,
  180. {0x8800000, 0x19800000, 0x22000000}, 0, 0},
  181. /* Select Baud Rate for SATA only */
  182. {INTERFACE_REG, 0x800, 0xc00, {0x800, NO_DATA, NO_DATA}, 0, 0},
  183. /* Phy Gen RX and TX */
  184. {ISOLATE_REG, 0x800, 0xff, {NO_DATA, 0x66, 0x66}, 0, 0},
  185. /* Bus Width */
  186. {LOOPBACK_REG, 0x800, 0xe, {0x4, 0x2, 0x2}, 0, 0}
  187. };
  188. /* SATA and SGMII - TX config seq */
  189. struct op_params sata_and_sgmii_tx_config_params1[] = {
  190. /*
  191. * unitunit_base_reg, unit_offset, mask, SATA data, SGMII data,
  192. * wait_time, num_of_loops
  193. */
  194. {GLUE_REG, 0x800, 0x1800, {NO_DATA, 0x800}, 0, 0},
  195. /* Sft Reset pulse */
  196. {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0},
  197. /* Sft Reset pulse */
  198. {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0},
  199. /* Power up PLL, RX and TX */
  200. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0000, {0x70000, 0x70000},
  201. 0, 0}
  202. };
  203. struct op_params sata_port0_tx_config_params[] = {
  204. /*
  205. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  206. * num_of_loops
  207. */
  208. /* Power Down Sata addr */
  209. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0},
  210. /* Power Down Sata Port 0 */
  211. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40000}, 0, 0},
  212. /* Regret bit addr */
  213. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0},
  214. /* Regret bit data */
  215. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0}
  216. };
  217. struct op_params sata_port1_tx_config_params[] = {
  218. /*
  219. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  220. * num_of_loops
  221. */
  222. /* Power Down Sata addr */
  223. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0},
  224. /* Power Down Sata Port 1 */
  225. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc40000}, 0, 0},
  226. /* Regret bit addr */
  227. {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0},
  228. /* Regret bit data */
  229. {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0}
  230. };
  231. struct op_params sata_and_sgmii_tx_config_serdes_rev1_params2[] = {
  232. /*
  233. * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
  234. * wait_time, num_of_loops
  235. */
  236. /* Wait for PHY power up sequence to finish */
  237. {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000},
  238. /* Wait for PHY power up sequence to finish */
  239. {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000}
  240. };
  241. struct op_params sata_and_sgmii_tx_config_serdes_rev2_params2[] = {
  242. /*
  243. * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
  244. * wait_time, num_of_loops
  245. */
  246. /* Wait for PHY power up sequence to finish */
  247. {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000},
  248. /* Assert Rx Init for SGMII */
  249. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x40000000},
  250. 0, 0},
  251. /* Assert Rx Init for SATA */
  252. {ISOLATE_REG, 0x800, 0x400, {0x400, NA}, 0, 0},
  253. /* Wait for PHY power up sequence to finish */
  254. {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000},
  255. /* De-assert Rx Init for SGMII */
  256. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x0}, 0, 0},
  257. /* De-assert Rx Init for SATA */
  258. {ISOLATE_REG, 0x800, 0x400, {0x0, NA}, 0, 0},
  259. /* os_ph_offset_force (align 90) */
  260. {RX_REG3, 0x800, 0xff, {0xde, NO_DATA}, 0, 0},
  261. /* Set os_ph_valid */
  262. {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0},
  263. /* Unset os_ph_valid */
  264. {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0},
  265. };
  266. struct op_params sata_electrical_config_serdes_rev1_params[] = {
  267. /*
  268. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  269. * num_of_loops
  270. */
  271. /* enable SSC and DFE update enable */
  272. {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000,}, 0, 0},
  273. /* tximpcal_th and rximpcal_th */
  274. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000,}, 0, 0},
  275. /* SQ_THRESH and FFE Setting */
  276. {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x6cf,}, 0, 0},
  277. /* G1_TX SLEW, EMPH1 and AMP */
  278. {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32,}, 0, 0},
  279. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  280. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9,}, 0, 0},
  281. /* G2_TX SLEW, EMPH1 and AMP */
  282. {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c,}, 0, 0},
  283. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  284. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0},
  285. /* G3_TX SLEW, EMPH1 and AMP */
  286. {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e,}, 0, 0},
  287. /* G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  288. {G3_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0},
  289. /* Cal rxclkalign90 ext enable and Cal os ph ext */
  290. {CAL_REG6, 0x800, 0xff00, {0xdd00,}, 0, 0},
  291. /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */
  292. {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0},
  293. };
  294. struct op_params sata_electrical_config_serdes_rev2_params[] = {
  295. /*
  296. * unit_base_reg, unit_offset, mask, SATA data, wait_time,
  297. * num_of_loops
  298. */
  299. /* SQ_THRESH and FFE Setting */
  300. {SQUELCH_FFE_SETTING_REG, 0x800, 0xf00, {0x600}, 0, 0},
  301. /* enable SSC and DFE update enable */
  302. {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000}, 0, 0},
  303. /* G1_TX SLEW, EMPH1 and AMP */
  304. {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32}, 0, 0},
  305. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  306. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  307. /* G2_TX SLEW, EMPH1 and AMP */
  308. {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c}, 0, 0},
  309. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  310. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
  311. /* G3_TX SLEW, EMPH1 and AMP */
  312. {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e}, 0, 0},
  313. /*
  314. * G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI & DFE_En Gen3,
  315. * DC wander calibration dis
  316. */
  317. {G3_SETTINGS_1_REG, 0x800, 0x47ff, {0x7d2}, 0, 0},
  318. /* Bit[12]=0x0 idle_sync_en */
  319. {PCIE_REG0, 0x800, 0x1000, {0x0}, 0, 0},
  320. /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */
  321. {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0},
  322. /* tximpcal_th and rximpcal_th */
  323. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
  324. /* DFE_STEP_FINE_FX[3:0] =0xa */
  325. {DFE_REG0, 0x800, 0xa00f, {0x800a}, 0, 0},
  326. /* DFE_EN and Dis Update control from pin disable */
  327. {DFE_REG3, 0x800, 0xc000, {0x0}, 0, 0},
  328. /* FFE Force FFE_REs and cap settings for Gen1 */
  329. {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
  330. /* FFE Force FFE_REs and cap settings for Gen2 */
  331. {G2_SETTINGS_3_REG, 0x800, 0xff, {0xbf}, 0, 0},
  332. /* FE Force FFE_REs=4 and cap settings for Gen3n */
  333. {G3_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
  334. /* Set DFE Gen 3 Resolution to 3 */
  335. {G3_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0},
  336. };
  337. struct op_params sgmii_electrical_config_serdes_rev1_params[] = {
  338. /*
  339. * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G),
  340. * wait_time, num_of_loops
  341. */
  342. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  343. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0},
  344. /* SQ_THRESH and FFE Setting */
  345. {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x8f, 0xbf}, 0, 0},
  346. /* tximpcal_th and rximpcal_th */
  347. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000, 0x4000}, 0, 0},
  348. };
  349. struct op_params sgmii_electrical_config_serdes_rev2_params[] = {
  350. /*
  351. * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G),
  352. * wait_time, num_of_loops
  353. */
  354. /* Set Slew_rate, Emph and Amp */
  355. {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8fa, 0x8fa}, 0, 0},
  356. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  357. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0},
  358. /* DTL_FLOOP_EN */
  359. {RX_REG2, 0x800, 0x4, {0x0, 0x0}, 0, 0},
  360. /* G1 FFE Setting Force, RES and CAP */
  361. {G1_SETTINGS_3_REG, 0x800, 0xff, {0x8f, 0xbf}, 0, 0},
  362. /* tximpcal_th and rximpcal_th */
  363. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000, 0x3000}, 0, 0},
  364. };
  365. /*
  366. * PEX and USB3
  367. */
  368. /* PEX and USB3 - power up seq for Serdes Rev 1.2 */
  369. struct op_params pex_and_usb3_power_up_serdes_rev1_params[] = {
  370. /*
  371. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  372. * wait_time, num_of_loops
  373. */
  374. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806,
  375. {0x4471804, 0x4479804}, 0, 0},
  376. {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0},
  377. {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0},
  378. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0},
  379. {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0},
  380. /* Ref clock source select */
  381. {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0}
  382. };
  383. /* PEX and USB3 - power up seq for Serdes Rev 2.1 */
  384. struct op_params pex_and_usb3_power_up_serdes_rev2_params[] = {
  385. /*
  386. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  387. * wait_time, num_of_loops
  388. */
  389. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806,
  390. {0x4471804, 0x4479804}, 0, 0},
  391. {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0},
  392. {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0},
  393. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0},
  394. {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0},
  395. {GLOBAL_MISC_CTRL, 0x800, 0xc0, {0x0, NO_DATA}, 0, 0},
  396. /* Ref clock source select */
  397. {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0}
  398. };
  399. /* PEX and USB3 - speed config seq */
  400. struct op_params pex_and_usb3_speed_config_params[] = {
  401. /*
  402. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  403. * wait_time, num_of_loops
  404. */
  405. /* Maximal PHY Generation Setting */
  406. {INTERFACE_REG, 0x800, 0xc00, {0x400, 0x400, 0x400, 0x400, 0x400},
  407. 0, 0},
  408. };
  409. struct op_params usb3_electrical_config_serdes_rev1_params[] = {
  410. /* Spread Spectrum Clock Enable */
  411. {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0},
  412. /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */
  413. {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0},
  414. /* tximpcal_th and rximpcal_th */
  415. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000}, 0, 0},
  416. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  417. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
  418. /* FFE Setting Force, RES and CAP */
  419. {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xef}, 0, 0},
  420. /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
  421. {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0},
  422. /* cal_rxclkalign90_ext_en and cal_os_ph_ext */
  423. {CAL_REG6, 0x800, 0xff00, {0xd500}, 0, 0},
  424. /* vco_cal_vth_sel */
  425. {REF_REG0, 0x800, 0x38, {0x20}, 0, 0},
  426. };
  427. struct op_params usb3_electrical_config_serdes_rev2_params[] = {
  428. /* Spread Spectrum Clock Enable */
  429. {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0},
  430. /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */
  431. {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0},
  432. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  433. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
  434. /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
  435. {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0},
  436. /* vco_cal_vth_sel */
  437. {REF_REG0, 0x800, 0x38, {0x20}, 0, 0},
  438. /* Spread Spectrum Clock Enable */
  439. {LANE_CFG5_REG, 0x800, 0x4, {0x4}, 0, 0},
  440. };
  441. /* PEX and USB3 - TX config seq */
  442. /*
  443. * For PEXx1: the pex_and_usb3_tx_config_params1/2/3 configurations should run
  444. * one by one on the lane.
  445. * For PEXx4: the pex_and_usb3_tx_config_params1/2/3 configurations should run
  446. * by setting each sequence for all 4 lanes.
  447. */
  448. struct op_params pex_and_usb3_tx_config_params1[] = {
  449. /*
  450. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  451. * wait_time, num_of_loops
  452. */
  453. {GLOBAL_CLK_CTRL, 0x800, 0x1, {0x0, 0x0}, 0, 0},
  454. /* 10ms delay */
  455. {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0},
  456. /* os_ph_offset_force (align 90) */
  457. {RX_REG3, 0x800, 0xff, {0xdc, NO_DATA}, 0, 0},
  458. /* Set os_ph_valid */
  459. {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0},
  460. /* Unset os_ph_valid */
  461. {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0},
  462. };
  463. struct op_params pex_and_usb3_tx_config_params2[] = {
  464. /*
  465. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  466. * wait_time, num_of_loops
  467. */
  468. /* Sft Reset pulse */
  469. {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0},
  470. };
  471. struct op_params pex_and_usb3_tx_config_params3[] = {
  472. /*
  473. * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
  474. * wait_time, num_of_loops
  475. */
  476. /* Sft Reset pulse */
  477. {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0},
  478. /* 10ms delay */
  479. {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0}
  480. };
  481. /* PEX by 4 config seq */
  482. struct op_params pex_by4_config_params[] = {
  483. /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
  484. {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0},
  485. /* Lane Alignment enable */
  486. {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0},
  487. /* Max PLL phy config */
  488. {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000},
  489. 0, 0},
  490. /* Max PLL pipe config */
  491. {LANE_CFG1_REG, 0x800, 0x600, {0x600, 0x600, 0x600, 0x600}, 0, 0},
  492. };
  493. /* USB3 device donfig seq */
  494. struct op_params usb3_device_config_params[] = {
  495. /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
  496. {LANE_CFG4_REG, 0x800, 0x200, {0x200}, 0, 0}
  497. };
  498. /* PEX - electrical configuration seq Rev 1.2 */
  499. struct op_params pex_electrical_config_serdes_rev1_params[] = {
  500. /*
  501. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  502. * num_of_loops
  503. */
  504. /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */
  505. {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0},
  506. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  507. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  508. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  509. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  510. /* CFG_DFE_EN_SEL */
  511. {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0},
  512. /* FFE Setting Force, RES and CAP */
  513. {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xaf}, 0, 0},
  514. /* tximpcal_th and rximpcal_th */
  515. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
  516. /* cal_rxclkalign90_ext_en and cal_os_ph_ext */
  517. {CAL_REG6, 0x800, 0xff00, {0xdc00}, 0, 0},
  518. };
  519. /* PEX - electrical configuration seq Rev 2.1 */
  520. struct op_params pex_electrical_config_serdes_rev2_params[] = {
  521. /*
  522. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  523. * num_of_loops
  524. */
  525. /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */
  526. {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0},
  527. /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  528. {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  529. /* G1 FFE Setting Force, RES and CAP */
  530. {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
  531. /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
  532. {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
  533. /* G2 FFE Setting Force, RES and CAP */
  534. {G2_SETTINGS_3_REG, 0x800, 0xff, {0xaf}, 0, 0},
  535. /* G2 DFE resolution value */
  536. {G2_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0},
  537. /* DFE resolution force */
  538. {DFE_REG0, 0x800, 0x8000, {0x8000}, 0, 0},
  539. /* Tx amplitude for Tx Margin 0 */
  540. {PCIE_REG1, 0x800, 0xf80, {0xd00}, 0, 0},
  541. /* Tx_Emph value for -3.5d_b and -6d_b */
  542. {PCIE_REG3, 0x800, 0xff00, {0xaf00}, 0, 0},
  543. /* CFG_DFE_EN_SEL */
  544. {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0},
  545. /* tximpcal_th and rximpcal_th */
  546. {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
  547. /* Force receiver detected */
  548. {LANE_CFG0_REG, 0x800, 0x8000, {0x8000}, 0, 0},
  549. };
  550. /* PEX - configuration seq for REF_CLOCK_25MHz */
  551. struct op_params pex_config_ref_clock25_m_hz[] = {
  552. /*
  553. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  554. * num_of_loops
  555. */
  556. /* Bits[4:0]=0x2 - REF_FREF_SEL */
  557. {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x2}, 0, 0},
  558. /* Bit[10]=0x1 - REFCLK_SEL */
  559. {MISC_REG, 0x800, 0x400, {0x400}, 0, 0},
  560. /* Bits[7:0]=0x7 - CFG_PM_RXDLOZ_WAIT */
  561. {GLOBAL_PM_CTRL, 0x800, 0xff, {0x7}, 0, 0},
  562. };
  563. /* PEX - configuration seq for REF_CLOCK_40MHz */
  564. struct op_params pex_config_ref_clock40_m_hz[] = {
  565. /*
  566. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  567. * num_of_loops
  568. */
  569. /* Bits[4:0]=0x3 - REF_FREF_SEL */
  570. {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x3}, 0, 0},
  571. /* Bits[10]=0x1 - REFCLK_SEL */
  572. {MISC_REG, 0x800, 0x400, {0x400}, 0, 0},
  573. /* Bits[7:0]=0xc - CFG_PM_RXDLOZ_WAIT */
  574. {GLOBAL_PM_CTRL, 0x800, 0xff, {0xc}, 0, 0},
  575. };
  576. /* PEX - configuration seq for REF_CLOCK_100MHz */
  577. struct op_params pex_config_ref_clock100_m_hz[] = {
  578. /*
  579. * unit_base_reg, unit_offset, mask, PEX data, wait_time,
  580. * num_of_loops
  581. */
  582. /* Bits[4:0]=0x0 - REF_FREF_SEL */
  583. {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x0}, 0, 0},
  584. /* Bit[10]=0x0 - REFCLK_SEL */
  585. {MISC_REG, 0x800, 0x400, {0x0}, 0, 0},
  586. /* Bits[7:0]=0x1e - CFG_PM_RXDLOZ_WAIT */
  587. {GLOBAL_PM_CTRL, 0x800, 0xff, {0x1e}, 0, 0},
  588. };
  589. /*
  590. * USB2
  591. */
  592. struct op_params usb2_power_up_params[] = {
  593. /*
  594. * unit_base_reg, unit_offset, mask, USB2 data, wait_time,
  595. * num_of_loops
  596. */
  597. /* Init phy 0 */
  598. {0x18440, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
  599. /* Init phy 1 */
  600. {0x18444, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
  601. /* Init phy 2 */
  602. {0x18448, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
  603. /* Phy offset 0x0 - PLL_CONTROL0 */
  604. {0xc0000, 0x0 /*NA*/, 0xffffffff, {0x40605205}, 0, 0},
  605. {0xc001c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
  606. {0xc201c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
  607. {0xc401c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
  608. /* Phy offset 0x1 - PLL_CONTROL1 */
  609. {0xc0004, 0x0 /*NA*/, 0x1, {0x1}, 0, 0},
  610. /* Phy0 register 3 - TX Channel control 0 */
  611. {0xc000c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
  612. /* Phy0 register 3 - TX Channel control 0 */
  613. {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
  614. /* Phy0 register 3 - TX Channel control 0 */
  615. {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
  616. /* Decrease the amplitude of the low speed eye to meet the spec */
  617. {0xc000c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
  618. {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
  619. {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
  620. /* Change the High speed impedance threshold */
  621. {0xc0008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0},
  622. {0xc2008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0},
  623. {0xc4008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0},
  624. /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */
  625. {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
  626. {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
  627. {0xc4014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
  628. /* Check PLLCAL_DONE is set and IMPCAL_DONE is set */
  629. {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000},
  630. /* Check REG_SQCAL_DONE is set */
  631. {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
  632. /* Check PLL_READY is set */
  633. {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
  634. /* Start calibrate of high seed impedance */
  635. {0xc0008, 0x0 /*NA*/, 0x2000, {0x2000}, 0, 0},
  636. {0x0, 0x0 /*NA*/, 0x0, {0x0}, 10, 0},
  637. /* De-assert the calibration signal */
  638. {0xc0008, 0x0 /*NA*/, 0x2000, {0x0}, 0, 0},
  639. };
  640. /*
  641. * QSGMII
  642. */
  643. /* QSGMII - power up seq */
  644. struct op_params qsgmii_port_power_up_params[] = {
  645. /*
  646. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  647. * num_of_loops
  648. */
  649. /* Connect the QSGMII to Gigabit Ethernet units */
  650. {QSGMII_CONTROL_REG1, 0x0, 0x40000000, {0x40000000}, 0, 0},
  651. /* Power Up */
  652. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0006, {0x80002}, 0, 0},
  653. /* Unreset */
  654. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000}, 0, 0},
  655. /* Phy Selector */
  656. {POWER_AND_PLL_CTRL_REG, 0x800, 0xff, {0xfc81}, 0, 0},
  657. /* Ref clock source select */
  658. {MISC_REG, 0x800, 0x4c0, {0x480}, 0, 0}
  659. };
  660. /* QSGMII - speed config seq */
  661. struct op_params qsgmii_port_speed_config_params[] = {
  662. /*
  663. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  664. * num_of_loops
  665. */
  666. /* Baud Rate */
  667. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000, {0xcc00000}, 0, 0},
  668. /* Phy Gen RX and TX */
  669. {ISOLATE_REG, 0x800, 0xff, {0x33}, 0, 0},
  670. /* Bus Width */
  671. {LOOPBACK_REG, 0x800, 0xe, {0x2}, 0, 0}
  672. };
  673. /* QSGMII - Select electrical param seq */
  674. struct op_params qsgmii_port_electrical_config_params[] = {
  675. /*
  676. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  677. * num_of_loops
  678. */
  679. /* Slew rate and emphasis */
  680. {G1_SETTINGS_0_REG, 0x800, 0x8000, {0x0}, 0, 0}
  681. };
  682. /* QSGMII - TX config seq */
  683. struct op_params qsgmii_port_tx_config_params1[] = {
  684. /*
  685. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  686. * num_of_loops
  687. */
  688. {GLUE_REG, 0x800, 0x1800, {0x800}, 0, 0},
  689. /* Sft Reset pulse */
  690. {RESET_DFE_REG, 0x800, 0x401, {0x401}, 0, 0},
  691. /* Sft Reset pulse */
  692. {RESET_DFE_REG, 0x800, 0x401, {0x0}, 0, 0},
  693. /* Lane align */
  694. {LANE_ALIGN_REG0, 0x800, 0x1000, {0x1000}, 0, 0},
  695. /* Power up PLL, RX and TX */
  696. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x70000, {0x70000}, 0, 0},
  697. /* Tx driver output idle */
  698. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x80000, {0x80000}, 0, 0}
  699. };
  700. struct op_params qsgmii_port_tx_config_params2[] = {
  701. /*
  702. * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
  703. * num_of_loops
  704. */
  705. /* Wait for PHY power up sequence to finish */
  706. {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc}, 10, 1000},
  707. /* Assert Rx Init and Tx driver output valid */
  708. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40080000, {0x40000000}, 0, 0},
  709. /* Wait for PHY power up sequence to finish */
  710. {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1}, 1, 1000},
  711. /* De-assert Rx Init */
  712. {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {0x0}, 0, 0}
  713. };
  714. /* SERDES_POWER_DOWN */
  715. struct op_params serdes_power_down_params[] = {
  716. {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0xf << 11), {(0x3 << 11)},
  717. 0, 0},
  718. {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0x7 << 16), {0}, 0, 0}
  719. };
  720. /*
  721. * hws_ctrl_serdes_rev_get
  722. *
  723. * DESCRIPTION: Get the Serdes revision number
  724. *
  725. * INPUT: config_field - Field description enum
  726. *
  727. * OUTPUT: None
  728. *
  729. * RETURN:
  730. * 8bit Serdes revision number
  731. */
  732. u8 hws_ctrl_serdes_rev_get(void)
  733. {
  734. /* for A38x-Z1 */
  735. if (sys_env_device_rev_get() == MV_88F68XX_Z1_ID)
  736. return MV_SERDES_REV_1_2;
  737. /* for A39x-Z1, A38x-A0 */
  738. return MV_SERDES_REV_2_1;
  739. }
  740. u32 hws_serdes_topology_verify(enum serdes_type serdes_type, u32 serdes_id,
  741. enum serdes_mode serdes_mode)
  742. {
  743. u32 test_result = 0;
  744. u8 serd_max_num, unit_numb;
  745. enum unit_id unit_id;
  746. if (serdes_type > RXAUI) {
  747. printf("%s: Warning: Wrong serdes type %s serdes#%d\n",
  748. __func__, serdes_type_to_string[serdes_type], serdes_id);
  749. return MV_FAIL;
  750. }
  751. unit_id = serdes_type_to_unit_info[serdes_type].serdes_unit_id;
  752. unit_numb = serdes_type_to_unit_info[serdes_type].serdes_unit_num;
  753. serd_max_num = sys_env_unit_max_num_get(unit_id);
  754. /* if didn't exceed amount of required Serdes lanes for current type */
  755. if (serdes_lane_in_use_count[unit_id][unit_numb] != 0) {
  756. /* update amount of required Serdes lanes for current type */
  757. serdes_lane_in_use_count[unit_id][unit_numb]--;
  758. /*
  759. * If reached the exact amount of required Serdes lanes for
  760. * current type
  761. */
  762. if (serdes_lane_in_use_count[unit_id][unit_numb] == 0) {
  763. if (((serdes_type <= PEX3)) &&
  764. ((serdes_mode == PEX_END_POINT_X4) ||
  765. (serdes_mode == PEX_ROOT_COMPLEX_X4))) {
  766. /* PCiex4 uses 2 SerDes */
  767. serdes_unit_count[PEX_UNIT_ID] += 2;
  768. } else {
  769. serdes_unit_count[unit_id]++;
  770. }
  771. /* test SoC unit count limitation */
  772. if (serdes_unit_count[unit_id] > serd_max_num) {
  773. test_result = WRONG_NUMBER_OF_UNITS;
  774. } else if (unit_numb >= serd_max_num) {
  775. /* test SoC unit number limitation */
  776. test_result = UNIT_NUMBER_VIOLATION;
  777. }
  778. }
  779. } else {
  780. test_result = SERDES_ALREADY_IN_USE;
  781. }
  782. if (test_result == SERDES_ALREADY_IN_USE) {
  783. printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n",
  784. __func__, serdes_id,
  785. serdes_type_to_string[serdes_type]);
  786. return MV_FAIL;
  787. } else if (test_result == WRONG_NUMBER_OF_UNITS) {
  788. printf("%s: Warning: serdes lane %d is set to type %s.\n",
  789. __func__, serdes_id,
  790. serdes_type_to_string[serdes_type]);
  791. printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n",
  792. __func__, serd_max_num);
  793. return MV_FAIL;
  794. } else if (test_result == UNIT_NUMBER_VIOLATION) {
  795. printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n",
  796. __func__, serdes_id,
  797. serdes_type_to_string[serdes_type],
  798. serd_max_num);
  799. return MV_FAIL;
  800. }
  801. return MV_OK;
  802. }
  803. void hws_serdes_xaui_topology_verify(void)
  804. {
  805. /*
  806. * If XAUI is in use - serdes_lane_in_use_count has to be = 0;
  807. * if it is not in use hast be = 4
  808. */
  809. if ((serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 0) &&
  810. (serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 4)) {
  811. printf("%s: Warning: wrong number of lanes is set to XAUI - %d\n",
  812. __func__, serdes_lane_in_use_count[XAUI_UNIT_ID][0]);
  813. printf("%s: XAUI has to be defined on 4 lanes\n", __func__);
  814. }
  815. /*
  816. * If RXAUI is in use - serdes_lane_in_use_count has to be = 0;
  817. * if it is not in use hast be = 2
  818. */
  819. if ((serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 0) &&
  820. (serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 2)) {
  821. printf("%s: Warning: wrong number of lanes is set to RXAUI - %d\n",
  822. __func__, serdes_lane_in_use_count[RXAUI_UNIT_ID][0]);
  823. printf("%s: RXAUI has to be defined on 2 lanes\n", __func__);
  824. }
  825. }
  826. int hws_serdes_seq_db_init(void)
  827. {
  828. u8 serdes_rev = hws_ctrl_serdes_rev_get();
  829. DEBUG_INIT_FULL_S("\n### serdes_seq38x_init ###\n");
  830. if (serdes_rev == MV_SERDES_REV_NA) {
  831. printf("hws_serdes_seq_db_init: serdes revision number is not supported\n");
  832. return MV_NOT_SUPPORTED;
  833. }
  834. /* SATA_PORT_0_ONLY_POWER_UP_SEQ sequence init */
  835. serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].op_params_ptr =
  836. sata_port0_power_up_params;
  837. serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].cfg_seq_size =
  838. sizeof(sata_port0_power_up_params) / sizeof(struct op_params);
  839. serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].data_arr_idx = SATA;
  840. /* SATA_PORT_1_ONLY_POWER_UP_SEQ sequence init */
  841. serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].op_params_ptr =
  842. sata_port1_power_up_params;
  843. serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].cfg_seq_size =
  844. sizeof(sata_port1_power_up_params) / sizeof(struct op_params);
  845. serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].data_arr_idx = SATA;
  846. /* SATA_POWER_UP_SEQ sequence init */
  847. serdes_seq_db[SATA_POWER_UP_SEQ].op_params_ptr =
  848. sata_and_sgmii_power_up_params;
  849. serdes_seq_db[SATA_POWER_UP_SEQ].cfg_seq_size =
  850. sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params);
  851. serdes_seq_db[SATA_POWER_UP_SEQ].data_arr_idx = SATA;
  852. /* SATA_1_5_SPEED_CONFIG_SEQ sequence init */
  853. serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].op_params_ptr =
  854. sata_and_sgmii_speed_config_params;
  855. serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].cfg_seq_size =
  856. sizeof(sata_and_sgmii_speed_config_params) /
  857. sizeof(struct op_params);
  858. serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
  859. /* SATA_3_SPEED_CONFIG_SEQ sequence init */
  860. serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].op_params_ptr =
  861. sata_and_sgmii_speed_config_params;
  862. serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].cfg_seq_size =
  863. sizeof(sata_and_sgmii_speed_config_params) /
  864. sizeof(struct op_params);
  865. serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
  866. /* SATA_6_SPEED_CONFIG_SEQ sequence init */
  867. serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].op_params_ptr =
  868. sata_and_sgmii_speed_config_params;
  869. serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].cfg_seq_size =
  870. sizeof(sata_and_sgmii_speed_config_params) /
  871. sizeof(struct op_params);
  872. serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
  873. /* SATA_ELECTRICAL_CONFIG_SEQ seq sequence init */
  874. if (serdes_rev == MV_SERDES_REV_1_2) {
  875. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  876. sata_electrical_config_serdes_rev1_params;
  877. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  878. sizeof(sata_electrical_config_serdes_rev1_params) /
  879. sizeof(struct op_params);
  880. } else {
  881. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  882. sata_electrical_config_serdes_rev2_params;
  883. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  884. sizeof(sata_electrical_config_serdes_rev2_params) /
  885. sizeof(struct op_params);
  886. }
  887. serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SATA;
  888. /* SATA_TX_CONFIG_SEQ sequence init */
  889. serdes_seq_db[SATA_TX_CONFIG_SEQ1].op_params_ptr =
  890. sata_and_sgmii_tx_config_params1;
  891. serdes_seq_db[SATA_TX_CONFIG_SEQ1].cfg_seq_size =
  892. sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params);
  893. serdes_seq_db[SATA_TX_CONFIG_SEQ1].data_arr_idx = SATA;
  894. /* SATA_PORT_0_ONLY_TX_CONFIG_SEQ sequence init */
  895. serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].op_params_ptr =
  896. sata_port0_tx_config_params;
  897. serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].cfg_seq_size =
  898. sizeof(sata_port0_tx_config_params) / sizeof(struct op_params);
  899. serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA;
  900. /* SATA_PORT_1_ONLY_TX_CONFIG_SEQ sequence init */
  901. serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].op_params_ptr =
  902. sata_port1_tx_config_params;
  903. serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].cfg_seq_size =
  904. sizeof(sata_port1_tx_config_params) / sizeof(struct op_params);
  905. serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA;
  906. /* SATA_TX_CONFIG_SEQ2 sequence init */
  907. if (serdes_rev == MV_SERDES_REV_1_2) {
  908. serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr =
  909. sata_and_sgmii_tx_config_serdes_rev1_params2;
  910. serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size =
  911. sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) /
  912. sizeof(struct op_params);
  913. } else {
  914. serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr =
  915. sata_and_sgmii_tx_config_serdes_rev2_params2;
  916. serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size =
  917. sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) /
  918. sizeof(struct op_params);
  919. }
  920. serdes_seq_db[SATA_TX_CONFIG_SEQ2].data_arr_idx = SATA;
  921. /* SGMII_POWER_UP_SEQ sequence init */
  922. serdes_seq_db[SGMII_POWER_UP_SEQ].op_params_ptr =
  923. sata_and_sgmii_power_up_params;
  924. serdes_seq_db[SGMII_POWER_UP_SEQ].cfg_seq_size =
  925. sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params);
  926. serdes_seq_db[SGMII_POWER_UP_SEQ].data_arr_idx = SGMII;
  927. /* SGMII_1_25_SPEED_CONFIG_SEQ sequence init */
  928. serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].op_params_ptr =
  929. sata_and_sgmii_speed_config_params;
  930. serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].cfg_seq_size =
  931. sizeof(sata_and_sgmii_speed_config_params) /
  932. sizeof(struct op_params);
  933. serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].data_arr_idx = SGMII;
  934. /* SGMII_3_125_SPEED_CONFIG_SEQ sequence init */
  935. serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].op_params_ptr =
  936. sata_and_sgmii_speed_config_params;
  937. serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].cfg_seq_size =
  938. sizeof(sata_and_sgmii_speed_config_params) /
  939. sizeof(struct op_params);
  940. serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].data_arr_idx = SGMII_3_125;
  941. /* SGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */
  942. if (serdes_rev == MV_SERDES_REV_1_2) {
  943. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  944. sgmii_electrical_config_serdes_rev1_params;
  945. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  946. sizeof(sgmii_electrical_config_serdes_rev1_params) /
  947. sizeof(struct op_params);
  948. } else {
  949. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  950. sgmii_electrical_config_serdes_rev2_params;
  951. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  952. sizeof(sgmii_electrical_config_serdes_rev2_params) /
  953. sizeof(struct op_params);
  954. }
  955. serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SGMII;
  956. /* SGMII_TX_CONFIG_SEQ sequence init */
  957. serdes_seq_db[SGMII_TX_CONFIG_SEQ1].op_params_ptr =
  958. sata_and_sgmii_tx_config_params1;
  959. serdes_seq_db[SGMII_TX_CONFIG_SEQ1].cfg_seq_size =
  960. sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params);
  961. serdes_seq_db[SGMII_TX_CONFIG_SEQ1].data_arr_idx = SGMII;
  962. /* SGMII_TX_CONFIG_SEQ sequence init */
  963. if (serdes_rev == MV_SERDES_REV_1_2) {
  964. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr =
  965. sata_and_sgmii_tx_config_serdes_rev1_params2;
  966. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size =
  967. sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) /
  968. sizeof(struct op_params);
  969. } else {
  970. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr =
  971. sata_and_sgmii_tx_config_serdes_rev2_params2;
  972. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size =
  973. sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) /
  974. sizeof(struct op_params);
  975. }
  976. serdes_seq_db[SGMII_TX_CONFIG_SEQ2].data_arr_idx = SGMII;
  977. /* PEX_POWER_UP_SEQ sequence init */
  978. if (serdes_rev == MV_SERDES_REV_1_2) {
  979. serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr =
  980. pex_and_usb3_power_up_serdes_rev1_params;
  981. serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size =
  982. sizeof(pex_and_usb3_power_up_serdes_rev1_params) /
  983. sizeof(struct op_params);
  984. } else {
  985. serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr =
  986. pex_and_usb3_power_up_serdes_rev2_params;
  987. serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size =
  988. sizeof(pex_and_usb3_power_up_serdes_rev2_params) /
  989. sizeof(struct op_params);
  990. }
  991. serdes_seq_db[PEX_POWER_UP_SEQ].data_arr_idx = PEX;
  992. /* PEX_2_5_SPEED_CONFIG_SEQ sequence init */
  993. serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].op_params_ptr =
  994. pex_and_usb3_speed_config_params;
  995. serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].cfg_seq_size =
  996. sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
  997. serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].data_arr_idx =
  998. PEXSERDES_SPEED_2_5_GBPS;
  999. /* PEX_5_SPEED_CONFIG_SEQ sequence init */
  1000. serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].op_params_ptr =
  1001. pex_and_usb3_speed_config_params;
  1002. serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].cfg_seq_size =
  1003. sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
  1004. serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].data_arr_idx =
  1005. PEXSERDES_SPEED_5_GBPS;
  1006. /* PEX_ELECTRICAL_CONFIG_SEQ seq sequence init */
  1007. if (serdes_rev == MV_SERDES_REV_1_2) {
  1008. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1009. pex_electrical_config_serdes_rev1_params;
  1010. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1011. sizeof(pex_electrical_config_serdes_rev1_params) /
  1012. sizeof(struct op_params);
  1013. } else {
  1014. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1015. pex_electrical_config_serdes_rev2_params;
  1016. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1017. sizeof(pex_electrical_config_serdes_rev2_params) /
  1018. sizeof(struct op_params);
  1019. }
  1020. serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].data_arr_idx = PEX;
  1021. /* PEX_TX_CONFIG_SEQ1 sequence init */
  1022. serdes_seq_db[PEX_TX_CONFIG_SEQ1].op_params_ptr =
  1023. pex_and_usb3_tx_config_params1;
  1024. serdes_seq_db[PEX_TX_CONFIG_SEQ1].cfg_seq_size =
  1025. sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params);
  1026. serdes_seq_db[PEX_TX_CONFIG_SEQ1].data_arr_idx = PEX;
  1027. /* PEX_TX_CONFIG_SEQ2 sequence init */
  1028. serdes_seq_db[PEX_TX_CONFIG_SEQ2].op_params_ptr =
  1029. pex_and_usb3_tx_config_params2;
  1030. serdes_seq_db[PEX_TX_CONFIG_SEQ2].cfg_seq_size =
  1031. sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params);
  1032. serdes_seq_db[PEX_TX_CONFIG_SEQ2].data_arr_idx = PEX;
  1033. /* PEX_TX_CONFIG_SEQ3 sequence init */
  1034. serdes_seq_db[PEX_TX_CONFIG_SEQ3].op_params_ptr =
  1035. pex_and_usb3_tx_config_params3;
  1036. serdes_seq_db[PEX_TX_CONFIG_SEQ3].cfg_seq_size =
  1037. sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params);
  1038. serdes_seq_db[PEX_TX_CONFIG_SEQ3].data_arr_idx = PEX;
  1039. /* PEX_BY_4_CONFIG_SEQ sequence init */
  1040. serdes_seq_db[PEX_BY_4_CONFIG_SEQ].op_params_ptr =
  1041. pex_by4_config_params;
  1042. serdes_seq_db[PEX_BY_4_CONFIG_SEQ].cfg_seq_size =
  1043. sizeof(pex_by4_config_params) / sizeof(struct op_params);
  1044. serdes_seq_db[PEX_BY_4_CONFIG_SEQ].data_arr_idx = PEX;
  1045. /* PEX_CONFIG_REF_CLOCK_25MHZ_SEQ sequence init */
  1046. serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].op_params_ptr =
  1047. pex_config_ref_clock25_m_hz;
  1048. serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].cfg_seq_size =
  1049. sizeof(pex_config_ref_clock25_m_hz) / sizeof(struct op_params);
  1050. serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].data_arr_idx = PEX;
  1051. /* PEX_ELECTRICAL_CONFIG_REF_CLOCK_40MHZ_SEQ sequence init */
  1052. serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].op_params_ptr =
  1053. pex_config_ref_clock40_m_hz;
  1054. serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].cfg_seq_size =
  1055. sizeof(pex_config_ref_clock40_m_hz) / sizeof(struct op_params);
  1056. serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].data_arr_idx = PEX;
  1057. /* PEX_CONFIG_REF_CLOCK_100MHZ_SEQ sequence init */
  1058. serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].op_params_ptr =
  1059. pex_config_ref_clock100_m_hz;
  1060. serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].cfg_seq_size =
  1061. sizeof(pex_config_ref_clock100_m_hz) / sizeof(struct op_params);
  1062. serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].data_arr_idx = PEX;
  1063. /* USB3_POWER_UP_SEQ sequence init */
  1064. if (serdes_rev == MV_SERDES_REV_1_2) {
  1065. serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr =
  1066. pex_and_usb3_power_up_serdes_rev1_params;
  1067. serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size =
  1068. sizeof(pex_and_usb3_power_up_serdes_rev1_params) /
  1069. sizeof(struct op_params);
  1070. } else {
  1071. serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr =
  1072. pex_and_usb3_power_up_serdes_rev2_params;
  1073. serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size =
  1074. sizeof(pex_and_usb3_power_up_serdes_rev2_params) /
  1075. sizeof(struct op_params);
  1076. }
  1077. serdes_seq_db[USB3_POWER_UP_SEQ].data_arr_idx = USB3;
  1078. /* USB3_HOST_SPEED_CONFIG_SEQ sequence init */
  1079. serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].op_params_ptr =
  1080. pex_and_usb3_speed_config_params;
  1081. serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].cfg_seq_size =
  1082. sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
  1083. serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].data_arr_idx =
  1084. USB3SERDES_SPEED_5_GBPS_HOST;
  1085. /* USB3_DEVICE_SPEED_CONFIG_SEQ sequence init */
  1086. serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].op_params_ptr =
  1087. pex_and_usb3_speed_config_params;
  1088. serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].cfg_seq_size =
  1089. sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
  1090. serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].data_arr_idx =
  1091. USB3SERDES_SPEED_5_GBPS_DEVICE;
  1092. /* USB3_ELECTRICAL_CONFIG_SEQ seq sequence init */
  1093. if (serdes_rev == MV_SERDES_REV_1_2) {
  1094. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1095. usb3_electrical_config_serdes_rev1_params;
  1096. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1097. sizeof(usb3_electrical_config_serdes_rev1_params) /
  1098. sizeof(struct op_params);
  1099. } else {
  1100. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1101. usb3_electrical_config_serdes_rev2_params;
  1102. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1103. sizeof(usb3_electrical_config_serdes_rev2_params) /
  1104. sizeof(struct op_params);
  1105. }
  1106. serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = USB3;
  1107. /* USB3_TX_CONFIG_SEQ sequence init */
  1108. serdes_seq_db[USB3_TX_CONFIG_SEQ1].op_params_ptr =
  1109. pex_and_usb3_tx_config_params1;
  1110. serdes_seq_db[USB3_TX_CONFIG_SEQ1].cfg_seq_size =
  1111. sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params);
  1112. serdes_seq_db[USB3_TX_CONFIG_SEQ1].data_arr_idx = USB3;
  1113. /* USB3_TX_CONFIG_SEQ sequence init */
  1114. serdes_seq_db[USB3_TX_CONFIG_SEQ2].op_params_ptr =
  1115. pex_and_usb3_tx_config_params2;
  1116. serdes_seq_db[USB3_TX_CONFIG_SEQ2].cfg_seq_size =
  1117. sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params);
  1118. serdes_seq_db[USB3_TX_CONFIG_SEQ2].data_arr_idx = USB3;
  1119. /* USB3_TX_CONFIG_SEQ sequence init */
  1120. serdes_seq_db[USB3_TX_CONFIG_SEQ3].op_params_ptr =
  1121. pex_and_usb3_tx_config_params3;
  1122. serdes_seq_db[USB3_TX_CONFIG_SEQ3].cfg_seq_size =
  1123. sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params);
  1124. serdes_seq_db[USB3_TX_CONFIG_SEQ3].data_arr_idx = USB3;
  1125. /* USB2_POWER_UP_SEQ sequence init */
  1126. serdes_seq_db[USB2_POWER_UP_SEQ].op_params_ptr = usb2_power_up_params;
  1127. serdes_seq_db[USB2_POWER_UP_SEQ].cfg_seq_size =
  1128. sizeof(usb2_power_up_params) / sizeof(struct op_params);
  1129. serdes_seq_db[USB2_POWER_UP_SEQ].data_arr_idx = 0;
  1130. /* USB3_DEVICE_CONFIG_SEQ sequence init */
  1131. serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].op_params_ptr =
  1132. usb3_device_config_params;
  1133. serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].cfg_seq_size =
  1134. sizeof(usb3_device_config_params) / sizeof(struct op_params);
  1135. serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].data_arr_idx = 0; /* Not relevant */
  1136. /* SERDES_POWER_DOWN_SEQ sequence init */
  1137. serdes_seq_db[SERDES_POWER_DOWN_SEQ].op_params_ptr =
  1138. serdes_power_down_params;
  1139. serdes_seq_db[SERDES_POWER_DOWN_SEQ].cfg_seq_size =
  1140. sizeof(serdes_power_down_params) /
  1141. sizeof(struct op_params);
  1142. serdes_seq_db[SERDES_POWER_DOWN_SEQ].data_arr_idx = FIRST_CELL;
  1143. if (serdes_rev == MV_SERDES_REV_2_1) {
  1144. /* QSGMII_POWER_UP_SEQ sequence init */
  1145. serdes_seq_db[QSGMII_POWER_UP_SEQ].op_params_ptr =
  1146. qsgmii_port_power_up_params;
  1147. serdes_seq_db[QSGMII_POWER_UP_SEQ].cfg_seq_size =
  1148. sizeof(qsgmii_port_power_up_params) /
  1149. sizeof(struct op_params);
  1150. serdes_seq_db[QSGMII_POWER_UP_SEQ].data_arr_idx =
  1151. QSGMII_SEQ_IDX;
  1152. /* QSGMII_5_SPEED_CONFIG_SEQ sequence init */
  1153. serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].op_params_ptr =
  1154. qsgmii_port_speed_config_params;
  1155. serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].cfg_seq_size =
  1156. sizeof(qsgmii_port_speed_config_params) /
  1157. sizeof(struct op_params);
  1158. serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].data_arr_idx =
  1159. QSGMII_SEQ_IDX;
  1160. /* QSGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */
  1161. serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
  1162. qsgmii_port_electrical_config_params;
  1163. serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
  1164. sizeof(qsgmii_port_electrical_config_params) /
  1165. sizeof(struct op_params);
  1166. serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx =
  1167. QSGMII_SEQ_IDX;
  1168. /* QSGMII_TX_CONFIG_SEQ sequence init */
  1169. serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].op_params_ptr =
  1170. qsgmii_port_tx_config_params1;
  1171. serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].cfg_seq_size =
  1172. sizeof(qsgmii_port_tx_config_params1) /
  1173. sizeof(struct op_params);
  1174. serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].data_arr_idx =
  1175. QSGMII_SEQ_IDX;
  1176. /* QSGMII_TX_CONFIG_SEQ sequence init */
  1177. serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].op_params_ptr =
  1178. qsgmii_port_tx_config_params2;
  1179. serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].cfg_seq_size =
  1180. sizeof(qsgmii_port_tx_config_params2) /
  1181. sizeof(struct op_params);
  1182. serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].data_arr_idx =
  1183. QSGMII_SEQ_IDX;
  1184. }
  1185. return MV_OK;
  1186. }
  1187. enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
  1188. enum serdes_speed baud_rate)
  1189. {
  1190. enum serdes_seq seq_id = SERDES_LAST_SEQ;
  1191. DEBUG_INIT_FULL_S("\n### serdes_type_and_speed_to_speed_seq ###\n");
  1192. switch (serdes_type) {
  1193. case PEX0:
  1194. case PEX1:
  1195. case PEX2:
  1196. case PEX3:
  1197. if (baud_rate == SERDES_SPEED_2_5_GBPS)
  1198. seq_id = PEX_2_5_SPEED_CONFIG_SEQ;
  1199. else if (baud_rate == SERDES_SPEED_5_GBPS)
  1200. seq_id = PEX_5_SPEED_CONFIG_SEQ;
  1201. break;
  1202. case USB3_HOST0:
  1203. case USB3_HOST1:
  1204. if (baud_rate == SERDES_SPEED_5_GBPS)
  1205. seq_id = USB3_HOST_SPEED_CONFIG_SEQ;
  1206. break;
  1207. case USB3_DEVICE:
  1208. if (baud_rate == SERDES_SPEED_5_GBPS)
  1209. seq_id = USB3_DEVICE_SPEED_CONFIG_SEQ;
  1210. break;
  1211. case SATA0:
  1212. case SATA1:
  1213. case SATA2:
  1214. case SATA3:
  1215. if (baud_rate == SERDES_SPEED_1_5_GBPS)
  1216. seq_id = SATA_1_5_SPEED_CONFIG_SEQ;
  1217. else if (baud_rate == SERDES_SPEED_3_GBPS)
  1218. seq_id = SATA_3_SPEED_CONFIG_SEQ;
  1219. else if (baud_rate == SERDES_SPEED_6_GBPS)
  1220. seq_id = SATA_6_SPEED_CONFIG_SEQ;
  1221. break;
  1222. case SGMII0:
  1223. case SGMII1:
  1224. case SGMII2:
  1225. if (baud_rate == SERDES_SPEED_1_25_GBPS)
  1226. seq_id = SGMII_1_25_SPEED_CONFIG_SEQ;
  1227. else if (baud_rate == SERDES_SPEED_3_125_GBPS)
  1228. seq_id = SGMII_3_125_SPEED_CONFIG_SEQ;
  1229. break;
  1230. case QSGMII:
  1231. seq_id = QSGMII_5_SPEED_CONFIG_SEQ;
  1232. break;
  1233. default:
  1234. return SERDES_LAST_SEQ;
  1235. }
  1236. return seq_id;
  1237. }
  1238. static void print_topology_details(const struct serdes_map *serdes_map,
  1239. u8 count)
  1240. {
  1241. u32 lane_num;
  1242. DEBUG_INIT_S("board SerDes lanes topology details:\n");
  1243. DEBUG_INIT_S(" | Lane # | Speed | Type |\n");
  1244. DEBUG_INIT_S(" --------------------------------\n");
  1245. for (lane_num = 0; lane_num < count; lane_num++) {
  1246. if (serdes_map[lane_num].serdes_type == DEFAULT_SERDES)
  1247. continue;
  1248. DEBUG_INIT_S(" | ");
  1249. DEBUG_INIT_D(hws_get_physical_serdes_num(lane_num), 1);
  1250. DEBUG_INIT_S(" | ");
  1251. DEBUG_INIT_D(serdes_map[lane_num].serdes_speed, 2);
  1252. DEBUG_INIT_S(" | ");
  1253. DEBUG_INIT_S((char *)
  1254. serdes_type_to_string[serdes_map[lane_num].
  1255. serdes_type]);
  1256. DEBUG_INIT_S("\t|\n");
  1257. }
  1258. DEBUG_INIT_S(" --------------------------------\n");
  1259. }
  1260. int hws_pre_serdes_init_config(void)
  1261. {
  1262. u32 data;
  1263. /*
  1264. * Configure Core PLL
  1265. */
  1266. /*
  1267. * set PLL parameters
  1268. * bits[2:0] =0x3 (Core-PLL Kdiv)
  1269. * bits[20:12]=0x9f (Core-PLL Ndiv)
  1270. * bits[24:21]=0x7(Core-PLL VCO Band)
  1271. * bits[28:25]=0x1(Core-PLL Rlf)
  1272. * bits[31:29]=0x2(Core-PLL charge-pump adjust)
  1273. */
  1274. reg_write(CORE_PLL_PARAMETERS_REG, 0x42e9f003);
  1275. /* Enable PLL Configuration */
  1276. data = reg_read(CORE_PLL_CONFIG_REG);
  1277. data = SET_BIT(data, 9);
  1278. reg_write(CORE_PLL_CONFIG_REG, data);
  1279. return MV_OK;
  1280. }
  1281. int serdes_phy_config(void)
  1282. {
  1283. struct serdes_map *serdes_map;
  1284. u8 serdes_count;
  1285. DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n");
  1286. DEBUG_INIT_S("High speed PHY - Version: ");
  1287. DEBUG_INIT_S(SERDES_VERSION);
  1288. DEBUG_INIT_S("\n");
  1289. /* Init serdes sequences DB */
  1290. if (hws_serdes_seq_init() != MV_OK) {
  1291. printf("hws_ctrl_high_speed_serdes_phy_config: Error: Serdes initialization fail\n");
  1292. return MV_FAIL;
  1293. }
  1294. /* Board topology load */
  1295. DEBUG_INIT_FULL_S
  1296. ("ctrl_high_speed_serdes_phy_config: Loading board topology..\n");
  1297. CHECK_STATUS(hws_board_topology_load(&serdes_map, &serdes_count));
  1298. if (serdes_count > hws_serdes_get_max_lane()) {
  1299. printf("Error: too many serdes lanes specified by board\n");
  1300. return MV_FAIL;
  1301. }
  1302. /* print topology */
  1303. print_topology_details(serdes_map, serdes_count);
  1304. CHECK_STATUS(hws_pre_serdes_init_config());
  1305. /* Power-Up sequence */
  1306. DEBUG_INIT_FULL_S
  1307. ("ctrl_high_speed_serdes_phy_config: Starting serdes power up sequence\n");
  1308. CHECK_STATUS(hws_power_up_serdes_lanes(serdes_map, serdes_count));
  1309. DEBUG_INIT_FULL_S
  1310. ("\n### ctrl_high_speed_serdes_phy_config ended successfully ###\n");
  1311. DEBUG_INIT_S(ENDED_OK);
  1312. return MV_OK;
  1313. }
  1314. int serdes_polarity_config(u32 serdes_num, int is_rx)
  1315. {
  1316. u32 data;
  1317. u32 reg_addr;
  1318. u8 bit_off = (is_rx) ? 11 : 10;
  1319. reg_addr = SERDES_REGS_LANE_BASE_OFFSET(serdes_num) + SYNC_PATTERN_REG;
  1320. data = reg_read(reg_addr);
  1321. data = SET_BIT(data, bit_off);
  1322. reg_write(reg_addr, data);
  1323. return MV_OK;
  1324. }
  1325. int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count)
  1326. {
  1327. u32 serdes_id, serdes_lane_num;
  1328. enum ref_clock ref_clock;
  1329. enum serdes_type serdes_type;
  1330. enum serdes_speed serdes_speed;
  1331. enum serdes_mode serdes_mode;
  1332. int serdes_rx_polarity_swap;
  1333. int serdes_tx_polarity_swap;
  1334. int is_pex_enabled = 0;
  1335. /*
  1336. * is_pex_enabled:
  1337. * Flag which indicates that one of the Serdes is of PEX.
  1338. * In this case, PEX unit will be initialized after Serdes power-up
  1339. */
  1340. DEBUG_INIT_FULL_S("\n### hws_power_up_serdes_lanes ###\n");
  1341. /* COMMON PHYS SELECTORS register configuration */
  1342. DEBUG_INIT_FULL_S
  1343. ("hws_power_up_serdes_lanes: Updating COMMON PHYS SELECTORS reg\n");
  1344. CHECK_STATUS(hws_update_serdes_phy_selectors(serdes_map, count));
  1345. /* per Serdes Power Up */
  1346. for (serdes_id = 0; serdes_id < count; serdes_id++) {
  1347. DEBUG_INIT_FULL_S
  1348. ("calling serdes_power_up_ctrl: serdes lane number ");
  1349. DEBUG_INIT_FULL_D_10(serdes_lane_num, 1);
  1350. DEBUG_INIT_FULL_S("\n");
  1351. serdes_lane_num = hws_get_physical_serdes_num(serdes_id);
  1352. serdes_type = serdes_map[serdes_id].serdes_type;
  1353. serdes_speed = serdes_map[serdes_id].serdes_speed;
  1354. serdes_mode = serdes_map[serdes_id].serdes_mode;
  1355. serdes_rx_polarity_swap = serdes_map[serdes_id].swap_rx;
  1356. serdes_tx_polarity_swap = serdes_map[serdes_id].swap_tx;
  1357. /* serdes lane is not in use */
  1358. if (serdes_type == DEFAULT_SERDES)
  1359. continue;
  1360. else if (serdes_type <= PEX3) /* PEX type */
  1361. is_pex_enabled = 1;
  1362. ref_clock = hws_serdes_get_ref_clock_val(serdes_type);
  1363. if (ref_clock == REF_CLOCK_UNSUPPORTED) {
  1364. DEBUG_INIT_S
  1365. ("hws_power_up_serdes_lanes: unsupported ref clock\n");
  1366. return MV_NOT_SUPPORTED;
  1367. }
  1368. CHECK_STATUS(serdes_power_up_ctrl(serdes_lane_num,
  1369. 1,
  1370. serdes_type,
  1371. serdes_speed,
  1372. serdes_mode, ref_clock));
  1373. /* RX Polarity config */
  1374. if (serdes_rx_polarity_swap)
  1375. CHECK_STATUS(serdes_polarity_config
  1376. (serdes_lane_num, 1));
  1377. /* TX Polarity config */
  1378. if (serdes_tx_polarity_swap)
  1379. CHECK_STATUS(serdes_polarity_config
  1380. (serdes_lane_num, 0));
  1381. }
  1382. if (is_pex_enabled) {
  1383. /* Set PEX_TX_CONFIG_SEQ sequence for PEXx4 mode.
  1384. After finish the Power_up sequence for all lanes,
  1385. the lanes should be released from reset state. */
  1386. CHECK_STATUS(hws_pex_tx_config_seq(serdes_map, count));
  1387. /* PEX configuration */
  1388. CHECK_STATUS(hws_pex_config(serdes_map, count));
  1389. }
  1390. /* USB2 configuration */
  1391. DEBUG_INIT_FULL_S("hws_power_up_serdes_lanes: init USB2 Phys\n");
  1392. CHECK_STATUS(mv_seq_exec(0 /* not relevant */ , USB2_POWER_UP_SEQ));
  1393. DEBUG_INIT_FULL_S
  1394. ("### hws_power_up_serdes_lanes ended successfully ###\n");
  1395. return MV_OK;
  1396. }
  1397. int ctrl_high_speed_serdes_phy_config(void)
  1398. {
  1399. return hws_ctrl_high_speed_serdes_phy_config();
  1400. }
  1401. static int serdes_pex_usb3_pipe_delay_w_a(u32 serdes_num, u8 serdes_type)
  1402. {
  1403. u32 reg_data;
  1404. /* WA for A380 Z1 relevant for lanes 3,4,5 only */
  1405. if (serdes_num >= 3) {
  1406. reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
  1407. /* set delay on pipe -
  1408. * When lane 3 is connected to a MAC of Pex -> set bit 7 to 1.
  1409. * When lane 3 is connected to a MAC of USB3 -> set bit 7 to 0.
  1410. * When lane 4 is connected to a MAC of Pex -> set bit 8 to 1.
  1411. * When lane 4 is connected to a MAC of USB3 -> set bit 8 to 0.
  1412. * When lane 5 is connected to a MAC of Pex -> set bit 8 to 1.
  1413. * When lane 5 is connected to a MAC of USB3 -> set bit 8 to 0.
  1414. */
  1415. if (serdes_type == PEX)
  1416. reg_data |= 1 << (7 + (serdes_num - 3));
  1417. if (serdes_type == USB3) {
  1418. /* USB3 */
  1419. reg_data &= ~(1 << (7 + (serdes_num - 3)));
  1420. }
  1421. reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data);
  1422. }
  1423. return MV_OK;
  1424. }
  1425. /*
  1426. * hws_serdes_pex_ref_clock_satr_get -
  1427. *
  1428. * DESCRIPTION: Get the reference clock value from DEVICE_SAMPLE_AT_RESET1_REG
  1429. * and check:
  1430. * bit[2] for PEX#0, bit[3] for PEX#1, bit[30] for PEX#2, bit[31]
  1431. * for PEX#3.
  1432. * If bit=0 --> REF_CLOCK_100MHz
  1433. * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=0
  1434. * --> REF_CLOCK_25MHz
  1435. * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=1
  1436. * --> REF_CLOCK_40MHz
  1437. *
  1438. * INPUT: serdes_type - Type of Serdes
  1439. *
  1440. * OUTPUT: pex_satr - Return the REF_CLOCK value:
  1441. * REF_CLOCK_25MHz, REF_CLOCK_40MHz or REF_CLOCK_100MHz
  1442. *
  1443. * RETURNS: MV_OK - for success
  1444. * MV_BAD_PARAM - for fail
  1445. */
  1446. int hws_serdes_pex_ref_clock_satr_get(enum serdes_type serdes_type, u32 *pex_satr)
  1447. {
  1448. u32 data, reg_satr1;
  1449. reg_satr1 = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);
  1450. switch (serdes_type) {
  1451. case PEX0:
  1452. data = REF_CLK_SELECTOR_VAL_PEX0(reg_satr1);
  1453. break;
  1454. case PEX1:
  1455. data = REF_CLK_SELECTOR_VAL_PEX1(reg_satr1);
  1456. break;
  1457. case PEX2:
  1458. data = REF_CLK_SELECTOR_VAL_PEX2(reg_satr1);
  1459. break;
  1460. case PEX3:
  1461. data = REF_CLK_SELECTOR_VAL_PEX3(reg_satr1);
  1462. break;
  1463. default:
  1464. printf("%s: Error: SerDes type %d is not supported\n",
  1465. __func__, serdes_type);
  1466. return MV_BAD_PARAM;
  1467. }
  1468. *pex_satr = data;
  1469. return MV_OK;
  1470. }
  1471. u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type)
  1472. {
  1473. u32 pex_satr;
  1474. enum ref_clock ref_clock;
  1475. DEBUG_INIT_FULL_S("\n### hws_serdes_get_ref_clock_val ###\n");
  1476. if (serdes_type >= LAST_SERDES_TYPE)
  1477. return REF_CLOCK_UNSUPPORTED;
  1478. /* read ref clock from S@R */
  1479. ref_clock = hws_serdes_silicon_ref_clock_get();
  1480. if (serdes_type > PEX3) {
  1481. /* for all Serdes types but PCIe */
  1482. return ref_clock;
  1483. }
  1484. /* for PCIe, need also to check PCIe S@R */
  1485. CHECK_STATUS(hws_serdes_pex_ref_clock_satr_get
  1486. (serdes_type, &pex_satr));
  1487. if (pex_satr == 0) {
  1488. return REF_CLOCK_100MHZ;
  1489. } else if (pex_satr == 1) {
  1490. /* value of 1 means we can use ref clock from SoC (as other Serdes types) */
  1491. return ref_clock;
  1492. } else {
  1493. printf
  1494. ("%s: Error: REF_CLK_SELECTOR_VAL for SerDes type %d is wrong\n",
  1495. __func__, serdes_type);
  1496. return REF_CLOCK_UNSUPPORTED;
  1497. }
  1498. }
  1499. int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
  1500. enum serdes_type serdes_type,
  1501. enum serdes_speed baud_rate,
  1502. enum serdes_mode serdes_mode, enum ref_clock ref_clock)
  1503. {
  1504. u32 sata_idx, pex_idx, sata_port;
  1505. enum serdes_seq speed_seq_id;
  1506. u32 reg_data;
  1507. int is_pex_by1;
  1508. DEBUG_INIT_FULL_S("\n### serdes_power_up_ctrl ###\n");
  1509. if (serdes_power_up == 1) { /* Serdes power up */
  1510. DEBUG_INIT_FULL_S
  1511. ("serdes_power_up_ctrl: executing power up.. ");
  1512. DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 2);
  1513. DEBUG_INIT_FULL_C("serdes type = ", serdes_type, 2);
  1514. DEBUG_INIT_FULL_S("Going access 1");
  1515. /* Getting the Speed Select sequence id */
  1516. speed_seq_id =
  1517. serdes_type_and_speed_to_speed_seq(serdes_type,
  1518. baud_rate);
  1519. if (speed_seq_id == SERDES_LAST_SEQ) {
  1520. printf
  1521. ("serdes_power_up_ctrl: serdes type %d and speed %d are not supported together\n",
  1522. serdes_type, baud_rate);
  1523. return MV_BAD_PARAM;
  1524. }
  1525. /* Executing power up, ref clock set, speed config and TX config */
  1526. switch (serdes_type) {
  1527. case PEX0:
  1528. case PEX1:
  1529. case PEX2:
  1530. case PEX3:
  1531. if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) {
  1532. CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a
  1533. (serdes_num, PEX));
  1534. }
  1535. is_pex_by1 = (serdes_mode == PEX_ROOT_COMPLEX_X1) ||
  1536. (serdes_mode == PEX_END_POINT_X1);
  1537. pex_idx = serdes_type - PEX0;
  1538. if ((is_pex_by1 == 1) || (serdes_type == PEX0)) {
  1539. /* For PEX by 4, init only the PEX 0 */
  1540. reg_data = reg_read(SOC_CONTROL_REG1);
  1541. if (is_pex_by1 == 1)
  1542. reg_data |= 0x4000;
  1543. else
  1544. reg_data &= ~0x4000;
  1545. reg_write(SOC_CONTROL_REG1, reg_data);
  1546. reg_data =
  1547. reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
  1548. 0x6c));
  1549. reg_data &= ~0x3f0;
  1550. if (is_pex_by1 == 1)
  1551. reg_data |= 0x10;
  1552. else
  1553. reg_data |= 0x40;
  1554. reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
  1555. reg_data);
  1556. reg_data =
  1557. reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
  1558. 0x6c));
  1559. reg_data &= ~0xf;
  1560. reg_data |= 0x2;
  1561. reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
  1562. reg_data);
  1563. reg_data =
  1564. reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
  1565. 0x70));
  1566. reg_data &= ~0x40;
  1567. reg_data |= 0x40;
  1568. reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
  1569. reg_data);
  1570. }
  1571. CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));
  1572. if (is_pex_by1 == 0) {
  1573. /*
  1574. * for PEX by 4 - use the PEX index as the
  1575. * seq array index
  1576. */
  1577. serdes_seq_db[PEX_BY_4_CONFIG_SEQ].
  1578. data_arr_idx = pex_idx;
  1579. CHECK_STATUS(mv_seq_exec
  1580. (serdes_num, PEX_BY_4_CONFIG_SEQ));
  1581. }
  1582. CHECK_STATUS(hws_ref_clock_set
  1583. (serdes_num, serdes_type, ref_clock));
  1584. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1585. CHECK_STATUS(mv_seq_exec
  1586. (serdes_num, PEX_ELECTRICAL_CONFIG_SEQ));
  1587. if (is_pex_by1 == 1) {
  1588. CHECK_STATUS(mv_seq_exec
  1589. (serdes_num, PEX_TX_CONFIG_SEQ2));
  1590. CHECK_STATUS(mv_seq_exec
  1591. (serdes_num, PEX_TX_CONFIG_SEQ3));
  1592. CHECK_STATUS(mv_seq_exec
  1593. (serdes_num, PEX_TX_CONFIG_SEQ1));
  1594. }
  1595. udelay(20);
  1596. break;
  1597. case USB3_HOST0:
  1598. case USB3_HOST1:
  1599. case USB3_DEVICE:
  1600. if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) {
  1601. CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a
  1602. (serdes_num, USB3));
  1603. }
  1604. CHECK_STATUS(mv_seq_exec
  1605. (serdes_num, USB3_POWER_UP_SEQ));
  1606. CHECK_STATUS(hws_ref_clock_set
  1607. (serdes_num, serdes_type, ref_clock));
  1608. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1609. if (serdes_type == USB3_DEVICE) {
  1610. CHECK_STATUS(mv_seq_exec
  1611. (serdes_num,
  1612. USB3_DEVICE_CONFIG_SEQ));
  1613. }
  1614. CHECK_STATUS(mv_seq_exec
  1615. (serdes_num, USB3_ELECTRICAL_CONFIG_SEQ));
  1616. CHECK_STATUS(mv_seq_exec
  1617. (serdes_num, USB3_TX_CONFIG_SEQ1));
  1618. CHECK_STATUS(mv_seq_exec
  1619. (serdes_num, USB3_TX_CONFIG_SEQ2));
  1620. CHECK_STATUS(mv_seq_exec
  1621. (serdes_num, USB3_TX_CONFIG_SEQ3));
  1622. udelay(10000);
  1623. break;
  1624. case SATA0:
  1625. case SATA1:
  1626. case SATA2:
  1627. case SATA3:
  1628. sata_idx = ((serdes_type == SATA0) ||
  1629. (serdes_type == SATA1)) ? 0 : 1;
  1630. sata_port = ((serdes_type == SATA0) ||
  1631. (serdes_type == SATA2)) ? 0 : 1;
  1632. CHECK_STATUS(mv_seq_exec
  1633. (sata_idx, (sata_port == 0) ?
  1634. SATA_PORT_0_ONLY_POWER_UP_SEQ :
  1635. SATA_PORT_1_ONLY_POWER_UP_SEQ));
  1636. CHECK_STATUS(mv_seq_exec
  1637. (serdes_num, SATA_POWER_UP_SEQ));
  1638. CHECK_STATUS(hws_ref_clock_set
  1639. (serdes_num, serdes_type, ref_clock));
  1640. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1641. CHECK_STATUS(mv_seq_exec
  1642. (serdes_num, SATA_ELECTRICAL_CONFIG_SEQ));
  1643. CHECK_STATUS(mv_seq_exec
  1644. (serdes_num, SATA_TX_CONFIG_SEQ1));
  1645. CHECK_STATUS(mv_seq_exec
  1646. (sata_idx, (sata_port == 0) ?
  1647. SATA_PORT_0_ONLY_TX_CONFIG_SEQ :
  1648. SATA_PORT_1_ONLY_TX_CONFIG_SEQ));
  1649. CHECK_STATUS(mv_seq_exec
  1650. (serdes_num, SATA_TX_CONFIG_SEQ2));
  1651. udelay(10000);
  1652. break;
  1653. case SGMII0:
  1654. case SGMII1:
  1655. case SGMII2:
  1656. CHECK_STATUS(mv_seq_exec
  1657. (serdes_num, SGMII_POWER_UP_SEQ));
  1658. CHECK_STATUS(hws_ref_clock_set
  1659. (serdes_num, serdes_type, ref_clock));
  1660. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1661. CHECK_STATUS(mv_seq_exec
  1662. (serdes_num, SGMII_ELECTRICAL_CONFIG_SEQ));
  1663. CHECK_STATUS(mv_seq_exec
  1664. (serdes_num, SGMII_TX_CONFIG_SEQ1));
  1665. CHECK_STATUS(mv_seq_exec
  1666. (serdes_num, SGMII_TX_CONFIG_SEQ2));
  1667. /* GBE configuration */
  1668. reg_data = reg_read(GBE_CONFIGURATION_REG);
  1669. /* write the SGMII index */
  1670. reg_data |= 0x1 << (serdes_type - SGMII0);
  1671. reg_write(GBE_CONFIGURATION_REG, reg_data);
  1672. break;
  1673. case QSGMII:
  1674. if (hws_ctrl_serdes_rev_get() < MV_SERDES_REV_2_1)
  1675. return MV_NOT_SUPPORTED;
  1676. CHECK_STATUS(mv_seq_exec
  1677. (serdes_num, QSGMII_POWER_UP_SEQ));
  1678. CHECK_STATUS(hws_ref_clock_set
  1679. (serdes_num, serdes_type, ref_clock));
  1680. CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
  1681. CHECK_STATUS(mv_seq_exec
  1682. (serdes_num,
  1683. QSGMII_ELECTRICAL_CONFIG_SEQ));
  1684. CHECK_STATUS(mv_seq_exec
  1685. (serdes_num, QSGMII_TX_CONFIG_SEQ1));
  1686. CHECK_STATUS(mv_seq_exec
  1687. (serdes_num, QSGMII_TX_CONFIG_SEQ2));
  1688. break;
  1689. case SGMII3:
  1690. case XAUI:
  1691. case RXAUI:
  1692. CHECK_STATUS(serdes_power_up_ctrl_ext
  1693. (serdes_num, serdes_power_up, serdes_type,
  1694. baud_rate, serdes_mode, ref_clock));
  1695. break;
  1696. default:
  1697. DEBUG_INIT_S
  1698. ("serdes_power_up_ctrl: bad serdes_type parameter\n");
  1699. return MV_BAD_PARAM;
  1700. }
  1701. } else { /* Serdes power down */
  1702. DEBUG_INIT_FULL_S("serdes_power_up: executing power down.. ");
  1703. DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 1);
  1704. CHECK_STATUS(mv_seq_exec(serdes_num, SERDES_POWER_DOWN_SEQ));
  1705. }
  1706. DEBUG_INIT_FULL_C(
  1707. "serdes_power_up_ctrl ended successfully for serdes ",
  1708. serdes_num, 2);
  1709. return MV_OK;
  1710. }
  1711. int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count)
  1712. {
  1713. u32 lane_data, idx, serdes_lane_hw_num, reg_data = 0;
  1714. enum serdes_type serdes_type;
  1715. enum serdes_mode serdes_mode;
  1716. u8 select_bit_off;
  1717. int is_pex_x4 = 0;
  1718. int updated_topology_print = 0;
  1719. DEBUG_INIT_FULL_S("\n### hws_update_serdes_phy_selectors ###\n");
  1720. DEBUG_INIT_FULL_S
  1721. ("Updating the COMMON PHYS SELECTORS register with the serdes types\n");
  1722. if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2)
  1723. select_bit_off = 3;
  1724. else
  1725. select_bit_off = 4;
  1726. /*
  1727. * Updating bits 0-17 in the COMMON PHYS SELECTORS register
  1728. * according to the serdes types
  1729. */
  1730. for (idx = 0; idx < count; idx++) {
  1731. serdes_type = serdes_map[idx].serdes_type;
  1732. serdes_mode = serdes_map[idx].serdes_mode;
  1733. serdes_lane_hw_num = hws_get_physical_serdes_num(idx);
  1734. lane_data =
  1735. hws_serdes_get_phy_selector_val(serdes_lane_hw_num,
  1736. serdes_type);
  1737. if (serdes_type == DEFAULT_SERDES)
  1738. continue;
  1739. if (hws_serdes_topology_verify
  1740. (serdes_type, idx, serdes_mode) != MV_OK) {
  1741. serdes_map[idx].serdes_type =
  1742. DEFAULT_SERDES;
  1743. printf("%s: SerDes lane #%d is disabled\n", __func__,
  1744. serdes_lane_hw_num);
  1745. updated_topology_print = 1;
  1746. continue;
  1747. }
  1748. /*
  1749. * Checking if the board topology configuration includes
  1750. * PEXx4 - for the next step
  1751. */
  1752. if ((serdes_mode == PEX_END_POINT_X4) ||
  1753. (serdes_mode == PEX_ROOT_COMPLEX_X4)) {
  1754. /* update lane data to the 3 next SERDES lanes */
  1755. lane_data =
  1756. common_phys_selectors_pex_by4_lanes
  1757. [serdes_lane_hw_num];
  1758. if (serdes_type == PEX0)
  1759. is_pex_x4 = 1;
  1760. }
  1761. if (lane_data == NA) {
  1762. printf
  1763. ("%s: Warning: SerDes lane #%d and type %d are not supported together\n",
  1764. __func__, serdes_lane_hw_num, serdes_mode);
  1765. serdes_map[idx].serdes_type = DEFAULT_SERDES;
  1766. printf("%s: SerDes lane #%d is disabled\n", __func__,
  1767. serdes_lane_hw_num);
  1768. continue;
  1769. }
  1770. /*
  1771. * Updating the data that will be written to
  1772. * COMMON_PHYS_SELECTORS_REG
  1773. */
  1774. reg_data |= (lane_data <<
  1775. (select_bit_off * serdes_lane_hw_num));
  1776. }
  1777. /*
  1778. * Check that number of used lanes for XAUI and RXAUI
  1779. * (if used) is right
  1780. */
  1781. hws_serdes_xaui_topology_verify();
  1782. /* Print topology */
  1783. if (updated_topology_print)
  1784. print_topology_details(serdes_map, count);
  1785. /*
  1786. * Updating the PEXx4 Enable bit in the COMMON PHYS SELECTORS
  1787. * register for PEXx4 mode
  1788. */
  1789. reg_data |= (is_pex_x4 == 1) ? (0x1 << PEX_X4_ENABLE_OFFS) : 0;
  1790. /* Updating the COMMON PHYS SELECTORS register */
  1791. reg_write(COMMON_PHYS_SELECTORS_REG, reg_data);
  1792. return MV_OK;
  1793. }
  1794. int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type,
  1795. enum ref_clock ref_clock)
  1796. {
  1797. u32 data1 = 0, data2 = 0, data3 = 0, reg_data;
  1798. DEBUG_INIT_FULL_S("\n### hws_ref_clock_set ###\n");
  1799. if (hws_is_serdes_active(serdes_num) != 1) {
  1800. printf("%s: SerDes lane #%d is not Active\n", __func__,
  1801. serdes_num);
  1802. return MV_BAD_PARAM;
  1803. }
  1804. switch (serdes_type) {
  1805. case PEX0:
  1806. case PEX1:
  1807. case PEX2:
  1808. case PEX3:
  1809. switch (ref_clock) {
  1810. case REF_CLOCK_25MHZ:
  1811. CHECK_STATUS(mv_seq_exec
  1812. (serdes_num,
  1813. PEX_CONFIG_REF_CLOCK_25MHZ_SEQ));
  1814. return MV_OK;
  1815. case REF_CLOCK_100MHZ:
  1816. CHECK_STATUS(mv_seq_exec
  1817. (serdes_num,
  1818. PEX_CONFIG_REF_CLOCK_100MHZ_SEQ));
  1819. return MV_OK;
  1820. default:
  1821. printf
  1822. ("%s: Error: ref_clock %d for SerDes lane #%d, type %d is not supported\n",
  1823. __func__, ref_clock, serdes_num, serdes_type);
  1824. return MV_BAD_PARAM;
  1825. }
  1826. case USB3_HOST0:
  1827. case USB3_HOST1:
  1828. case USB3_DEVICE:
  1829. if (ref_clock == REF_CLOCK_25MHZ) {
  1830. data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2;
  1831. data2 = GLOBAL_PM_CTRL_REG_25MHZ_VAL;
  1832. data3 = LANE_CFG4_REG_25MHZ_VAL;
  1833. } else if (ref_clock == REF_CLOCK_40MHZ) {
  1834. data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
  1835. data2 = GLOBAL_PM_CTRL_REG_40MHZ_VAL;
  1836. data3 = LANE_CFG4_REG_40MHZ_VAL;
  1837. } else {
  1838. printf
  1839. ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
  1840. serdes_type);
  1841. return MV_BAD_PARAM;
  1842. }
  1843. break;
  1844. case SATA0:
  1845. case SATA1:
  1846. case SATA2:
  1847. case SATA3:
  1848. case SGMII0:
  1849. case SGMII1:
  1850. case SGMII2:
  1851. case QSGMII:
  1852. if (ref_clock == REF_CLOCK_25MHZ) {
  1853. data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1;
  1854. } else if (ref_clock == REF_CLOCK_40MHZ) {
  1855. data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
  1856. } else {
  1857. printf
  1858. ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
  1859. serdes_type);
  1860. return MV_BAD_PARAM;
  1861. }
  1862. break;
  1863. default:
  1864. DEBUG_INIT_S("hws_ref_clock_set: not supported serdes type\n");
  1865. return MV_BAD_PARAM;
  1866. }
  1867. /*
  1868. * Write the ref_clock to relevant SELECT_REF_CLOCK_REG bits and
  1869. * offset
  1870. */
  1871. reg_data = reg_read(POWER_AND_PLL_CTRL_REG +
  1872. SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
  1873. reg_data &= POWER_AND_PLL_CTRL_REG_MASK;
  1874. reg_data |= data1;
  1875. reg_write(POWER_AND_PLL_CTRL_REG +
  1876. SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
  1877. if ((serdes_type == USB3_HOST0) || (serdes_type == USB3_HOST1) ||
  1878. (serdes_type == USB3_DEVICE)) {
  1879. reg_data = reg_read(GLOBAL_PM_CTRL +
  1880. SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
  1881. reg_data &= GLOBAL_PM_CTRL_REG_MASK;
  1882. reg_data |= data2;
  1883. reg_write(GLOBAL_PM_CTRL +
  1884. SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
  1885. reg_data = reg_read(LANE_CFG4_REG +
  1886. SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
  1887. reg_data &= LANE_CFG4_REG_MASK;
  1888. reg_data |= data3;
  1889. reg_write(LANE_CFG4_REG +
  1890. SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
  1891. }
  1892. return MV_OK;
  1893. }
  1894. /*
  1895. * hws_pex_tx_config_seq -
  1896. *
  1897. * DESCRIPTION: Set PEX_TX_CONFIG_SEQ sequence init for PEXx4 mode
  1898. * INPUT: serdes_map - The board topology map
  1899. * OUTPUT: None
  1900. * RETURNS: MV_OK - for success
  1901. * MV_BAD_PARAM - for fail
  1902. */
  1903. int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count)
  1904. {
  1905. enum serdes_mode serdes_mode;
  1906. u32 serdes_lane_id, serdes_lane_hw_num;
  1907. DEBUG_INIT_FULL_S("\n### hws_pex_tx_config_seq ###\n");
  1908. /*
  1909. * For PEXx4: the pex_and_usb3_tx_config_params1/2/3
  1910. * configurations should run by setting each sequence for
  1911. * all 4 lanes.
  1912. */
  1913. /* relese pipe soft reset for all lanes */
  1914. for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) {
  1915. serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
  1916. serdes_lane_hw_num =
  1917. hws_get_physical_serdes_num(serdes_lane_id);
  1918. if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  1919. (serdes_mode == PEX_END_POINT_X4)) {
  1920. CHECK_STATUS(mv_seq_exec
  1921. (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ1));
  1922. }
  1923. }
  1924. /* set phy soft reset for all lanes */
  1925. for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) {
  1926. serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
  1927. serdes_lane_hw_num =
  1928. hws_get_physical_serdes_num(serdes_lane_id);
  1929. if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  1930. (serdes_mode == PEX_END_POINT_X4)) {
  1931. CHECK_STATUS(mv_seq_exec
  1932. (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ2));
  1933. }
  1934. }
  1935. /* set phy soft reset for all lanes */
  1936. for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) {
  1937. serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
  1938. serdes_lane_hw_num =
  1939. hws_get_physical_serdes_num(serdes_lane_id);
  1940. if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  1941. (serdes_mode == PEX_END_POINT_X4)) {
  1942. CHECK_STATUS(mv_seq_exec
  1943. (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ3));
  1944. }
  1945. }
  1946. return MV_OK;
  1947. }