cpu.h 3.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. */
  7. #ifndef _MVEBU_CPU_H
  8. #define _MVEBU_CPU_H
  9. #include <asm/system.h>
  10. #ifndef __ASSEMBLY__
  11. #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
  12. #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
  13. enum memory_bank {
  14. BANK0,
  15. BANK1,
  16. BANK2,
  17. BANK3
  18. };
  19. enum cpu_winen {
  20. CPU_WIN_DISABLE,
  21. CPU_WIN_ENABLE
  22. };
  23. enum cpu_target {
  24. CPU_TARGET_DRAM = 0x0,
  25. CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
  26. CPU_TARGET_ETH23 = 0x3,
  27. CPU_TARGET_PCIE02 = 0x4,
  28. CPU_TARGET_ETH01 = 0x7,
  29. CPU_TARGET_PCIE13 = 0x8,
  30. CPU_TARGET_DFX = 0x8,
  31. CPU_TARGET_SASRAM = 0x9,
  32. CPU_TARGET_SATA01 = 0xa, /* A38X */
  33. CPU_TARGET_NAND = 0xd,
  34. CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
  35. };
  36. enum cpu_attrib {
  37. CPU_ATTR_SASRAM = 0x01,
  38. CPU_ATTR_DRAM_CS0 = 0x0e,
  39. CPU_ATTR_DRAM_CS1 = 0x0d,
  40. CPU_ATTR_DRAM_CS2 = 0x0b,
  41. CPU_ATTR_DRAM_CS3 = 0x07,
  42. CPU_ATTR_NANDFLASH = 0x2f,
  43. CPU_ATTR_SPIFLASH = 0x1e,
  44. CPU_ATTR_SPI0_CS0 = 0x1e,
  45. CPU_ATTR_SPI0_CS1 = 0x5e,
  46. CPU_ATTR_SPI1_CS2 = 0x9a,
  47. CPU_ATTR_BOOTROM = 0x1d,
  48. CPU_ATTR_PCIE_IO = 0xe0,
  49. CPU_ATTR_PCIE_MEM = 0xe8,
  50. CPU_ATTR_DEV_CS0 = 0x3e,
  51. CPU_ATTR_DEV_CS1 = 0x3d,
  52. CPU_ATTR_DEV_CS2 = 0x3b,
  53. CPU_ATTR_DEV_CS3 = 0x37,
  54. };
  55. enum {
  56. MVEBU_SOC_AXP,
  57. MVEBU_SOC_A375,
  58. MVEBU_SOC_A38X,
  59. MVEBU_SOC_MSYS,
  60. MVEBU_SOC_UNKNOWN,
  61. };
  62. #define MVEBU_SDRAM_SIZE_MAX 0xc0000000
  63. /*
  64. * Default Device Address MAP BAR values
  65. */
  66. #define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX
  67. #define MBUS_PCI_MEM_SIZE (128 << 20)
  68. #define MBUS_PCI_IO_BASE 0xF1100000
  69. #define MBUS_PCI_IO_SIZE (64 << 10)
  70. #define MBUS_SPI_BASE 0xF4000000
  71. #define MBUS_SPI_SIZE (8 << 20)
  72. #define MBUS_DFX_BASE 0xF6000000
  73. #define MBUS_DFX_SIZE (1 << 20)
  74. #define MBUS_BOOTROM_BASE 0xF8000000
  75. #define MBUS_BOOTROM_SIZE (8 << 20)
  76. struct mbus_win {
  77. u32 base;
  78. u32 size;
  79. u8 target;
  80. u8 attr;
  81. };
  82. /*
  83. * System registers
  84. * Ref: Datasheet sec:A.28
  85. */
  86. struct mvebu_system_registers {
  87. #if defined(CONFIG_ARMADA_375)
  88. u8 pad1[0x54];
  89. #else
  90. u8 pad1[0x60];
  91. #endif
  92. u32 rstoutn_mask; /* 0x60 */
  93. u32 sys_soft_rst; /* 0x64 */
  94. };
  95. /*
  96. * GPIO Registers
  97. * Ref: Datasheet sec:A.19
  98. */
  99. struct kwgpio_registers {
  100. u32 dout;
  101. u32 oe;
  102. u32 blink_en;
  103. u32 din_pol;
  104. u32 din;
  105. u32 irq_cause;
  106. u32 irq_mask;
  107. u32 irq_level;
  108. };
  109. struct sar_freq_modes {
  110. u8 val;
  111. u8 ffc; /* Fabric Frequency Configuration */
  112. u32 p_clk;
  113. u32 nb_clk;
  114. u32 d_clk;
  115. };
  116. /* Needed for dynamic (board-specific) mbus configuration */
  117. extern struct mvebu_mbus_state mbus_state;
  118. /*
  119. * functions
  120. */
  121. unsigned int mvebu_sdram_bar(enum memory_bank bank);
  122. unsigned int mvebu_sdram_bs(enum memory_bank bank);
  123. void mvebu_sdram_size_adjust(enum memory_bank bank);
  124. int mvebu_mbus_probe(struct mbus_win windows[], int count);
  125. int mvebu_soc_family(void);
  126. u32 mvebu_get_nand_clock(void);
  127. void return_to_bootrom(void);
  128. #ifndef CONFIG_DM_MMC
  129. int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
  130. #endif
  131. void get_sar_freq(struct sar_freq_modes *sar_freq);
  132. /*
  133. * Highspeed SERDES PHY config init, ported from bin_hdr
  134. * to mainline U-Boot
  135. */
  136. int serdes_phy_config(void);
  137. /*
  138. * DDR3 init / training code ported from Marvell bin_hdr. Now
  139. * available in mainline U-Boot in:
  140. * drivers/ddr/marvell
  141. */
  142. int ddr3_init(void);
  143. /* Auto Voltage Scaling */
  144. #if defined(CONFIG_ARMADA_38X)
  145. void mv_avs_init(void);
  146. void mv_rtc_config(void);
  147. #else
  148. static inline void mv_avs_init(void) {}
  149. static inline void mv_rtc_config(void) {}
  150. #endif
  151. /* A8K dram functions */
  152. u64 a8k_dram_scan_ap_sz(void);
  153. int a8k_dram_init_banksize(void);
  154. /* A3700 dram functions */
  155. int a3700_dram_init(void);
  156. int a3700_dram_init_banksize(void);
  157. /* A3700 PCIe regions fixer for device tree */
  158. int a3700_fdt_fix_pcie_regions(void *blob);
  159. /*
  160. * get_ref_clk
  161. *
  162. * return: reference clock in MHz (25 or 40)
  163. */
  164. u32 get_ref_clk(void);
  165. #endif /* __ASSEMBLY__ */
  166. #endif /* _MVEBU_CPU_H */