imx-regs.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #ifndef __ASM_ARCH_IMX8_REGS_H__
  6. #define __ASM_ARCH_IMX8_REGS_H__
  7. #define ARCH_MXC
  8. #define LPUART_BASE 0x5A060000
  9. #define GPT1_BASE_ADDR 0x5D140000
  10. #define SCU_LPUART_BASE 0x33220000
  11. #define GPIO1_BASE_ADDR 0x5D080000
  12. #define GPIO2_BASE_ADDR 0x5D090000
  13. #define GPIO3_BASE_ADDR 0x5D0A0000
  14. #define GPIO4_BASE_ADDR 0x5D0B0000
  15. #define GPIO5_BASE_ADDR 0x5D0C0000
  16. #define GPIO6_BASE_ADDR 0x5D0D0000
  17. #define GPIO7_BASE_ADDR 0x5D0E0000
  18. #define GPIO8_BASE_ADDR 0x5D0F0000
  19. #define LPI2C1_BASE_ADDR 0x5A800000
  20. #define LPI2C2_BASE_ADDR 0x5A810000
  21. #define LPI2C3_BASE_ADDR 0x5A820000
  22. #define LPI2C4_BASE_ADDR 0x5A830000
  23. #define LPI2C5_BASE_ADDR 0x5A840000
  24. #define FEC_QUIRK_ENET_MAC
  25. #ifdef CONFIG_IMX8QXP
  26. #define LVDS0_PHYCTRL_BASE 0x56221000
  27. #define LVDS1_PHYCTRL_BASE 0x56241000
  28. #define MIPI0_SS_BASE 0x56220000
  29. #define MIPI1_SS_BASE 0x56240000
  30. #endif
  31. #define APBH_DMA_ARB_BASE_ADDR 0x5B810000
  32. #define APBH_DMA_ARB_END_ADDR 0x5B81FFFF
  33. #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
  34. #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
  35. #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
  36. #define PASS_OVER_INFO_ADDR 0x0010fe00
  37. #define USB_BASE_ADDR 0x5b0d0000
  38. #define USB_PHY0_BASE_ADDR 0x5b100000
  39. #endif /* __ASM_ARCH_IMX8_REGS_H__ */