imx8mm-venice-gw72xx.dtsi 7.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright 2020 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/leds/common.h>
  7. / {
  8. aliases {
  9. usb0 = &usbotg1;
  10. usb1 = &usbotg2;
  11. };
  12. led-controller {
  13. compatible = "gpio-leds";
  14. pinctrl-names = "default";
  15. pinctrl-0 = <&pinctrl_gpio_leds>;
  16. led-0 {
  17. function = LED_FUNCTION_STATUS;
  18. color = <LED_COLOR_ID_GREEN>;
  19. gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  20. default-state = "on";
  21. linux,default-trigger = "heartbeat";
  22. };
  23. led-1 {
  24. function = LED_FUNCTION_STATUS;
  25. color = <LED_COLOR_ID_RED>;
  26. gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  27. default-state = "off";
  28. };
  29. };
  30. pps {
  31. compatible = "pps-gpio";
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&pinctrl_pps>;
  34. gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
  35. status = "okay";
  36. };
  37. reg_3p3v: regulator-3p3v {
  38. compatible = "regulator-fixed";
  39. regulator-name = "3P3V";
  40. regulator-min-microvolt = <3300000>;
  41. regulator-max-microvolt = <3300000>;
  42. regulator-always-on;
  43. };
  44. reg_usb_otg1_vbus: regulator-usb-otg1 {
  45. pinctrl-names = "default";
  46. pinctrl-0 = <&pinctrl_reg_usb1_en>;
  47. compatible = "regulator-fixed";
  48. regulator-name = "usb_otg1_vbus";
  49. gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  50. enable-active-high;
  51. regulator-min-microvolt = <5000000>;
  52. regulator-max-microvolt = <5000000>;
  53. };
  54. reg_usb_otg2_vbus: regulator-usb-otg2 {
  55. pinctrl-names = "default";
  56. pinctrl-0 = <&pinctrl_reg_usb2_en>;
  57. compatible = "regulator-fixed";
  58. regulator-name = "usb_otg2_vbus";
  59. gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  60. enable-active-high;
  61. regulator-min-microvolt = <5000000>;
  62. regulator-max-microvolt = <5000000>;
  63. };
  64. };
  65. /* off-board header */
  66. &ecspi2 {
  67. pinctrl-names = "default";
  68. pinctrl-0 = <&pinctrl_spi2>;
  69. cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
  70. status = "okay";
  71. };
  72. &i2c2 {
  73. clock-frequency = <400000>;
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&pinctrl_i2c2>;
  76. status = "okay";
  77. accelerometer@19 {
  78. pinctrl-names = "default";
  79. pinctrl-0 = <&pinctrl_accel>;
  80. compatible = "st,lis2de12";
  81. reg = <0x19>;
  82. st,drdy-int-pin = <1>;
  83. interrupt-parent = <&gpio4>;
  84. interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
  85. interrupt-names = "INT1";
  86. };
  87. };
  88. /* off-board header */
  89. &i2c3 {
  90. clock-frequency = <400000>;
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&pinctrl_i2c3>;
  93. status = "okay";
  94. };
  95. /* off-board header */
  96. &sai3 {
  97. pinctrl-names = "default";
  98. pinctrl-0 = <&pinctrl_sai3>;
  99. assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
  100. assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  101. assigned-clock-rates = <24576000>;
  102. status = "okay";
  103. };
  104. /* GPS */
  105. &uart1 {
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&pinctrl_uart1>;
  108. status = "okay";
  109. };
  110. /* off-board header */
  111. &uart3 {
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&pinctrl_uart3>;
  114. status = "okay";
  115. };
  116. /* RS232 */
  117. &uart4 {
  118. pinctrl-names = "default";
  119. pinctrl-0 = <&pinctrl_uart4>;
  120. status = "okay";
  121. };
  122. &usbotg1 {
  123. dr_mode = "otg";
  124. vbus-supply = <&reg_usb_otg1_vbus>;
  125. status = "okay";
  126. };
  127. &usbotg2 {
  128. dr_mode = "host";
  129. vbus-supply = <&reg_usb_otg2_vbus>;
  130. status = "okay";
  131. };
  132. /* microSD */
  133. &usdhc2 {
  134. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  135. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  136. pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  137. pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  138. cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  139. bus-width = <4>;
  140. vmmc-supply = <&reg_3p3v>;
  141. status = "okay";
  142. };
  143. &iomuxc {
  144. pinctrl-names = "default";
  145. pinctrl-0 = <&pinctrl_hog>;
  146. pinctrl_hog: hoggrp {
  147. fsl,pins = <
  148. MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
  149. MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
  150. MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
  151. MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
  152. MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
  153. MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
  154. MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
  155. MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
  156. >;
  157. };
  158. pinctrl_accel: accelgrp {
  159. fsl,pins = <
  160. MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
  161. >;
  162. };
  163. pinctrl_gpio_leds: gpioledgrp {
  164. fsl,pins = <
  165. MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
  166. MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
  167. >;
  168. };
  169. pinctrl_i2c3: i2c3grp {
  170. fsl,pins = <
  171. MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
  172. MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
  173. >;
  174. };
  175. pinctrl_pps: ppsgrp {
  176. fsl,pins = <
  177. MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
  178. >;
  179. };
  180. pinctrl_reg_usb1_en: regusb1grp {
  181. fsl,pins = <
  182. MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
  183. MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
  184. >;
  185. };
  186. pinctrl_reg_usb2_en: regusb2grp {
  187. fsl,pins = <
  188. MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
  189. >;
  190. };
  191. pinctrl_sai3: sai3grp {
  192. fsl,pins = <
  193. MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
  194. MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
  195. MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
  196. MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
  197. MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
  198. >;
  199. };
  200. pinctrl_spi2: spi2grp {
  201. fsl,pins = <
  202. MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
  203. MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
  204. MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
  205. MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
  206. >;
  207. };
  208. pinctrl_uart1: uart1grp {
  209. fsl,pins = <
  210. MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
  211. MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
  212. >;
  213. };
  214. pinctrl_uart3: uart3grp {
  215. fsl,pins = <
  216. MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
  217. MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
  218. >;
  219. };
  220. pinctrl_uart4: uart4grp {
  221. fsl,pins = <
  222. MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
  223. MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
  224. >;
  225. };
  226. pinctrl_usdhc1: usdhc1grp {
  227. fsl,pins = <
  228. MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
  229. MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
  230. MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
  231. MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
  232. MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
  233. MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
  234. >;
  235. };
  236. pinctrl_usdhc2: usdhc2grp {
  237. fsl,pins = <
  238. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
  239. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
  240. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
  241. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
  242. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
  243. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
  244. >;
  245. };
  246. pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
  247. fsl,pins = <
  248. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
  249. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
  250. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
  251. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
  252. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
  253. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
  254. >;
  255. };
  256. pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
  257. fsl,pins = <
  258. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
  259. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
  260. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
  261. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
  262. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
  263. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
  264. >;
  265. };
  266. pinctrl_usdhc2_gpio: usdhc2gpiogrp {
  267. fsl,pins = <
  268. MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
  269. MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
  270. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  271. >;
  272. };
  273. };