imx8mm-venice-gw700x.dtsi 9.8 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright 2020 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/net/ti-dp83867.h>
  8. / {
  9. memory@40000000 {
  10. device_type = "memory";
  11. reg = <0x0 0x40000000 0 0x80000000>;
  12. };
  13. gpio-keys {
  14. compatible = "gpio-keys";
  15. user-pb {
  16. label = "user_pb";
  17. gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  18. linux,code = <BTN_0>;
  19. };
  20. user-pb1x {
  21. label = "user_pb1x";
  22. linux,code = <BTN_1>;
  23. interrupt-parent = <&gsc>;
  24. interrupts = <0>;
  25. };
  26. key-erased {
  27. label = "key_erased";
  28. linux,code = <BTN_2>;
  29. interrupt-parent = <&gsc>;
  30. interrupts = <1>;
  31. };
  32. eeprom-wp {
  33. label = "eeprom_wp";
  34. linux,code = <BTN_3>;
  35. interrupt-parent = <&gsc>;
  36. interrupts = <2>;
  37. };
  38. tamper {
  39. label = "tamper";
  40. linux,code = <BTN_4>;
  41. interrupt-parent = <&gsc>;
  42. interrupts = <5>;
  43. };
  44. switch-hold {
  45. label = "switch_hold";
  46. linux,code = <BTN_5>;
  47. interrupt-parent = <&gsc>;
  48. interrupts = <7>;
  49. };
  50. };
  51. };
  52. &A53_0 {
  53. cpu-supply = <&buck3_reg>;
  54. };
  55. &A53_1 {
  56. cpu-supply = <&buck3_reg>;
  57. };
  58. &A53_2 {
  59. cpu-supply = <&buck3_reg>;
  60. };
  61. &A53_3 {
  62. cpu-supply = <&buck3_reg>;
  63. };
  64. &ddrc {
  65. operating-points-v2 = <&ddrc_opp_table>;
  66. ddrc_opp_table: opp-table {
  67. compatible = "operating-points-v2";
  68. opp-25M {
  69. opp-hz = /bits/ 64 <25000000>;
  70. };
  71. opp-100M {
  72. opp-hz = /bits/ 64 <100000000>;
  73. };
  74. opp-750M {
  75. opp-hz = /bits/ 64 <750000000>;
  76. };
  77. };
  78. };
  79. &fec1 {
  80. pinctrl-names = "default";
  81. pinctrl-0 = <&pinctrl_fec1>;
  82. phy-mode = "rgmii-id";
  83. phy-handle = <&ethphy0>;
  84. status = "okay";
  85. mdio {
  86. #address-cells = <1>;
  87. #size-cells = <0>;
  88. ethphy0: ethernet-phy@0 {
  89. compatible = "ethernet-phy-ieee802.3-c22";
  90. reg = <0>;
  91. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  92. ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  93. tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  94. rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  95. };
  96. };
  97. };
  98. &i2c1 {
  99. clock-frequency = <100000>;
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&pinctrl_i2c1>;
  102. status = "okay";
  103. gsc: gsc@20 {
  104. compatible = "gw,gsc";
  105. reg = <0x20>;
  106. pinctrl-0 = <&pinctrl_gsc>;
  107. interrupt-parent = <&gpio2>;
  108. interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
  109. interrupt-controller;
  110. #interrupt-cells = <1>;
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. adc {
  114. compatible = "gw,gsc-adc";
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. channel@6 {
  118. gw,mode = <0>;
  119. reg = <0x06>;
  120. label = "temp";
  121. };
  122. channel@8 {
  123. gw,mode = <1>;
  124. reg = <0x08>;
  125. label = "vdd_bat";
  126. };
  127. channel@16 {
  128. gw,mode = <4>;
  129. reg = <0x16>;
  130. label = "fan_tach";
  131. };
  132. channel@82 {
  133. gw,mode = <2>;
  134. reg = <0x82>;
  135. label = "vdd_vin";
  136. gw,voltage-divider-ohms = <22100 1000>;
  137. };
  138. channel@84 {
  139. gw,mode = <2>;
  140. reg = <0x84>;
  141. label = "vdd_adc1";
  142. gw,voltage-divider-ohms = <10000 10000>;
  143. };
  144. channel@86 {
  145. gw,mode = <2>;
  146. reg = <0x86>;
  147. label = "vdd_adc2";
  148. gw,voltage-divider-ohms = <10000 10000>;
  149. };
  150. channel@88 {
  151. gw,mode = <2>;
  152. reg = <0x88>;
  153. label = "vdd_dram";
  154. };
  155. channel@8c {
  156. gw,mode = <2>;
  157. reg = <0x8c>;
  158. label = "vdd_1p2";
  159. };
  160. channel@8e {
  161. gw,mode = <2>;
  162. reg = <0x8e>;
  163. label = "vdd_1p0";
  164. };
  165. channel@90 {
  166. gw,mode = <2>;
  167. reg = <0x90>;
  168. label = "vdd_2p5";
  169. gw,voltage-divider-ohms = <10000 10000>;
  170. };
  171. channel@92 {
  172. gw,mode = <2>;
  173. reg = <0x92>;
  174. label = "vdd_3p3";
  175. gw,voltage-divider-ohms = <10000 10000>;
  176. };
  177. channel@98 {
  178. gw,mode = <2>;
  179. reg = <0x98>;
  180. label = "vdd_0p95";
  181. };
  182. channel@9a {
  183. gw,mode = <2>;
  184. reg = <0x9a>;
  185. label = "vdd_1p8";
  186. };
  187. channel@a2 {
  188. gw,mode = <2>;
  189. reg = <0xa2>;
  190. label = "vdd_gsc";
  191. gw,voltage-divider-ohms = <10000 10000>;
  192. };
  193. };
  194. fan-controller@0 {
  195. #address-cells = <1>;
  196. #size-cells = <0>;
  197. compatible = "gw,gsc-fan";
  198. reg = <0x0a>;
  199. };
  200. };
  201. gpio: gpio@23 {
  202. compatible = "nxp,pca9555";
  203. reg = <0x23>;
  204. gpio-controller;
  205. #gpio-cells = <2>;
  206. interrupt-parent = <&gsc>;
  207. interrupts = <4>;
  208. };
  209. eeprom@50 {
  210. compatible = "atmel,24c02";
  211. reg = <0x50>;
  212. pagesize = <16>;
  213. };
  214. eeprom@51 {
  215. compatible = "atmel,24c02";
  216. reg = <0x51>;
  217. pagesize = <16>;
  218. };
  219. eeprom@52 {
  220. compatible = "atmel,24c02";
  221. reg = <0x52>;
  222. pagesize = <16>;
  223. };
  224. eeprom@53 {
  225. compatible = "atmel,24c02";
  226. reg = <0x53>;
  227. pagesize = <16>;
  228. };
  229. rtc@68 {
  230. compatible = "dallas,ds1672";
  231. reg = <0x68>;
  232. };
  233. pmic@69 {
  234. compatible = "mps,mp5416";
  235. pinctrl-names = "default";
  236. pinctrl-0 = <&pinctrl_pmic>;
  237. reg = <0x69>;
  238. regulators {
  239. buck1 {
  240. regulator-name = "vdd_0p95";
  241. regulator-min-microvolt = <805000>;
  242. regulator-max-microvolt = <1000000>;
  243. regulator-max-microamp = <2500000>;
  244. regulator-boot-on;
  245. };
  246. buck2 {
  247. regulator-name = "vdd_soc";
  248. regulator-min-microvolt = <805000>;
  249. regulator-max-microvolt = <900000>;
  250. regulator-max-microamp = <1000000>;
  251. regulator-boot-on;
  252. };
  253. buck3_reg: buck3 {
  254. regulator-name = "vdd_arm";
  255. regulator-min-microvolt = <805000>;
  256. regulator-max-microvolt = <1000000>;
  257. regulator-max-microamp = <2200000>;
  258. regulator-boot-on;
  259. };
  260. buck4 {
  261. regulator-name = "vdd_1p8";
  262. regulator-min-microvolt = <1800000>;
  263. regulator-max-microvolt = <1800000>;
  264. regulator-max-microamp = <500000>;
  265. regulator-boot-on;
  266. };
  267. ldo1 {
  268. regulator-name = "nvcc_snvs_1p8";
  269. regulator-min-microvolt = <1800000>;
  270. regulator-max-microvolt = <1800000>;
  271. regulator-max-microamp = <300000>;
  272. regulator-boot-on;
  273. };
  274. ldo2 {
  275. regulator-name = "vdd_snvs_0p8";
  276. regulator-min-microvolt = <800000>;
  277. regulator-max-microvolt = <800000>;
  278. regulator-boot-on;
  279. };
  280. ldo3 {
  281. regulator-name = "vdd_0p95";
  282. regulator-min-microvolt = <800000>;
  283. regulator-max-microvolt = <800000>;
  284. regulator-boot-on;
  285. };
  286. ldo4 {
  287. regulator-name = "vdd_1p8";
  288. regulator-min-microvolt = <1800000>;
  289. regulator-max-microvolt = <1800000>;
  290. regulator-boot-on;
  291. };
  292. };
  293. };
  294. };
  295. &i2c2 {
  296. clock-frequency = <400000>;
  297. pinctrl-names = "default";
  298. pinctrl-0 = <&pinctrl_i2c2>;
  299. status = "okay";
  300. eeprom@52 {
  301. compatible = "atmel,24c32";
  302. reg = <0x52>;
  303. pagesize = <32>;
  304. };
  305. };
  306. /* console */
  307. &uart2 {
  308. pinctrl-names = "default";
  309. pinctrl-0 = <&pinctrl_uart2>;
  310. status = "okay";
  311. };
  312. /* eMMC */
  313. &usdhc3 {
  314. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  315. pinctrl-0 = <&pinctrl_usdhc3>;
  316. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  317. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  318. bus-width = <8>;
  319. non-removable;
  320. status = "okay";
  321. };
  322. &wdog1 {
  323. pinctrl-names = "default";
  324. pinctrl-0 = <&pinctrl_wdog>;
  325. fsl,ext-reset-output;
  326. status = "okay";
  327. };
  328. &iomuxc {
  329. pinctrl_fec1: fec1grp {
  330. fsl,pins = <
  331. MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  332. MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
  333. MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  334. MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  335. MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  336. MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  337. MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  338. MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  339. MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  340. MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  341. MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  342. MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  343. MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  344. MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  345. MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
  346. >;
  347. };
  348. pinctrl_gsc: gscgrp {
  349. fsl,pins = <
  350. MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
  351. >;
  352. };
  353. pinctrl_i2c1: i2c1grp {
  354. fsl,pins = <
  355. MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
  356. MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
  357. >;
  358. };
  359. pinctrl_i2c2: i2c2grp {
  360. fsl,pins = <
  361. MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
  362. MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
  363. >;
  364. };
  365. pinctrl_pmic: pmicgrp {
  366. fsl,pins = <
  367. MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
  368. >;
  369. };
  370. pinctrl_uart2: uart2grp {
  371. fsl,pins = <
  372. MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
  373. MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
  374. >;
  375. };
  376. pinctrl_usdhc3: usdhc3grp {
  377. fsl,pins = <
  378. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
  379. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
  380. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
  381. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
  382. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
  383. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
  384. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
  385. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
  386. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
  387. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
  388. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
  389. >;
  390. };
  391. pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
  392. fsl,pins = <
  393. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
  394. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
  395. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
  396. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
  397. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
  398. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
  399. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
  400. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
  401. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
  402. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
  403. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
  404. >;
  405. };
  406. pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
  407. fsl,pins = <
  408. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
  409. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
  410. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
  411. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
  412. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
  413. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
  414. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
  415. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
  416. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
  417. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
  418. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
  419. >;
  420. };
  421. pinctrl_wdog: wdoggrp {
  422. fsl,pins = <
  423. MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  424. >;
  425. };
  426. };