fsl-imx8qxp-apalis.dts 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2. /*
  3. * Copyright 2020 Toradex
  4. */
  5. /dts-v1/;
  6. #include "fsl-imx8qxp.dtsi"
  7. #include "fsl-imx8qxp-apalis-u-boot.dtsi"
  8. / {
  9. model = "Toradex Apalis iMX8X";
  10. compatible = "toradex,apalis-imx8x", "fsl,imx8qxp";
  11. chosen {
  12. bootargs = "console=ttyLP1,115200";
  13. stdout-path = &lpuart1;
  14. };
  15. regulators {
  16. compatible = "simple-bus";
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. reg_usb_otg1_vbus: regulator@0 {
  20. compatible = "regulator-fixed";
  21. reg = <0>;
  22. regulator-name = "usb_otg1_vbus";
  23. regulator-min-microvolt = <5000000>;
  24. regulator-max-microvolt = <5000000>;
  25. gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  26. enable-active-high;
  27. };
  28. };
  29. };
  30. &iomuxc {
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>;
  33. apalis-imx8x {
  34. /* Apalis UART1 */
  35. pinctrl_lpuart1: lpuart1grp {
  36. fsl,pins = <
  37. SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 /* SODIMM 118 */
  38. SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 /* SODIMM 112 */
  39. >;
  40. };
  41. /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */
  42. pinctrl_fec1: fec1grp {
  43. fsl,pins = <
  44. SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0
  45. SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0
  46. SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
  47. SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
  48. SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
  49. SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61
  50. SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
  51. SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
  52. SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61
  53. SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61
  54. SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61
  55. SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
  56. SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61
  57. SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61
  58. SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61
  59. SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61
  60. /* On-module ETH_RESET# */
  61. SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x06000020
  62. /* On-module ETH_INT# */
  63. SC_P_ADC_IN2_LSIO_GPIO1_IO12 0x21
  64. >;
  65. };
  66. /* Apalis BKL_ON */
  67. pinctrl_gpio_bkl_on: gpio-bkl-on {
  68. fsl,pins = <
  69. SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 286 */
  70. >;
  71. };
  72. pinctrl_hog0: hog0grp {
  73. fsl,pins = <
  74. SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
  75. >;
  76. };
  77. pinctrl_hog1: hog1grp {
  78. fsl,pins = <
  79. /* Apalis USBO1_EN */
  80. SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x41 /* SODIMM 274 */
  81. >;
  82. };
  83. /* Apalis RESET_MOCI# */
  84. pinctrl_reset_moci: gpioresetmocigrp {
  85. fsl,pins = <
  86. SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x21
  87. >;
  88. };
  89. /* On-module eMMC */
  90. pinctrl_usdhc1: usdhc1grp {
  91. fsl,pins = <
  92. SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
  93. SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21
  94. SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
  95. SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
  96. SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
  97. SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
  98. SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
  99. SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
  100. SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
  101. SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
  102. SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
  103. SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
  104. >;
  105. };
  106. pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  107. fsl,pins = <
  108. SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
  109. SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21
  110. SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
  111. SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
  112. SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
  113. SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
  114. SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
  115. SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
  116. SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
  117. SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
  118. SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
  119. SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
  120. >;
  121. };
  122. pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  123. fsl,pins = <
  124. SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
  125. SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21
  126. SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
  127. SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
  128. SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
  129. SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
  130. SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
  131. SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
  132. SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
  133. SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
  134. SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
  135. SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
  136. >;
  137. };
  138. /* Apalis MMC1_CD# */
  139. pinctrl_usdhc2_gpio: mmc1gpiogrp {
  140. fsl,pins = <
  141. SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* SODIMM 164 */
  142. >;
  143. };
  144. pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp {
  145. fsl,pins = <
  146. SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* SODIMM 164 */
  147. >;
  148. };
  149. /* Apalis USBH_EN */
  150. pinctrl_usbh_en: usbhen {
  151. fsl,pins = <
  152. SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x40 /* SODIMM 84 */
  153. >;
  154. };
  155. /* Apalis MMC1 */
  156. pinctrl_usdhc2: usdhc2grp {
  157. fsl,pins = <
  158. SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */
  159. SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */
  160. SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */
  161. SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */
  162. SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */
  163. SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */
  164. SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
  165. >;
  166. };
  167. pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  168. fsl,pins = <
  169. SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */
  170. SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */
  171. SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */
  172. SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */
  173. SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */
  174. SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */
  175. SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
  176. >;
  177. };
  178. pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  179. fsl,pins = <
  180. SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */
  181. SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */
  182. SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */
  183. SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */
  184. SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */
  185. SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */
  186. SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
  187. >;
  188. };
  189. pinctrl_usdhc2_sleep: usdhc2slpgrp {
  190. fsl,pins = <
  191. SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 154 */
  192. SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 150 */
  193. SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 160 */
  194. SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 162 */
  195. SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 144 */
  196. SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 146 */
  197. SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
  198. >;
  199. };
  200. };
  201. };
  202. /* Apalis Gigabit LAN */
  203. &fec1 {
  204. pinctrl-names = "default";
  205. pinctrl-0 = <&pinctrl_fec1>;
  206. fsl,magic-packet;
  207. phy-handle = <&ethphy0>;
  208. phy-mode = "rgmii-id";
  209. phy-reset-duration = <10>;
  210. phy-reset-post-delay = <150>;
  211. phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
  212. status = "okay";
  213. mdio {
  214. #address-cells = <1>;
  215. #size-cells = <0>;
  216. ethphy0: ethernet-phy@4 {
  217. compatible = "ethernet-phy-ieee802.3-c22";
  218. reg = <4>;
  219. };
  220. };
  221. };
  222. /* Apalis UART1 */
  223. &lpuart1 {
  224. pinctrl-names = "default";
  225. pinctrl-0 = <&pinctrl_lpuart1>;
  226. status = "okay";
  227. };
  228. /* On-module eMMC */
  229. &usdhc1 {
  230. bus-width = <8>;
  231. non-removable;
  232. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  233. pinctrl-0 = <&pinctrl_usdhc1>;
  234. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  235. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  236. status = "okay";
  237. };
  238. /* Apalis MMC1 */
  239. &usdhc2 {
  240. bus-width = <4>;
  241. cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  242. pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
  243. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  244. pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  245. pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  246. pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
  247. disable-wp;
  248. status = "okay";
  249. };