fsl-imx8qm-apalis.dts 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2017-2019 Toradex
  4. */
  5. /dts-v1/;
  6. /* First 128KB is for PSCI ATF. */
  7. /memreserve/ 0x80000000 0x00020000;
  8. #include "fsl-imx8qm.dtsi"
  9. #include "fsl-imx8qm-apalis-u-boot.dtsi"
  10. / {
  11. model = "Toradex Apalis iMX8";
  12. compatible = "toradex,apalis-imx8", "fsl,imx8qm";
  13. chosen {
  14. bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";
  15. stdout-path = &lpuart1;
  16. };
  17. };
  18. &iomuxc {
  19. pinctrl-names = "default";
  20. pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
  21. <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
  22. <&pinctrl_gpio12>, <&pinctrl_gpio34>, <&pinctrl_gpio56>,
  23. <&pinctrl_gpio7>, <&pinctrl_gpio8>, <&pinctrl_gpio_bkl_on>,
  24. <&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>,
  25. <&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>,
  26. <&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>,
  27. <&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>,
  28. <&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>,
  29. <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
  30. <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
  31. <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
  32. <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
  33. <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>;
  34. apalis-imx8 {
  35. pinctrl_gpio12: gpio12grp {
  36. fsl,pins = <
  37. /* Apalis GPIO1 */
  38. SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021
  39. /* Apalis GPIO2 */
  40. SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021
  41. >;
  42. };
  43. pinctrl_gpio34: gpio34grp {
  44. fsl,pins = <
  45. /* Apalis GPIO3 */
  46. SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021
  47. /* Apalis GPIO4 */
  48. SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021
  49. >;
  50. };
  51. pinctrl_gpio56: gpio56grp {
  52. fsl,pins = <
  53. /* Apalis GPIO5 */
  54. SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021
  55. /* Apalis GPIO6 */
  56. SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x06000021
  57. >;
  58. };
  59. pinctrl_gpio7: gpio7 {
  60. fsl,pins = <
  61. /* Apalis GPIO7 */
  62. SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021
  63. >;
  64. };
  65. pinctrl_gpio8: gpio8 {
  66. fsl,pins = <
  67. /* Apalis GPIO8 */
  68. SC_P_MLB_DATA_LSIO_GPIO3_IO28 0x00000021
  69. >;
  70. };
  71. pinctrl_gpio_keys: gpio-keys {
  72. fsl,pins = <
  73. /* Apalis WAKE1_MICO */
  74. SC_P_SPI3_CS0_LSIO_GPIO2_IO20 0x06000021
  75. >;
  76. };
  77. pinctrl_fec1: fec1grp {
  78. fsl,pins = <
  79. SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 3.3V mode */
  80. SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
  81. SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
  82. SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
  83. SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
  84. SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
  85. SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
  86. SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
  87. SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
  88. SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
  89. SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
  90. SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
  91. SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
  92. SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
  93. SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
  94. SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020
  95. /* ETH_RESET# */
  96. SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020
  97. >;
  98. };
  99. pinctrl_gpio_bkl_on: gpio-bkl-on {
  100. fsl,pins = <
  101. /* Apalis BKL_ON */
  102. SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021
  103. >;
  104. };
  105. /* Apalis I2C2 (DDC) */
  106. pinctrl_lpi2c0: lpi2c0grp {
  107. fsl,pins = <
  108. SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022
  109. SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022
  110. >;
  111. };
  112. pinctrl_cam1_gpios: cam1gpiosgrp {
  113. fsl,pins = <
  114. /* Apalis CAM1_D7 */
  115. SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021
  116. /* Apalis CAM1_D6 */
  117. SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021
  118. /* Apalis CAM1_D5 */
  119. SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021
  120. /* Apalis CAM1_D4 */
  121. SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021
  122. /* Apalis CAM1_D3 */
  123. SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021
  124. /* Apalis CAM1_D2 */
  125. SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021
  126. /* Apalis CAM1_D1 */
  127. SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021
  128. /* Apalis CAM1_D0 */
  129. SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021
  130. /* Apalis CAM1_PCLK */
  131. SC_P_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021
  132. /* Apalis CAM1_MCLK */
  133. SC_P_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021
  134. /* Apalis CAM1_VSYNC */
  135. SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021
  136. /* Apalis CAM1_HSYNC */
  137. SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021
  138. >;
  139. };
  140. pinctrl_dap1_gpios: dap1gpiosgrp {
  141. fsl,pins = <
  142. /* Apalis DAP1_MCLK */
  143. SC_P_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021
  144. /* Apalis DAP1_D_OUT */
  145. SC_P_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021
  146. /* Apalis DAP1_RESET */
  147. SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021
  148. /* Apalis DAP1_BIT_CLK */
  149. SC_P_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021
  150. /* Apalis DAP1_D_IN */
  151. SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021
  152. /* Apalis DAP1_SYNC */
  153. SC_P_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021
  154. /* Wi-Fi_I2S_EN# */
  155. SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021
  156. >;
  157. };
  158. pinctrl_esai0_gpios: esai0gpiosgrp {
  159. fsl,pins = <
  160. /* Apalis LCD1_G1 */
  161. SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021
  162. /* Apalis LCD1_G2 */
  163. SC_P_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021
  164. >;
  165. };
  166. pinctrl_fec2_gpios: fec2gpiosgrp {
  167. fsl,pins = <
  168. SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
  169. /* Apalis LCD1_R1 */
  170. SC_P_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021
  171. /* Apalis LCD1_R0 */
  172. SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021
  173. /* Apalis LCD1_G0 */
  174. SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021
  175. /* Apalis LCD1_R7 */
  176. SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021
  177. /* Apalis LCD1_DE */
  178. SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021
  179. /* Apalis LCD1_HSYNC */
  180. SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021
  181. /* Apalis LCD1_VSYNC */
  182. SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021
  183. /* Apalis LCD1_PCLK */
  184. SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021
  185. /* Apalis LCD1_R6 */
  186. SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021
  187. /* Apalis LCD1_R5 */
  188. SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021
  189. /* Apalis LCD1_R4 */
  190. SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021
  191. /* Apalis LCD1_R3 */
  192. SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021
  193. /* Apalis LCD1_R2 */
  194. SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021
  195. >;
  196. };
  197. pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio {
  198. fsl,pins = <
  199. /* Apalis TS_2 */
  200. SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021
  201. >;
  202. };
  203. pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
  204. fsl,pins = <
  205. /* Apalis LCD1_G6 */
  206. SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021
  207. /* Apalis LCD1_G7 */
  208. SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021
  209. >;
  210. };
  211. pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
  212. fsl,pins = <
  213. /* Apalis TS_4 */
  214. SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021
  215. >;
  216. };
  217. pinctrl_mlb_gpios: mlbgpiosgrp {
  218. fsl,pins = <
  219. /* Apalis TS_1 */
  220. SC_P_MLB_CLK_LSIO_GPIO3_IO27 0x00000021
  221. >;
  222. };
  223. pinctrl_qspi1a_gpios: qspi1agpiosgrp {
  224. fsl,pins = <
  225. /* Apalis LCD1_B0 */
  226. SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
  227. /* Apalis LCD1_B1 */
  228. SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021
  229. /* Apalis LCD1_B2 */
  230. SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021
  231. /* Apalis LCD1_B3 */
  232. SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021
  233. /* Apalis LCD1_B5 */
  234. SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021
  235. /* Apalis LCD1_B7 */
  236. SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021
  237. /* Apalis LCD1_B4 */
  238. SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021
  239. /* Apalis LCD1_B6 */
  240. SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021
  241. >;
  242. };
  243. pinctrl_sim0_gpios: sim0gpiosgrp {
  244. fsl,pins = <
  245. /* Apalis LCD1_G5 */
  246. SC_P_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021
  247. /* Apalis LCD1_G3 */
  248. SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021
  249. /* Apalis TS_5 */
  250. SC_P_SIM0_IO_LSIO_GPIO0_IO02 0x00000021
  251. /* Apalis LCD1_G4 */
  252. SC_P_SIM0_RST_LSIO_GPIO0_IO01 0x00000021
  253. >;
  254. };
  255. pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
  256. fsl,pins = <
  257. /* Apalis TS_6 */
  258. SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021
  259. >;
  260. };
  261. pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en {
  262. fsl,pins = <
  263. /* Apalis TS_3 */
  264. SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021
  265. >;
  266. };
  267. /* On-module I2C */
  268. pinctrl_lpi2c1: lpi2c1grp {
  269. fsl,pins = <
  270. SC_P_GPT0_CLK_DMA_I2C1_SCL 0x04000020
  271. SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020
  272. >;
  273. };
  274. /* Apalis I2C1 */
  275. pinctrl_lpi2c2: lpi2c2grp {
  276. fsl,pins = <
  277. SC_P_GPT1_CLK_DMA_I2C2_SCL 0x04000020
  278. SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020
  279. >;
  280. };
  281. /* Apalis I2C3 (CAM) */
  282. pinctrl_lpi2c3: lpi2c3grp {
  283. fsl,pins = <
  284. SC_P_SIM0_PD_DMA_I2C3_SCL 0x04000020
  285. SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020
  286. >;
  287. };
  288. /* Apalis UART3 */
  289. pinctrl_lpuart0: lpuart0grp {
  290. fsl,pins = <
  291. SC_P_UART0_RX_DMA_UART0_RX 0x06000020
  292. SC_P_UART0_TX_DMA_UART0_TX 0x06000020
  293. >;
  294. };
  295. /* Apalis UART1 */
  296. pinctrl_lpuart1: lpuart1grp {
  297. fsl,pins = <
  298. SC_P_UART1_RX_DMA_UART1_RX 0x06000020
  299. SC_P_UART1_TX_DMA_UART1_TX 0x06000020
  300. SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
  301. SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
  302. >;
  303. };
  304. pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
  305. fsl,pins = <
  306. /* Apalis UART1_DTR */
  307. SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021
  308. /* Apalis UART1_DSR */
  309. SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021
  310. /* Apalis UART1_DCD */
  311. SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021
  312. /* Apalis UART1_RI */
  313. SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021
  314. >;
  315. };
  316. /* Apalis UART4 */
  317. pinctrl_lpuart2: lpuart2grp {
  318. fsl,pins = <
  319. SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020
  320. SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020
  321. >;
  322. };
  323. /* Apalis UART2 */
  324. pinctrl_lpuart3: lpuart3grp {
  325. fsl,pins = <
  326. SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020
  327. SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020
  328. SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020
  329. SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020
  330. >;
  331. };
  332. /* Apalis PWM3 */
  333. pinctrl_gpio_pwm0: gpiopwm0grp {
  334. fsl,pins = <
  335. SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 0x00000021
  336. >;
  337. };
  338. /* Apalis PWM4 */
  339. pinctrl_gpio_pwm1: gpiopwm1grp {
  340. fsl,pins = <
  341. SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 0x00000021
  342. >;
  343. };
  344. /* Apalis PWM1 */
  345. pinctrl_gpio_pwm2: gpiopwm2grp {
  346. fsl,pins = <
  347. SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 0x00000021
  348. >;
  349. };
  350. /* Apalis PWM2 */
  351. pinctrl_gpio_pwm3: gpiopwm3grp {
  352. fsl,pins = <
  353. SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 0x00000021
  354. >;
  355. };
  356. /* Apalis BKL1_PWM */
  357. pinctrl_gpio_pwm_bkl: gpiopwmbklgrp {
  358. fsl,pins = <
  359. SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 0x00000021
  360. >;
  361. };
  362. /* Apalis USBH_EN */
  363. pinctrl_gpio_usbh_en: gpiousbhen {
  364. fsl,pins = <
  365. SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x06000060
  366. >;
  367. };
  368. /* Apalis USBH_OC# */
  369. pinctrl_gpio_usbh_oc_n: gpiousbhocn {
  370. fsl,pins = <
  371. SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000060
  372. >;
  373. };
  374. /* Apalis USBO1_EN */
  375. pinctrl_gpio_usbo1_en: gpiousbo1en {
  376. fsl,pins = <
  377. SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000060
  378. >;
  379. };
  380. /* Apalis USBO1_OC# */
  381. pinctrl_gpio_usbo1_oc_n: gpiousbo1ocn {
  382. fsl,pins = <
  383. SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x06000060
  384. >;
  385. };
  386. pinctrl_usdhc1: usdhc1grp {
  387. fsl,pins = <
  388. SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
  389. SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
  390. SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
  391. SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
  392. SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
  393. SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
  394. SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
  395. SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
  396. SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
  397. SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
  398. SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
  399. SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
  400. >;
  401. };
  402. pinctrl_sata1_act: sata1actgrp {
  403. fsl,pins = <
  404. /* Apalis SATA1_ACT# */
  405. SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021
  406. >;
  407. };
  408. pinctrl_mmc1_cd: mmc1cdgrp {
  409. fsl,pins = <
  410. /* Apalis MMC1_CD# */
  411. SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021
  412. >;
  413. };
  414. pinctrl_usdhc2: usdhc2grp {
  415. fsl,pins = <
  416. SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
  417. SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
  418. SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
  419. SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
  420. SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
  421. SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
  422. SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021
  423. SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021
  424. SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021
  425. SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021
  426. /* On-module PMIC use */
  427. SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
  428. >;
  429. };
  430. pinctrl_sd1_cd: sd1cdgrp {
  431. fsl,pins = <
  432. /* Apalis SD1_CD# */
  433. SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
  434. >;
  435. };
  436. pinctrl_usdhc3: usdhc3grp {
  437. fsl,pins = <
  438. SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
  439. SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
  440. SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
  441. SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
  442. SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
  443. SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
  444. /* On-module PMIC use */
  445. SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
  446. >;
  447. };
  448. };
  449. };
  450. &fec1 {
  451. pinctrl-names = "default";
  452. pinctrl-0 = <&pinctrl_fec1>;
  453. fsl,magic-packet;
  454. phy-handle = <&ethphy0>;
  455. phy-mode = "rgmii-id";
  456. phy-reset-duration = <10>;
  457. phy-reset-gpios = <&gpio1 11 1>;
  458. status = "okay";
  459. mdio {
  460. #address-cells = <1>;
  461. #size-cells = <0>;
  462. ethphy0: ethernet-phy@7 {
  463. compatible = "ethernet-phy-ieee802.3-c22";
  464. reg = <7>;
  465. };
  466. };
  467. };
  468. /* Apalis I2C2 (DDC) */
  469. &i2c0 {
  470. #address-cells = <1>;
  471. #size-cells = <0>;
  472. pinctrl-names = "default";
  473. pinctrl-0 = <&pinctrl_lpi2c0>;
  474. clock-frequency = <100000>;
  475. status = "okay";
  476. };
  477. /* On-module I2C */
  478. &i2c1 {
  479. #address-cells = <1>;
  480. #size-cells = <0>;
  481. clock-frequency = <100000>;
  482. pinctrl-names = "default";
  483. pinctrl-0 = <&pinctrl_lpi2c1>;
  484. status = "okay";
  485. };
  486. /* Apalis I2C1 */
  487. &i2c2 {
  488. #address-cells = <1>;
  489. #size-cells = <0>;
  490. clock-frequency = <100000>;
  491. pinctrl-names = "default";
  492. pinctrl-0 = <&pinctrl_lpi2c2>;
  493. status = "okay";
  494. };
  495. /* Apalis I2C3 (CAM) */
  496. &i2c3 {
  497. #address-cells = <1>;
  498. #size-cells = <0>;
  499. clock-frequency = <100000>;
  500. pinctrl-names = "default";
  501. pinctrl-0 = <&pinctrl_lpi2c3>;
  502. status = "okay";
  503. };
  504. /* Apalis UART3 */
  505. &lpuart0 {
  506. pinctrl-names = "default";
  507. pinctrl-0 = <&pinctrl_lpuart0>;
  508. status = "okay";
  509. };
  510. /* Apalis UART1 */
  511. &lpuart1 {
  512. pinctrl-names = "default";
  513. pinctrl-0 = <&pinctrl_lpuart1>;
  514. status = "okay";
  515. };
  516. /* Apalis UART4 */
  517. &lpuart2 {
  518. pinctrl-names = "default";
  519. pinctrl-0 = <&pinctrl_lpuart2>;
  520. status = "okay";
  521. };
  522. /* Apalis UART2 */
  523. &lpuart3 {
  524. pinctrl-names = "default";
  525. pinctrl-0 = <&pinctrl_lpuart3>;
  526. status = "okay";
  527. };
  528. /* eMMC */
  529. &usdhc1 {
  530. pinctrl-names = "default";
  531. pinctrl-0 = <&pinctrl_usdhc1>;
  532. bus-width = <8>;
  533. non-removable;
  534. status = "okay";
  535. };
  536. /* Apalis MMC1 */
  537. &usdhc2 {
  538. pinctrl-names = "default";
  539. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
  540. bus-width = <8>;
  541. cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
  542. status = "okay";
  543. };
  544. /* Apalis SD1 */
  545. &usdhc3 {
  546. pinctrl-names = "default";
  547. pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
  548. bus-width = <4>;
  549. cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
  550. status = "okay";
  551. };