ag102.h 2.4 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Andes Technology Corporation
  4. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  5. */
  6. #ifndef __AG102_H
  7. #define __AG102_H
  8. /*
  9. * Hardware register bases
  10. */
  11. /* LPC Controller */
  12. #define CONFIG_LPC_IO_BASE 0x90100000
  13. /* LPC Controller */
  14. #define CONFIG_LPC_BASE 0x90200000
  15. /* NDS32 Data Local Memory 01 */
  16. #define CONFIG_NDS_DLM1_BASE 0x90300000
  17. /* NDS32 Data Local Memory 02 */
  18. #define CONFIG_NDS_DLM2_BASE 0x90400000
  19. /* Synopsys DWC DDR2/1 Controller */
  20. #define CONFIG_DWCDDR21MCTL_BASE 0x90500000
  21. /* DMA Controller */
  22. #define CONFIG_FTDMAC020_BASE 0x90600000
  23. /* FTIDE020_S IDE (ATA) Controller */
  24. #define CONFIG_FTIDE020S_BASE 0x90700000
  25. /* USB OTG Controller */
  26. #define CONFIG_FZOTG266HD0A_BASE 0x90800000
  27. /* Andes L2 Cache Controller */
  28. #define CONFIG_NCEL2C100_BASE 0x90900000
  29. /* XGI XG22 GPU */
  30. #define CONFIG_XGI_XG22_BASE 0x90A00000
  31. /* GMAC Ethernet Controller */
  32. #define CONFIG_FTGMAC100_BASE 0x90B00000
  33. /* AHB Controller */
  34. #define CONFIG_FTAHBC020S_BASE 0x90C00000
  35. /* AHB-to-APB Bridge Controller */
  36. #define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000
  37. /* External AHB2AHB Controller */
  38. #define CONFIG_EXT_AHB2AHB_BASE 0x90E00000
  39. /* Andes Multi-core Interrupt Controller */
  40. #define CONFIG_NCEMIC100_BASE 0x90F00000
  41. /*
  42. * APB Device definitions
  43. */
  44. /* Compat Flash Controller */
  45. #define CONFIG_FTCFC010_BASE 0x94000000
  46. /* APB - SSP (SPI) (without AC97) Controller */
  47. #define CONFIG_FTSSP010_01_BASE 0x94100000
  48. /* UART1 - APB STUART Controller (UART0 in Linux) */
  49. #define CONFIG_FTUART010_01_BASE 0x94200000
  50. /* APB - SSP with HDA/AC97 Controller */
  51. #define CONFIG_FTSSP010_02_BASE 0x94500000
  52. /* UART2 - APB STUART Controller (UART1 in Linux) */
  53. #define CONFIG_FTUART010_02_BASE 0x94600000
  54. /* PCU Controller */
  55. #define CONFIG_ANDES_PCU_BASE 0x94800000
  56. /* FTTMR010 Timer */
  57. #define CONFIG_FTTMR010_BASE 0x94900000
  58. /* Watch Dog Controller */
  59. #define CONFIG_FTWDT010_BASE 0x94A00000
  60. /* FTRTC010 Real Time Clock */
  61. #define CONFIG_FTRTC010_BASE 0x98B00000
  62. /* GPIO Controller */
  63. #define CONFIG_FTGPIO010_BASE 0x94C00000
  64. /* I2C Controller */
  65. #define CONFIG_FTIIC010_BASE 0x94E00000
  66. /* PWM - Pulse Width Modulator Controller */
  67. #define CONFIG_FTPWM010_BASE 0x94F00000
  68. /* Debug LED */
  69. #define CONFIG_DEBUG_LED 0x902FFFFC
  70. /* Power Management Unit */
  71. #define CONFIG_FTPMU010_BASE 0x98100000
  72. #endif /* __AG102_H */