baytrail_som-db5800-som-6867.dts 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289
  1. /*
  2. * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  3. * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /dts-v1/;
  8. #include <dt-bindings/gpio/x86-gpio.h>
  9. #include <dt-bindings/interrupt-router/intel-irq.h>
  10. /include/ "skeleton.dtsi"
  11. /include/ "serial.dtsi"
  12. /include/ "rtc.dtsi"
  13. /include/ "tsc_timer.dtsi"
  14. / {
  15. model = "Advantech SOM-DB5800-SOM-6867";
  16. compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
  17. aliases {
  18. serial0 = &serial;
  19. spi0 = &spi;
  20. };
  21. config {
  22. silent_console = <0>;
  23. };
  24. pch_pinctrl {
  25. compatible = "intel,x86-pinctrl";
  26. reg = <0 0>;
  27. /* HDA_RSTB */
  28. soc_gpio_s0_8@0 {
  29. pad-offset = <0x220>;
  30. mode-func = <2>;
  31. };
  32. /* HDA_SYNC */
  33. soc_gpio_s0_9@0 {
  34. pad-offset = <0x250>;
  35. mode-func = <2>;
  36. pull-assign = <1>;
  37. };
  38. /* HDA_CLK */
  39. soc_gpio_s0_10@0 {
  40. pad-offset = <0x240>;
  41. mode-func = <2>;
  42. };
  43. /* HDA_SDO */
  44. soc_gpio_s0_11@0 {
  45. pad-offset = <0x260>;
  46. mode-func = <2>;
  47. pull-assign = <1>;
  48. };
  49. /* HDA_SDI0 */
  50. soc_gpio_s0_12@0 {
  51. pad-offset = <0x270>;
  52. mode-func = <2>;
  53. };
  54. };
  55. chosen {
  56. stdout-path = "/serial";
  57. };
  58. cpus {
  59. #address-cells = <1>;
  60. #size-cells = <0>;
  61. cpu@0 {
  62. device_type = "cpu";
  63. compatible = "intel,baytrail-cpu";
  64. reg = <0>;
  65. intel,apic-id = <0>;
  66. };
  67. cpu@1 {
  68. device_type = "cpu";
  69. compatible = "intel,baytrail-cpu";
  70. reg = <1>;
  71. intel,apic-id = <2>;
  72. };
  73. cpu@2 {
  74. device_type = "cpu";
  75. compatible = "intel,baytrail-cpu";
  76. reg = <2>;
  77. intel,apic-id = <4>;
  78. };
  79. cpu@3 {
  80. device_type = "cpu";
  81. compatible = "intel,baytrail-cpu";
  82. reg = <3>;
  83. intel,apic-id = <6>;
  84. };
  85. };
  86. pci {
  87. compatible = "intel,pci-baytrail", "pci-x86";
  88. #address-cells = <3>;
  89. #size-cells = <2>;
  90. u-boot,dm-pre-reloc;
  91. ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
  92. 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  93. 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  94. pch@1f,0 {
  95. reg = <0x0000f800 0 0 0 0>;
  96. compatible = "pci8086,0f1c", "intel,pch9";
  97. #address-cells = <1>;
  98. #size-cells = <1>;
  99. irq-router {
  100. compatible = "intel,irq-router";
  101. intel,pirq-config = "ibase";
  102. intel,ibase-offset = <0x50>;
  103. intel,actl-addr = <0>;
  104. intel,pirq-link = <8 8>;
  105. intel,pirq-mask = <0xdee0>;
  106. intel,pirq-routing = <
  107. /* BayTrail PCI devices */
  108. PCI_BDF(0, 2, 0) INTA PIRQA
  109. PCI_BDF(0, 3, 0) INTA PIRQA
  110. PCI_BDF(0, 16, 0) INTA PIRQA
  111. PCI_BDF(0, 17, 0) INTA PIRQA
  112. PCI_BDF(0, 18, 0) INTA PIRQA
  113. PCI_BDF(0, 19, 0) INTA PIRQA
  114. PCI_BDF(0, 20, 0) INTA PIRQA
  115. PCI_BDF(0, 21, 0) INTA PIRQA
  116. PCI_BDF(0, 22, 0) INTA PIRQA
  117. PCI_BDF(0, 23, 0) INTA PIRQA
  118. PCI_BDF(0, 24, 0) INTA PIRQA
  119. PCI_BDF(0, 24, 1) INTC PIRQC
  120. PCI_BDF(0, 24, 2) INTD PIRQD
  121. PCI_BDF(0, 24, 3) INTB PIRQB
  122. PCI_BDF(0, 24, 4) INTA PIRQA
  123. PCI_BDF(0, 24, 5) INTC PIRQC
  124. PCI_BDF(0, 24, 6) INTD PIRQD
  125. PCI_BDF(0, 24, 7) INTB PIRQB
  126. PCI_BDF(0, 26, 0) INTA PIRQA
  127. PCI_BDF(0, 27, 0) INTA PIRQA
  128. PCI_BDF(0, 28, 0) INTA PIRQA
  129. PCI_BDF(0, 28, 1) INTB PIRQB
  130. PCI_BDF(0, 28, 2) INTC PIRQC
  131. PCI_BDF(0, 28, 3) INTD PIRQD
  132. PCI_BDF(0, 29, 0) INTA PIRQA
  133. PCI_BDF(0, 30, 0) INTA PIRQA
  134. PCI_BDF(0, 30, 1) INTD PIRQD
  135. PCI_BDF(0, 30, 2) INTB PIRQB
  136. PCI_BDF(0, 30, 3) INTC PIRQC
  137. PCI_BDF(0, 30, 4) INTD PIRQD
  138. PCI_BDF(0, 30, 5) INTB PIRQB
  139. PCI_BDF(0, 31, 3) INTB PIRQB
  140. /*
  141. * PCIe root ports downstream
  142. * interrupts
  143. */
  144. PCI_BDF(1, 0, 0) INTA PIRQA
  145. PCI_BDF(1, 0, 0) INTB PIRQB
  146. PCI_BDF(1, 0, 0) INTC PIRQC
  147. PCI_BDF(1, 0, 0) INTD PIRQD
  148. PCI_BDF(2, 0, 0) INTA PIRQB
  149. PCI_BDF(2, 0, 0) INTB PIRQC
  150. PCI_BDF(2, 0, 0) INTC PIRQD
  151. PCI_BDF(2, 0, 0) INTD PIRQA
  152. PCI_BDF(3, 0, 0) INTA PIRQC
  153. PCI_BDF(3, 0, 0) INTB PIRQD
  154. PCI_BDF(3, 0, 0) INTC PIRQA
  155. PCI_BDF(3, 0, 0) INTD PIRQB
  156. PCI_BDF(4, 0, 0) INTA PIRQD
  157. PCI_BDF(4, 0, 0) INTB PIRQA
  158. PCI_BDF(4, 0, 0) INTC PIRQB
  159. PCI_BDF(4, 0, 0) INTD PIRQC
  160. >;
  161. };
  162. spi: spi {
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. compatible = "intel,ich9-spi";
  166. spi-flash@0 {
  167. #address-cells = <1>;
  168. #size-cells = <1>;
  169. reg = <0>;
  170. compatible = "macronix,mx25l6405d",
  171. "spi-flash";
  172. memory-map = <0xff800000 0x00800000>;
  173. rw-mrc-cache {
  174. label = "rw-mrc-cache";
  175. reg = <0x006f0000 0x00010000>;
  176. };
  177. };
  178. };
  179. gpioa {
  180. compatible = "intel,ich6-gpio";
  181. u-boot,dm-pre-reloc;
  182. reg = <0 0x20>;
  183. bank-name = "A";
  184. };
  185. gpiob {
  186. compatible = "intel,ich6-gpio";
  187. u-boot,dm-pre-reloc;
  188. reg = <0x20 0x20>;
  189. bank-name = "B";
  190. };
  191. gpioc {
  192. compatible = "intel,ich6-gpio";
  193. u-boot,dm-pre-reloc;
  194. reg = <0x40 0x20>;
  195. bank-name = "C";
  196. };
  197. gpiod {
  198. compatible = "intel,ich6-gpio";
  199. u-boot,dm-pre-reloc;
  200. reg = <0x60 0x20>;
  201. bank-name = "D";
  202. };
  203. gpioe {
  204. compatible = "intel,ich6-gpio";
  205. u-boot,dm-pre-reloc;
  206. reg = <0x80 0x20>;
  207. bank-name = "E";
  208. };
  209. gpiof {
  210. compatible = "intel,ich6-gpio";
  211. u-boot,dm-pre-reloc;
  212. reg = <0xA0 0x20>;
  213. bank-name = "F";
  214. };
  215. };
  216. };
  217. fsp {
  218. compatible = "intel,baytrail-fsp";
  219. fsp,mrc-init-tseg-size = <0>;
  220. fsp,mrc-init-mmio-size = <0x800>;
  221. fsp,mrc-init-spd-addr1 = <0xa0>;
  222. fsp,mrc-init-spd-addr2 = <0xa2>;
  223. fsp,enable-spi;
  224. fsp,enable-sata;
  225. fsp,sata-mode = <1>;
  226. fsp,enable-azalia;
  227. fsp,lpss-sio-enable-pci-mode;
  228. fsp,enable-dma0;
  229. fsp,enable-dma1;
  230. fsp,enable-i2c0;
  231. fsp,enable-i2c1;
  232. fsp,enable-i2c2;
  233. fsp,enable-i2c3;
  234. fsp,enable-i2c4;
  235. fsp,enable-i2c5;
  236. fsp,enable-i2c6;
  237. fsp,enable-pwm0;
  238. fsp,enable-pwm1;
  239. fsp,igd-dvmt50-pre-alloc = <2>;
  240. fsp,aperture-size = <2>;
  241. fsp,gtt-size = <2>;
  242. fsp,scc-enable-pci-mode;
  243. fsp,os-selection = <4>;
  244. fsp,enable-igd;
  245. fsp,serial-debug-port-address = <0x3f8>;
  246. fsp,serial-debug-port-type = <1>;
  247. };
  248. microcode {
  249. update@0 {
  250. #include "microcode/m0130673325.dtsi"
  251. };
  252. update@1 {
  253. #include "microcode/m0130679907.dtsi"
  254. };
  255. };
  256. };