Kconfig 17 KB

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  1. menu "x86 architecture"
  2. depends on X86
  3. config SYS_ARCH
  4. default "x86"
  5. choice
  6. prompt "Mainboard vendor"
  7. default VENDOR_EMULATION
  8. config VENDOR_ADVANTECH
  9. bool "advantech"
  10. config VENDOR_CONGATEC
  11. bool "congatec"
  12. config VENDOR_COREBOOT
  13. bool "coreboot"
  14. config VENDOR_EFI
  15. bool "efi"
  16. config VENDOR_EMULATION
  17. bool "emulation"
  18. config VENDOR_GOOGLE
  19. bool "Google"
  20. config VENDOR_INTEL
  21. bool "Intel"
  22. endchoice
  23. # board-specific options below
  24. source "board/advantech/Kconfig"
  25. source "board/congatec/Kconfig"
  26. source "board/coreboot/Kconfig"
  27. source "board/efi/Kconfig"
  28. source "board/emulation/Kconfig"
  29. source "board/google/Kconfig"
  30. source "board/intel/Kconfig"
  31. # platform-specific options below
  32. source "arch/x86/cpu/baytrail/Kconfig"
  33. source "arch/x86/cpu/broadwell/Kconfig"
  34. source "arch/x86/cpu/coreboot/Kconfig"
  35. source "arch/x86/cpu/ivybridge/Kconfig"
  36. source "arch/x86/cpu/qemu/Kconfig"
  37. source "arch/x86/cpu/quark/Kconfig"
  38. source "arch/x86/cpu/queensbay/Kconfig"
  39. # architecture-specific options below
  40. config AHCI
  41. default y
  42. config SYS_MALLOC_F_LEN
  43. default 0x800
  44. config RAMBASE
  45. hex
  46. default 0x100000
  47. config XIP_ROM_SIZE
  48. hex
  49. depends on X86_RESET_VECTOR
  50. default ROM_SIZE
  51. config CPU_ADDR_BITS
  52. int
  53. default 36
  54. config HPET_ADDRESS
  55. hex
  56. default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
  57. config SMM_TSEG
  58. bool
  59. default n
  60. config SMM_TSEG_SIZE
  61. hex
  62. config X86_RESET_VECTOR
  63. bool
  64. default n
  65. config RESET_SEG_START
  66. hex
  67. depends on X86_RESET_VECTOR
  68. default 0xffff0000
  69. config RESET_SEG_SIZE
  70. hex
  71. depends on X86_RESET_VECTOR
  72. default 0x10000
  73. config RESET_VEC_LOC
  74. hex
  75. depends on X86_RESET_VECTOR
  76. default 0xfffffff0
  77. config SYS_X86_START16
  78. hex
  79. depends on X86_RESET_VECTOR
  80. default 0xfffff800
  81. config BOARD_ROMSIZE_KB_512
  82. bool
  83. config BOARD_ROMSIZE_KB_1024
  84. bool
  85. config BOARD_ROMSIZE_KB_2048
  86. bool
  87. config BOARD_ROMSIZE_KB_4096
  88. bool
  89. config BOARD_ROMSIZE_KB_8192
  90. bool
  91. config BOARD_ROMSIZE_KB_16384
  92. bool
  93. choice
  94. prompt "ROM chip size"
  95. depends on X86_RESET_VECTOR
  96. default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
  97. default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
  98. default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
  99. default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
  100. default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
  101. default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
  102. help
  103. Select the size of the ROM chip you intend to flash U-Boot on.
  104. The build system will take care of creating a u-boot.rom file
  105. of the matching size.
  106. config UBOOT_ROMSIZE_KB_512
  107. bool "512 KB"
  108. help
  109. Choose this option if you have a 512 KB ROM chip.
  110. config UBOOT_ROMSIZE_KB_1024
  111. bool "1024 KB (1 MB)"
  112. help
  113. Choose this option if you have a 1024 KB (1 MB) ROM chip.
  114. config UBOOT_ROMSIZE_KB_2048
  115. bool "2048 KB (2 MB)"
  116. help
  117. Choose this option if you have a 2048 KB (2 MB) ROM chip.
  118. config UBOOT_ROMSIZE_KB_4096
  119. bool "4096 KB (4 MB)"
  120. help
  121. Choose this option if you have a 4096 KB (4 MB) ROM chip.
  122. config UBOOT_ROMSIZE_KB_8192
  123. bool "8192 KB (8 MB)"
  124. help
  125. Choose this option if you have a 8192 KB (8 MB) ROM chip.
  126. config UBOOT_ROMSIZE_KB_16384
  127. bool "16384 KB (16 MB)"
  128. help
  129. Choose this option if you have a 16384 KB (16 MB) ROM chip.
  130. endchoice
  131. # Map the config names to an integer (KB).
  132. config UBOOT_ROMSIZE_KB
  133. int
  134. default 512 if UBOOT_ROMSIZE_KB_512
  135. default 1024 if UBOOT_ROMSIZE_KB_1024
  136. default 2048 if UBOOT_ROMSIZE_KB_2048
  137. default 4096 if UBOOT_ROMSIZE_KB_4096
  138. default 8192 if UBOOT_ROMSIZE_KB_8192
  139. default 16384 if UBOOT_ROMSIZE_KB_16384
  140. # Map the config names to a hex value (bytes).
  141. config ROM_SIZE
  142. hex
  143. default 0x80000 if UBOOT_ROMSIZE_KB_512
  144. default 0x100000 if UBOOT_ROMSIZE_KB_1024
  145. default 0x200000 if UBOOT_ROMSIZE_KB_2048
  146. default 0x400000 if UBOOT_ROMSIZE_KB_4096
  147. default 0x800000 if UBOOT_ROMSIZE_KB_8192
  148. default 0xc00000 if UBOOT_ROMSIZE_KB_12288
  149. default 0x1000000 if UBOOT_ROMSIZE_KB_16384
  150. config HAVE_INTEL_ME
  151. bool "Platform requires Intel Management Engine"
  152. help
  153. Newer higher-end devices have an Intel Management Engine (ME)
  154. which is a very large binary blob (typically 1.5MB) which is
  155. required for the platform to work. This enforces a particular
  156. SPI flash format. You will need to supply the me.bin file in
  157. your board directory.
  158. config X86_RAMTEST
  159. bool "Perform a simple RAM test after SDRAM initialisation"
  160. help
  161. If there is something wrong with SDRAM then the platform will
  162. often crash within U-Boot or the kernel. This option enables a
  163. very simple RAM test that quickly checks whether the SDRAM seems
  164. to work correctly. It is not exhaustive but can save time by
  165. detecting obvious failures.
  166. config HAVE_FSP
  167. bool "Add an Firmware Support Package binary"
  168. depends on !EFI
  169. help
  170. Select this option to add an Firmware Support Package binary to
  171. the resulting U-Boot image. It is a binary blob which U-Boot uses
  172. to set up SDRAM and other chipset specific initialization.
  173. Note: Without this binary U-Boot will not be able to set up its
  174. SDRAM so will not boot.
  175. config FSP_FILE
  176. string "Firmware Support Package binary filename"
  177. depends on HAVE_FSP
  178. default "fsp.bin"
  179. help
  180. The filename of the file to use as Firmware Support Package binary
  181. in the board directory.
  182. config FSP_ADDR
  183. hex "Firmware Support Package binary location"
  184. depends on HAVE_FSP
  185. default 0xfffc0000
  186. help
  187. FSP is not Position Independent Code (PIC) and the whole FSP has to
  188. be rebased if it is placed at a location which is different from the
  189. perferred base address specified during the FSP build. Use Intel's
  190. Binary Configuration Tool (BCT) to do the rebase.
  191. The default base address of 0xfffc0000 indicates that the binary must
  192. be located at offset 0xc0000 from the beginning of a 1MB flash device.
  193. config FSP_TEMP_RAM_ADDR
  194. hex
  195. depends on HAVE_FSP
  196. default 0x2000000
  197. help
  198. Stack top address which is used in fsp_init() after DRAM is ready and
  199. CAR is disabled.
  200. config FSP_SYS_MALLOC_F_LEN
  201. hex
  202. depends on HAVE_FSP
  203. default 0x100000
  204. help
  205. Additional size of malloc() pool before relocation.
  206. config FSP_USE_UPD
  207. bool
  208. depends on HAVE_FSP
  209. default y
  210. help
  211. Most FSPs use UPD data region for some FSP customization. But there
  212. are still some FSPs that might not even have UPD. For such FSPs,
  213. override this to n in their platform Kconfig files.
  214. config FSP_BROKEN_HOB
  215. bool
  216. depends on HAVE_FSP
  217. help
  218. Indicate some buggy FSPs that does not report memory used by FSP
  219. itself as reserved in the resource descriptor HOB. Select this to
  220. tell U-Boot to do some additional work to ensure U-Boot relocation
  221. do not overwrite the important boot service data which is used by
  222. FSP, otherwise the subsequent call to fsp_notify() will fail.
  223. config ENABLE_MRC_CACHE
  224. bool "Enable MRC cache"
  225. depends on !EFI && !SYS_COREBOOT
  226. help
  227. Enable this feature to cause MRC data to be cached in NV storage
  228. to be used for speeding up boot time on future reboots and/or
  229. power cycles.
  230. For platforms that use Intel FSP for the memory initialization,
  231. please check FSP output HOB via U-Boot command 'fsp hob' to see
  232. if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
  233. If such GUID does not exist, MRC cache is not avaiable on such
  234. platform (eg: Intel Queensbay), which means selecting this option
  235. here does not make any difference.
  236. config HAVE_MRC
  237. bool "Add a System Agent binary"
  238. depends on !HAVE_FSP
  239. help
  240. Select this option to add a System Agent binary to
  241. the resulting U-Boot image. MRC stands for Memory Reference Code.
  242. It is a binary blob which U-Boot uses to set up SDRAM.
  243. Note: Without this binary U-Boot will not be able to set up its
  244. SDRAM so will not boot.
  245. config CACHE_MRC_BIN
  246. bool
  247. depends on HAVE_MRC
  248. default n
  249. help
  250. Enable caching for the memory reference code binary. This uses an
  251. MTRR (memory type range register) to turn on caching for the section
  252. of SPI flash that contains the memory reference code. This makes
  253. SDRAM init run faster.
  254. config CACHE_MRC_SIZE_KB
  255. int
  256. depends on HAVE_MRC
  257. default 512
  258. help
  259. Sets the size of the cached area for the memory reference code.
  260. This ends at the end of SPI flash (address 0xffffffff) and is
  261. measured in KB. Typically this is set to 512, providing for 0.5MB
  262. of cached space.
  263. config DCACHE_RAM_BASE
  264. hex
  265. depends on HAVE_MRC
  266. help
  267. Sets the base of the data cache area in memory space. This is the
  268. start address of the cache-as-RAM (CAR) area and the address varies
  269. depending on the CPU. Once CAR is set up, read/write memory becomes
  270. available at this address and can be used temporarily until SDRAM
  271. is working.
  272. config DCACHE_RAM_SIZE
  273. hex
  274. depends on HAVE_MRC
  275. default 0x40000
  276. help
  277. Sets the total size of the data cache area in memory space. This
  278. sets the size of the cache-as-RAM (CAR) area. Note that much of the
  279. CAR space is required by the MRC. The CAR space available to U-Boot
  280. is normally at the start and typically extends to 1/4 or 1/2 of the
  281. available size.
  282. config DCACHE_RAM_MRC_VAR_SIZE
  283. hex
  284. depends on HAVE_MRC
  285. help
  286. This is the amount of CAR (Cache as RAM) reserved for use by the
  287. memory reference code. This depends on the implementation of the
  288. memory reference code and must be set correctly or the board will
  289. not boot.
  290. config HAVE_REFCODE
  291. bool "Add a Reference Code binary"
  292. help
  293. Select this option to add a Reference Code binary to the resulting
  294. U-Boot image. This is an Intel binary blob that handles system
  295. initialisation, in this case the PCH and System Agent.
  296. Note: Without this binary (on platforms that need it such as
  297. broadwell) U-Boot will be missing some critical setup steps.
  298. Various peripherals may fail to work.
  299. config SMP
  300. bool "Enable Symmetric Multiprocessing"
  301. default n
  302. help
  303. Enable use of more than one CPU in U-Boot and the Operating System
  304. when loaded. Each CPU will be started up and information can be
  305. obtained using the 'cpu' command. If this option is disabled, then
  306. only one CPU will be enabled regardless of the number of CPUs
  307. available.
  308. config MAX_CPUS
  309. int "Maximum number of CPUs permitted"
  310. depends on SMP
  311. default 4
  312. help
  313. When using multi-CPU chips it is possible for U-Boot to start up
  314. more than one CPU. The stack memory used by all of these CPUs is
  315. pre-allocated so at present U-Boot wants to know the maximum
  316. number of CPUs that may be present. Set this to at least as high
  317. as the number of CPUs in your system (it uses about 4KB of RAM for
  318. each CPU).
  319. config AP_STACK_SIZE
  320. hex
  321. depends on SMP
  322. default 0x1000
  323. help
  324. Each additional CPU started by U-Boot requires its own stack. This
  325. option sets the stack size used by each CPU and directly affects
  326. the memory used by this initialisation process. Typically 4KB is
  327. enough space.
  328. config HAVE_VGA_BIOS
  329. bool "Add a VGA BIOS image"
  330. help
  331. Select this option if you have a VGA BIOS image that you would
  332. like to add to your ROM.
  333. config VGA_BIOS_FILE
  334. string "VGA BIOS image filename"
  335. depends on HAVE_VGA_BIOS
  336. default "vga.bin"
  337. help
  338. The filename of the VGA BIOS image in the board directory.
  339. config VGA_BIOS_ADDR
  340. hex "VGA BIOS image location"
  341. depends on HAVE_VGA_BIOS
  342. default 0xfff90000
  343. help
  344. The location of VGA BIOS image in the SPI flash. For example, base
  345. address of 0xfff90000 indicates that the image will be put at offset
  346. 0x90000 from the beginning of a 1MB flash device.
  347. menu "System tables"
  348. depends on !EFI && !SYS_COREBOOT
  349. config GENERATE_PIRQ_TABLE
  350. bool "Generate a PIRQ table"
  351. default n
  352. help
  353. Generate a PIRQ routing table for this board. The PIRQ routing table
  354. is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
  355. at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
  356. It specifies the interrupt router information as well how all the PCI
  357. devices' interrupt pins are wired to PIRQs.
  358. config GENERATE_SFI_TABLE
  359. bool "Generate a SFI (Simple Firmware Interface) table"
  360. help
  361. The Simple Firmware Interface (SFI) provides a lightweight method
  362. for platform firmware to pass information to the operating system
  363. via static tables in memory. Kernel SFI support is required to
  364. boot on SFI-only platforms. If you have ACPI tables then these are
  365. used instead.
  366. U-Boot writes this table in write_sfi_table() just before booting
  367. the OS.
  368. For more information, see http://simplefirmware.org
  369. config GENERATE_MP_TABLE
  370. bool "Generate an MP (Multi-Processor) table"
  371. default n
  372. help
  373. Generate an MP (Multi-Processor) table for this board. The MP table
  374. provides a way for the operating system to support for symmetric
  375. multiprocessing as well as symmetric I/O interrupt handling with
  376. the local APIC and I/O APIC.
  377. config GENERATE_ACPI_TABLE
  378. bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
  379. default n
  380. select QFW if QEMU
  381. help
  382. The Advanced Configuration and Power Interface (ACPI) specification
  383. provides an open standard for device configuration and management
  384. by the operating system. It defines platform-independent interfaces
  385. for configuration and power management monitoring.
  386. config GENERATE_SMBIOS_TABLE
  387. bool "Generate an SMBIOS (System Management BIOS) table"
  388. default y
  389. help
  390. The System Management BIOS (SMBIOS) specification addresses how
  391. motherboard and system vendors present management information about
  392. their products in a standard format by extending the BIOS interface
  393. on Intel architecture systems.
  394. Check http://www.dmtf.org/standards/smbios for details.
  395. config SMBIOS_MANUFACTURER
  396. string "SMBIOS Manufacturer"
  397. depends on GENERATE_SMBIOS_TABLE
  398. default SYS_VENDOR
  399. help
  400. The board manufacturer to store in SMBIOS structures.
  401. Change this to override the default one (CONFIG_SYS_VENDOR).
  402. config SMBIOS_PRODUCT_NAME
  403. string "SMBIOS Product Name"
  404. depends on GENERATE_SMBIOS_TABLE
  405. default SYS_BOARD
  406. help
  407. The product name to store in SMBIOS structures.
  408. Change this to override the default one (CONFIG_SYS_BOARD).
  409. endmenu
  410. config MAX_PIRQ_LINKS
  411. int
  412. default 8
  413. help
  414. This variable specifies the number of PIRQ interrupt links which are
  415. routable. On most older chipsets, this is 4, PIRQA through PIRQD.
  416. Some newer chipsets offer more than four links, commonly up to PIRQH.
  417. config IRQ_SLOT_COUNT
  418. int
  419. default 128
  420. help
  421. U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
  422. which in turns forms a table of exact 4KiB. The default value 128
  423. should be enough for most boards. If this does not fit your board,
  424. change it according to your needs.
  425. config PCIE_ECAM_BASE
  426. hex
  427. default 0xe0000000
  428. help
  429. This is the memory-mapped address of PCI configuration space, which
  430. is only available through the Enhanced Configuration Access
  431. Mechanism (ECAM) with PCI Express. It can be set up almost
  432. anywhere. Before it is set up, it is possible to access PCI
  433. configuration space through I/O access, but memory access is more
  434. convenient. Using this, PCI can be scanned and configured. This
  435. should be set to a region that does not conflict with memory
  436. assigned to PCI devices - i.e. the memory and prefetch regions, as
  437. passed to pci_set_region().
  438. config PCIE_ECAM_SIZE
  439. hex
  440. default 0x10000000
  441. help
  442. This is the size of memory-mapped address of PCI configuration space,
  443. which is only available through the Enhanced Configuration Access
  444. Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
  445. so a default 0x10000000 size covers all of the 256 buses which is the
  446. maximum number of PCI buses as defined by the PCI specification.
  447. config I8259_PIC
  448. bool
  449. default y
  450. help
  451. Intel 8259 ISA compatible chipset incorporates two 8259 (master and
  452. slave) interrupt controllers. Include this to have U-Boot set up
  453. the interrupt correctly.
  454. config I8254_TIMER
  455. bool
  456. default y
  457. help
  458. Intel 8254 timer contains three counters which have fixed uses.
  459. Include this to have U-Boot set up the timer correctly.
  460. config I8042_KEYB
  461. default y
  462. config DM_KEYBOARD
  463. default y
  464. config SEABIOS
  465. bool "Support booting SeaBIOS"
  466. help
  467. SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
  468. It can run in an emulator or natively on X86 hardware with the use
  469. of coreboot/U-Boot. By turning on this option, U-Boot prepares
  470. all the configuration tables that are necessary to boot SeaBIOS.
  471. Check http://www.seabios.org/SeaBIOS for details.
  472. config HIGH_TABLE_SIZE
  473. hex "Size of configuration tables which reside in high memory"
  474. default 0x10000
  475. depends on SEABIOS
  476. help
  477. SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
  478. configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
  479. puts a copy of configuration tables in high memory region which
  480. is reserved on the stack before relocation. The region size is
  481. determined by this option.
  482. Increse it if the default size does not fit the board's needs.
  483. This is most likely due to a large ACPI DSDT table is used.
  484. source "arch/x86/lib/efi/Kconfig"
  485. endmenu