ohci-lpc32xx.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008 by NXP Semiconductors
  4. * @Author: Based on code by Kevin Wells
  5. * @Descr: USB driver - Embedded Artists LPC3250 OEM Board support functions
  6. *
  7. * Copyright (c) 2015 Tyco Fire Protection Products.
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <wait_bit.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/clk.h>
  18. #include <asm/arch/i2c.h>
  19. #include <usb.h>
  20. #include <i2c.h>
  21. /* OTG I2C controller module register structures */
  22. struct otgi2c_regs {
  23. u32 otg_i2c_txrx; /* OTG I2C Tx/Rx Data FIFO */
  24. u32 otg_i2c_stat; /* OTG I2C Status Register */
  25. u32 otg_i2c_ctrl; /* OTG I2C Control Register */
  26. u32 otg_i2c_clk_hi; /* OTG I2C Clock Divider high */
  27. u32 otg_i2c_clk_lo; /* OTG I2C Clock Divider low */
  28. };
  29. /* OTG controller module register structures */
  30. struct otg_regs {
  31. u32 reserved1[64];
  32. u32 otg_int_sts; /* OTG int status register */
  33. u32 otg_int_enab; /* OTG int enable register */
  34. u32 otg_int_set; /* OTG int set register */
  35. u32 otg_int_clr; /* OTG int clear register */
  36. u32 otg_sts_ctrl; /* OTG status/control register */
  37. u32 otg_timer; /* OTG timer register */
  38. u32 reserved2[122];
  39. struct otgi2c_regs otg_i2c;
  40. u32 reserved3[824];
  41. u32 otg_clk_ctrl; /* OTG clock control reg */
  42. u32 otg_clk_sts; /* OTG clock status reg */
  43. };
  44. /* otg_sts_ctrl register definitions */
  45. #define OTG_HOST_EN (1 << 0) /* Enable host mode */
  46. /* otg_clk_ctrl and otg_clk_sts register definitions */
  47. #define OTG_CLK_AHB_EN (1 << 4) /* Enable AHB clock */
  48. #define OTG_CLK_OTG_EN (1 << 3) /* Enable OTG clock */
  49. #define OTG_CLK_I2C_EN (1 << 2) /* Enable I2C clock */
  50. #define OTG_CLK_HOST_EN (1 << 0) /* Enable host clock */
  51. /* ISP1301 USB transceiver I2C registers */
  52. #define MC1_SPEED_REG (1 << 0)
  53. #define MC1_DAT_SE0 (1 << 2)
  54. #define MC1_UART_EN (1 << 6)
  55. #define MC2_SPD_SUSP_CTRL (1 << 1)
  56. #define MC2_BI_DI (1 << 2)
  57. #define MC2_PSW_EN (1 << 6)
  58. #define OTG1_DP_PULLUP (1 << 0)
  59. #define OTG1_DM_PULLUP (1 << 1)
  60. #define OTG1_DP_PULLDOWN (1 << 2)
  61. #define OTG1_DM_PULLDOWN (1 << 3)
  62. #define OTG1_VBUS_DRV (1 << 5)
  63. #define ISP1301_I2C_ADDR CONFIG_USB_ISP1301_I2C_ADDR
  64. #define ISP1301_I2C_MODE_CONTROL_1_SET 0x04
  65. #define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05
  66. #define ISP1301_I2C_MODE_CONTROL_2_SET 0x12
  67. #define ISP1301_I2C_MODE_CONTROL_2_CLR 0x13
  68. #define ISP1301_I2C_OTG_CONTROL_1_SET 0x06
  69. #define ISP1301_I2C_OTG_CONTROL_1_CLR 0x07
  70. #define ISP1301_I2C_INTERRUPT_LATCH_CLR 0x0B
  71. #define ISP1301_I2C_INTERRUPT_FALLING_CLR 0x0D
  72. #define ISP1301_I2C_INTERRUPT_RISING_CLR 0x0F
  73. static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
  74. static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
  75. static int isp1301_set_value(struct udevice *dev, int reg, u8 value)
  76. {
  77. #if !CONFIG_IS_ENABLED(DM_I2C)
  78. return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1);
  79. #else
  80. return dm_i2c_write(dev, reg, &value, 1);
  81. #endif
  82. }
  83. static void isp1301_configure(struct udevice *dev)
  84. {
  85. #if !CONFIG_IS_ENABLED(DM_I2C)
  86. i2c_set_bus_num(I2C_2);
  87. #endif
  88. /*
  89. * LPC32XX only supports DAT_SE0 USB mode
  90. * This sequence is important
  91. */
  92. /* Disable transparent UART mode first */
  93. isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
  94. isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
  95. isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
  96. isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
  97. isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET,
  98. MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
  99. isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
  100. isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
  101. isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET,
  102. OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
  103. isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR,
  104. OTG1_DM_PULLUP | OTG1_DP_PULLUP);
  105. isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
  106. isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
  107. isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
  108. /* Enable usb_need_clk clock after transceiver is initialized */
  109. setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
  110. }
  111. static int usbpll_setup(void)
  112. {
  113. u32 ret;
  114. /* make sure clocks are disabled */
  115. clrbits_le32(&clk_pwr->usb_ctrl,
  116. CLK_USBCTRL_CLK_EN1 | CLK_USBCTRL_CLK_EN2);
  117. /* start PLL clock input */
  118. setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1);
  119. /* Setup PLL. */
  120. setbits_le32(&clk_pwr->usb_ctrl,
  121. CLK_USBCTRL_FDBK_PLUS1(192 - 1));
  122. setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01));
  123. setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP);
  124. ret = wait_for_bit_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
  125. true, CONFIG_SYS_HZ, false);
  126. if (ret)
  127. return ret;
  128. /* enable PLL output */
  129. setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2);
  130. return 0;
  131. }
  132. int usb_cpu_init(void)
  133. {
  134. u32 ret;
  135. struct udevice *dev = NULL;
  136. #if CONFIG_IS_ENABLED(DM_I2C)
  137. ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
  138. if (ret) {
  139. debug("%s: No bus %d\n", __func__, I2C_2);
  140. return ret;
  141. }
  142. #endif
  143. /*
  144. * USB pins routing setup is done by "lpc32xx_usb_init()" and should
  145. * be call by board "board_init()" or "misc_init_r()" functions.
  146. */
  147. /* enable AHB slave USB clock */
  148. setbits_le32(&clk_pwr->usb_ctrl,
  149. CLK_USBCTRL_HCLK_EN | CLK_USBCTRL_BUS_KEEPER);
  150. /* enable I2C clock */
  151. writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl);
  152. ret = wait_for_bit_le32(&otg->otg_clk_sts, OTG_CLK_I2C_EN, true,
  153. CONFIG_SYS_HZ, false);
  154. if (ret)
  155. return ret;
  156. /* Configure ISP1301 */
  157. isp1301_configure(dev);
  158. /* setup USB clocks and PLL */
  159. ret = usbpll_setup();
  160. if (ret)
  161. return ret;
  162. /* enable usb_host_need_clk */
  163. setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN);
  164. /* enable all needed USB clocks */
  165. const u32 mask = OTG_CLK_AHB_EN | OTG_CLK_OTG_EN |
  166. OTG_CLK_I2C_EN | OTG_CLK_HOST_EN;
  167. writel(mask, &otg->otg_clk_ctrl);
  168. ret = wait_for_bit_le32(&otg->otg_clk_sts, mask, true,
  169. CONFIG_SYS_HZ, false);
  170. if (ret)
  171. return ret;
  172. setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
  173. isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
  174. return 0;
  175. }
  176. int usb_cpu_stop(void)
  177. {
  178. struct udevice *dev = NULL;
  179. int ret = 0;
  180. #if CONFIG_IS_ENABLED(DM_I2C)
  181. ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
  182. if (ret) {
  183. debug("%s: No bus %d\n", __func__, I2C_2);
  184. return ret;
  185. }
  186. #endif
  187. /* vbus off */
  188. isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
  189. clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
  190. clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN);
  191. return ret;
  192. }
  193. int usb_cpu_init_fail(void)
  194. {
  195. return usb_cpu_stop();
  196. }