mxc_i2c.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * i2c driver for Freescale i.MX series
  4. *
  5. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  6. * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
  7. * Copyright 2020 NXP
  8. *
  9. * Based on i2c-imx.c from linux kernel:
  10. * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
  11. * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  12. * Copyright (C) 2007 RightHand Technologies, Inc.
  13. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  14. *
  15. */
  16. #include <common.h>
  17. #include <log.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/imx-regs.h>
  20. #include <asm/global_data.h>
  21. #include <dm/device_compat.h>
  22. #include <linux/delay.h>
  23. #include <linux/errno.h>
  24. #include <asm/mach-imx/mxc_i2c.h>
  25. #include <asm/mach-imx/sys_proto.h>
  26. #include <asm/io.h>
  27. #include <i2c.h>
  28. #include <watchdog.h>
  29. #include <dm.h>
  30. #include <dm/pinctrl.h>
  31. #include <fdtdec.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define I2C_QUIRK_FLAG (1 << 0)
  34. #define IMX_I2C_REGSHIFT 2
  35. #define VF610_I2C_REGSHIFT 0
  36. #define I2C_EARLY_INIT_INDEX 0
  37. #ifdef CONFIG_SYS_I2C_IFDR_DIV
  38. #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
  39. #else
  40. #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
  41. #endif
  42. /* Register index */
  43. #define IADR 0
  44. #define IFDR 1
  45. #define I2CR 2
  46. #define I2SR 3
  47. #define I2DR 4
  48. #define I2CR_IIEN (1 << 6)
  49. #define I2CR_MSTA (1 << 5)
  50. #define I2CR_MTX (1 << 4)
  51. #define I2CR_TX_NO_AK (1 << 3)
  52. #define I2CR_RSTA (1 << 2)
  53. #define I2SR_ICF (1 << 7)
  54. #define I2SR_IBB (1 << 5)
  55. #define I2SR_IAL (1 << 4)
  56. #define I2SR_IIF (1 << 1)
  57. #define I2SR_RX_NO_AK (1 << 0)
  58. #ifdef I2C_QUIRK_REG
  59. #define I2CR_IEN (0 << 7)
  60. #define I2CR_IDIS (1 << 7)
  61. #define I2SR_IIF_CLEAR (1 << 1)
  62. #else
  63. #define I2CR_IEN (1 << 7)
  64. #define I2CR_IDIS (0 << 7)
  65. #define I2SR_IIF_CLEAR (0 << 1)
  66. #endif
  67. #ifdef I2C_QUIRK_REG
  68. static u16 i2c_clk_div[60][2] = {
  69. { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
  70. { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
  71. { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
  72. { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
  73. { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
  74. { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
  75. { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
  76. { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
  77. { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
  78. { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
  79. { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
  80. { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  81. { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  82. { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  83. { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  84. };
  85. #else
  86. static u16 i2c_clk_div[50][2] = {
  87. { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
  88. { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
  89. { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
  90. { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
  91. { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
  92. { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
  93. { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
  94. { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
  95. { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
  96. { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
  97. { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  98. { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
  99. { 3072, 0x1E }, { 3840, 0x1F }
  100. };
  101. #endif
  102. #ifndef CONFIG_SYS_MXC_I2C1_SPEED
  103. #define CONFIG_SYS_MXC_I2C1_SPEED 100000
  104. #endif
  105. #ifndef CONFIG_SYS_MXC_I2C2_SPEED
  106. #define CONFIG_SYS_MXC_I2C2_SPEED 100000
  107. #endif
  108. #ifndef CONFIG_SYS_MXC_I2C3_SPEED
  109. #define CONFIG_SYS_MXC_I2C3_SPEED 100000
  110. #endif
  111. #ifndef CONFIG_SYS_MXC_I2C4_SPEED
  112. #define CONFIG_SYS_MXC_I2C4_SPEED 100000
  113. #endif
  114. #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
  115. #define CONFIG_SYS_MXC_I2C1_SLAVE 0
  116. #endif
  117. #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
  118. #define CONFIG_SYS_MXC_I2C2_SLAVE 0
  119. #endif
  120. #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
  121. #define CONFIG_SYS_MXC_I2C3_SLAVE 0
  122. #endif
  123. #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
  124. #define CONFIG_SYS_MXC_I2C4_SLAVE 0
  125. #endif
  126. /*
  127. * Calculate and set proper clock divider
  128. */
  129. static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
  130. {
  131. unsigned int i2c_clk_rate;
  132. unsigned int div;
  133. u8 clk_div;
  134. #if defined(CONFIG_MX31)
  135. struct clock_control_regs *sc_regs =
  136. (struct clock_control_regs *)CCM_BASE;
  137. /* start the required I2C clock */
  138. writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
  139. &sc_regs->cgr0);
  140. #endif
  141. /* Divider value calculation */
  142. #if CONFIG_IS_ENABLED(CLK)
  143. i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
  144. #else
  145. i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
  146. #endif
  147. div = (i2c_clk_rate + rate - 1) / rate;
  148. if (div < i2c_clk_div[0][0])
  149. clk_div = 0;
  150. else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
  151. clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
  152. else
  153. for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
  154. ;
  155. /* Store divider value */
  156. return clk_div;
  157. }
  158. /*
  159. * Set I2C Bus speed
  160. */
  161. static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
  162. {
  163. ulong base = i2c_bus->base;
  164. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  165. u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
  166. u8 idx = i2c_clk_div[clk_idx][1];
  167. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  168. if (!base)
  169. return -EINVAL;
  170. /* Store divider value */
  171. writeb(idx, base + (IFDR << reg_shift));
  172. /* Reset module */
  173. writeb(I2CR_IDIS, base + (I2CR << reg_shift));
  174. writeb(0, base + (I2SR << reg_shift));
  175. return 0;
  176. }
  177. #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
  178. #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
  179. #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
  180. static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
  181. {
  182. unsigned sr;
  183. ulong elapsed;
  184. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  185. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  186. ulong base = i2c_bus->base;
  187. ulong start_time = get_timer(0);
  188. for (;;) {
  189. sr = readb(base + (I2SR << reg_shift));
  190. if (sr & I2SR_IAL) {
  191. if (quirk)
  192. writeb(sr | I2SR_IAL, base +
  193. (I2SR << reg_shift));
  194. else
  195. writeb(sr & ~I2SR_IAL, base +
  196. (I2SR << reg_shift));
  197. printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
  198. __func__, sr, readb(base + (I2CR << reg_shift)),
  199. state);
  200. return -ERESTART;
  201. }
  202. if ((sr & (state >> 8)) == (unsigned char)state)
  203. return sr;
  204. WATCHDOG_RESET();
  205. elapsed = get_timer(start_time);
  206. if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
  207. break;
  208. }
  209. printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
  210. sr, readb(base + (I2CR << reg_shift)), state);
  211. return -ETIMEDOUT;
  212. }
  213. static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
  214. {
  215. int ret;
  216. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  217. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  218. ulong base = i2c_bus->base;
  219. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  220. writeb(byte, base + (I2DR << reg_shift));
  221. ret = wait_for_sr_state(i2c_bus, ST_IIF);
  222. if (ret < 0)
  223. return ret;
  224. if (ret & I2SR_RX_NO_AK)
  225. return -EREMOTEIO;
  226. return 0;
  227. }
  228. /*
  229. * Stub implementations for outer i2c slave operations.
  230. */
  231. void __i2c_force_reset_slave(void)
  232. {
  233. }
  234. void i2c_force_reset_slave(void)
  235. __attribute__((weak, alias("__i2c_force_reset_slave")));
  236. /*
  237. * Stop I2C transaction
  238. */
  239. static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
  240. {
  241. int ret;
  242. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  243. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  244. ulong base = i2c_bus->base;
  245. unsigned int temp = readb(base + (I2CR << reg_shift));
  246. temp &= ~(I2CR_MSTA | I2CR_MTX);
  247. writeb(temp, base + (I2CR << reg_shift));
  248. ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
  249. if (ret < 0)
  250. printf("%s:trigger stop failed\n", __func__);
  251. }
  252. /*
  253. * Send start signal, chip address and
  254. * write register address
  255. */
  256. static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
  257. u32 addr, int alen)
  258. {
  259. unsigned int temp;
  260. int ret;
  261. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  262. ulong base = i2c_bus->base;
  263. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  264. /* Reset i2c slave */
  265. i2c_force_reset_slave();
  266. /* Enable I2C controller */
  267. if (quirk)
  268. ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
  269. else
  270. ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
  271. if (ret) {
  272. writeb(I2CR_IEN, base + (I2CR << reg_shift));
  273. /* Wait for controller to be stable */
  274. udelay(50);
  275. }
  276. if (readb(base + (IADR << reg_shift)) == (chip << 1))
  277. writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
  278. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  279. ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
  280. if (ret < 0)
  281. return ret;
  282. /* Start I2C transaction */
  283. temp = readb(base + (I2CR << reg_shift));
  284. temp |= I2CR_MSTA;
  285. writeb(temp, base + (I2CR << reg_shift));
  286. ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
  287. if (ret < 0)
  288. return ret;
  289. temp |= I2CR_MTX | I2CR_TX_NO_AK;
  290. writeb(temp, base + (I2CR << reg_shift));
  291. if (alen >= 0) {
  292. /* write slave address */
  293. ret = tx_byte(i2c_bus, chip << 1);
  294. if (ret < 0)
  295. return ret;
  296. while (alen--) {
  297. ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
  298. if (ret < 0)
  299. return ret;
  300. }
  301. }
  302. return 0;
  303. }
  304. #if !defined(I2C2_BASE_ADDR)
  305. #define I2C2_BASE_ADDR 0
  306. #endif
  307. #if !defined(I2C3_BASE_ADDR)
  308. #define I2C3_BASE_ADDR 0
  309. #endif
  310. #if !defined(I2C4_BASE_ADDR)
  311. #define I2C4_BASE_ADDR 0
  312. #endif
  313. #if !defined(I2C5_BASE_ADDR)
  314. #define I2C5_BASE_ADDR 0
  315. #endif
  316. #if !defined(I2C6_BASE_ADDR)
  317. #define I2C6_BASE_ADDR 0
  318. #endif
  319. #if !defined(I2C7_BASE_ADDR)
  320. #define I2C7_BASE_ADDR 0
  321. #endif
  322. #if !defined(I2C8_BASE_ADDR)
  323. #define I2C8_BASE_ADDR 0
  324. #endif
  325. static struct mxc_i2c_bus mxc_i2c_buses[] = {
  326. #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
  327. defined(CONFIG_FSL_LAYERSCAPE)
  328. { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
  329. { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
  330. { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
  331. { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
  332. { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
  333. { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
  334. { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
  335. { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
  336. #else
  337. { 0, I2C1_BASE_ADDR, 0 },
  338. { 1, I2C2_BASE_ADDR, 0 },
  339. { 2, I2C3_BASE_ADDR, 0 },
  340. { 3, I2C4_BASE_ADDR, 0 },
  341. { 4, I2C5_BASE_ADDR, 0 },
  342. { 5, I2C6_BASE_ADDR, 0 },
  343. { 6, I2C7_BASE_ADDR, 0 },
  344. { 7, I2C8_BASE_ADDR, 0 },
  345. #endif
  346. };
  347. #if !CONFIG_IS_ENABLED(DM_I2C)
  348. int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
  349. {
  350. if (i2c_bus && i2c_bus->idle_bus_fn)
  351. return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
  352. return 0;
  353. }
  354. #else
  355. /*
  356. * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
  357. * "
  358. * scl-gpios: specify the gpio related to SCL pin
  359. * sda-gpios: specify the gpio related to SDA pin
  360. * add pinctrl to configure i2c pins to gpio function for i2c
  361. * bus recovery, call it "gpio" state
  362. * "
  363. *
  364. * The i2c_idle_bus is an implementation following Linux Kernel.
  365. */
  366. int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
  367. {
  368. struct udevice *bus = i2c_bus->bus;
  369. struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
  370. struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
  371. struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
  372. int sda, scl, idle_sclks;
  373. int i, ret = 0;
  374. ulong elapsed, start_time;
  375. if (pinctrl_select_state(bus, "gpio")) {
  376. dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
  377. /*
  378. * GPIO pinctrl for i2c force idle is not a must,
  379. * but it is strongly recommended to be used.
  380. * Because it can help you to recover from bad
  381. * i2c bus state. Do not return failure, because
  382. * it is not a must.
  383. */
  384. return 0;
  385. }
  386. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  387. dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
  388. scl = dm_gpio_get_value(scl_gpio);
  389. sda = dm_gpio_get_value(sda_gpio);
  390. if ((sda & scl) == 1)
  391. goto exit; /* Bus is idle already */
  392. /*
  393. * In most cases it is just enough to generate 8 + 1 SCLK
  394. * clocks to recover I2C slave device from 'stuck' state
  395. * (when for example SW reset was performed, in the middle of
  396. * I2C transmission).
  397. *
  398. * However, there are devices which send data in packets of
  399. * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
  400. * clocks.
  401. */
  402. idle_sclks = 8 + 1;
  403. if (i2c->max_transaction_bytes > 0)
  404. idle_sclks = i2c->max_transaction_bytes * 8 + 1;
  405. /* Send high and low on the SCL line */
  406. for (i = 0; i < idle_sclks; i++) {
  407. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
  408. dm_gpio_set_value(scl_gpio, 0);
  409. udelay(50);
  410. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  411. udelay(50);
  412. }
  413. start_time = get_timer(0);
  414. for (;;) {
  415. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  416. dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
  417. scl = dm_gpio_get_value(scl_gpio);
  418. sda = dm_gpio_get_value(sda_gpio);
  419. if ((sda & scl) == 1)
  420. break;
  421. WATCHDOG_RESET();
  422. elapsed = get_timer(start_time);
  423. if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
  424. ret = -EBUSY;
  425. printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
  426. break;
  427. }
  428. }
  429. exit:
  430. pinctrl_select_state(bus, "default");
  431. return ret;
  432. }
  433. #endif
  434. /*
  435. * Early init I2C for prepare read the clk through I2C.
  436. */
  437. void i2c_early_init_f(void)
  438. {
  439. ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
  440. bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
  441. & I2C_QUIRK_FLAG ? true : false;
  442. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  443. /* Set I2C divider value */
  444. writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
  445. /* Reset module */
  446. writeb(I2CR_IDIS, base + (I2CR << reg_shift));
  447. writeb(0, base + (I2SR << reg_shift));
  448. /* Enable I2C */
  449. writeb(I2CR_IEN, base + (I2CR << reg_shift));
  450. }
  451. static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
  452. u32 addr, int alen)
  453. {
  454. int retry;
  455. int ret;
  456. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  457. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  458. if (!i2c_bus->base)
  459. return -EINVAL;
  460. for (retry = 0; retry < 3; retry++) {
  461. ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
  462. if (ret >= 0)
  463. return 0;
  464. i2c_imx_stop(i2c_bus);
  465. if (ret == -EREMOTEIO)
  466. return ret;
  467. printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
  468. retry);
  469. if (ret != -ERESTART)
  470. /* Disable controller */
  471. writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
  472. udelay(100);
  473. if (i2c_idle_bus(i2c_bus) < 0)
  474. break;
  475. }
  476. printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
  477. return ret;
  478. }
  479. static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
  480. int len)
  481. {
  482. int i, ret = 0;
  483. debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
  484. debug("write_data: ");
  485. /* use rc for counter */
  486. for (i = 0; i < len; ++i)
  487. debug(" 0x%02x", buf[i]);
  488. debug("\n");
  489. for (i = 0; i < len; i++) {
  490. ret = tx_byte(i2c_bus, buf[i]);
  491. if (ret < 0) {
  492. debug("i2c_write_data(): rc=%d\n", ret);
  493. break;
  494. }
  495. }
  496. return ret;
  497. }
  498. /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
  499. * final message of a transaction. If not, it switches the bus back to TX mode
  500. * and does not send a STOP, leaving the bus in a state where a repeated start
  501. * and address can be sent for another message.
  502. */
  503. static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
  504. int len, bool last)
  505. {
  506. int ret;
  507. unsigned int temp;
  508. int i;
  509. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  510. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  511. ulong base = i2c_bus->base;
  512. debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
  513. /* setup bus to read data */
  514. temp = readb(base + (I2CR << reg_shift));
  515. temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
  516. if (len == 1)
  517. temp |= I2CR_TX_NO_AK;
  518. writeb(temp, base + (I2CR << reg_shift));
  519. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  520. /* dummy read to clear ICF */
  521. readb(base + (I2DR << reg_shift));
  522. /* read data */
  523. for (i = 0; i < len; i++) {
  524. ret = wait_for_sr_state(i2c_bus, ST_IIF);
  525. if (ret < 0) {
  526. debug("i2c_read_data(): ret=%d\n", ret);
  527. i2c_imx_stop(i2c_bus);
  528. return ret;
  529. }
  530. if (i == (len - 1)) {
  531. /* Final byte has already been received by master! When
  532. * we read it from I2DR, the master will start another
  533. * cycle. We must program it first to send a STOP or
  534. * switch to TX to avoid this.
  535. */
  536. if (last) {
  537. i2c_imx_stop(i2c_bus);
  538. } else {
  539. /* Final read, no stop, switch back to tx */
  540. temp = readb(base + (I2CR << reg_shift));
  541. temp |= I2CR_MTX | I2CR_TX_NO_AK;
  542. writeb(temp, base + (I2CR << reg_shift));
  543. }
  544. } else if (i == (len - 2)) {
  545. /* Master has already recevied penultimate byte. When
  546. * we read it from I2DR, master will start RX of final
  547. * byte. We must set TX_NO_AK now so it does not ACK
  548. * that final byte.
  549. */
  550. temp = readb(base + (I2CR << reg_shift));
  551. temp |= I2CR_TX_NO_AK;
  552. writeb(temp, base + (I2CR << reg_shift));
  553. }
  554. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  555. buf[i] = readb(base + (I2DR << reg_shift));
  556. }
  557. /* reuse ret for counter*/
  558. for (ret = 0; ret < len; ++ret)
  559. debug(" 0x%02x", buf[ret]);
  560. debug("\n");
  561. /* It is not clear to me that this is necessary */
  562. if (last)
  563. i2c_imx_stop(i2c_bus);
  564. return 0;
  565. }
  566. int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  567. {
  568. return 1;
  569. }
  570. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  571. __attribute__((weak, alias("__enable_i2c_clk")));
  572. #if !CONFIG_IS_ENABLED(DM_I2C)
  573. /*
  574. * Read data from I2C device
  575. *
  576. * The transactions use the syntax defined in the Linux kernel I2C docs.
  577. *
  578. * If alen is > 0, then this function will send a transaction of the form:
  579. * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
  580. * This is a normal I2C register read: writing the register address, then doing
  581. * a repeated start and reading the data.
  582. *
  583. * If alen == 0, then we get this transaction:
  584. * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
  585. * This is somewhat unusual, though valid, transaction. It addresses the chip
  586. * in write mode, but doesn't actually write any register address or data, then
  587. * does a repeated start and reads data.
  588. *
  589. * If alen < 0, then we get this transaction:
  590. * S Chip Rd [A] [data] A ... NA P
  591. * The chip is addressed in read mode and then data is read. No register
  592. * address is written first. This is perfectly valid on most devices and
  593. * required on some (usually those that don't act like an array of registers).
  594. */
  595. static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
  596. int alen, u8 *buf, int len)
  597. {
  598. int ret = 0;
  599. u32 temp;
  600. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  601. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  602. ulong base = i2c_bus->base;
  603. ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
  604. if (ret < 0)
  605. return ret;
  606. if (alen >= 0) {
  607. temp = readb(base + (I2CR << reg_shift));
  608. temp |= I2CR_RSTA;
  609. writeb(temp, base + (I2CR << reg_shift));
  610. }
  611. ret = tx_byte(i2c_bus, (chip << 1) | 1);
  612. if (ret < 0) {
  613. i2c_imx_stop(i2c_bus);
  614. return ret;
  615. }
  616. ret = i2c_read_data(i2c_bus, chip, buf, len, true);
  617. i2c_imx_stop(i2c_bus);
  618. return ret;
  619. }
  620. /*
  621. * Write data to I2C device
  622. *
  623. * If alen > 0, we get this transaction:
  624. * S Chip Wr [A] addr [A] data [A] ... [A] P
  625. * An ordinary write register command.
  626. *
  627. * If alen == 0, then we get this:
  628. * S Chip Wr [A] data [A] ... [A] P
  629. * This is a simple I2C write.
  630. *
  631. * If alen < 0, then we get this:
  632. * S data [A] ... [A] P
  633. * This is most likely NOT something that should be used. It doesn't send the
  634. * chip address first, so in effect, the first byte of data will be used as the
  635. * address.
  636. */
  637. static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
  638. int alen, const u8 *buf, int len)
  639. {
  640. int ret = 0;
  641. ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
  642. if (ret < 0)
  643. return ret;
  644. ret = i2c_write_data(i2c_bus, chip, buf, len);
  645. i2c_imx_stop(i2c_bus);
  646. return ret;
  647. }
  648. struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
  649. {
  650. return &mxc_i2c_buses[adap->hwadapnr];
  651. }
  652. static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  653. uint addr, int alen, uint8_t *buffer,
  654. int len)
  655. {
  656. return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
  657. }
  658. static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
  659. uint addr, int alen, uint8_t *buffer,
  660. int len)
  661. {
  662. return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
  663. }
  664. /*
  665. * Test if a chip at a given address responds (probe the chip)
  666. */
  667. static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
  668. {
  669. return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
  670. }
  671. void bus_i2c_init(int index, int speed, int unused,
  672. int (*idle_bus_fn)(void *p), void *idle_bus_data)
  673. {
  674. int ret;
  675. if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
  676. debug("Error i2c index\n");
  677. return;
  678. }
  679. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  680. if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
  681. printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
  682. (ulong)mxc_i2c_buses[index].base);
  683. return;
  684. }
  685. }
  686. /*
  687. * Warning: Be careful to allow the assignment to a static
  688. * variable here. This function could be called while U-Boot is
  689. * still running in flash memory. So such assignment is equal
  690. * to write data to flash without erasing.
  691. */
  692. if (idle_bus_fn)
  693. mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
  694. if (idle_bus_data)
  695. mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
  696. ret = enable_i2c_clk(1, index);
  697. if (ret < 0) {
  698. debug("I2C-%d clk fail to enable.\n", index);
  699. return;
  700. }
  701. bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
  702. }
  703. /*
  704. * Init I2C Bus
  705. */
  706. static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  707. {
  708. bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
  709. }
  710. /*
  711. * Set I2C Speed
  712. */
  713. static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  714. {
  715. return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
  716. }
  717. /*
  718. * Register mxc i2c adapters
  719. */
  720. #ifdef CONFIG_SYS_I2C_MXC_I2C1
  721. U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
  722. mxc_i2c_read, mxc_i2c_write,
  723. mxc_i2c_set_bus_speed,
  724. CONFIG_SYS_MXC_I2C1_SPEED,
  725. CONFIG_SYS_MXC_I2C1_SLAVE, 0)
  726. #endif
  727. #ifdef CONFIG_SYS_I2C_MXC_I2C2
  728. U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
  729. mxc_i2c_read, mxc_i2c_write,
  730. mxc_i2c_set_bus_speed,
  731. CONFIG_SYS_MXC_I2C2_SPEED,
  732. CONFIG_SYS_MXC_I2C2_SLAVE, 1)
  733. #endif
  734. #ifdef CONFIG_SYS_I2C_MXC_I2C3
  735. U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
  736. mxc_i2c_read, mxc_i2c_write,
  737. mxc_i2c_set_bus_speed,
  738. CONFIG_SYS_MXC_I2C3_SPEED,
  739. CONFIG_SYS_MXC_I2C3_SLAVE, 2)
  740. #endif
  741. #ifdef CONFIG_SYS_I2C_MXC_I2C4
  742. U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
  743. mxc_i2c_read, mxc_i2c_write,
  744. mxc_i2c_set_bus_speed,
  745. CONFIG_SYS_MXC_I2C4_SPEED,
  746. CONFIG_SYS_MXC_I2C4_SLAVE, 3)
  747. #endif
  748. #ifdef CONFIG_SYS_I2C_MXC_I2C5
  749. U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
  750. mxc_i2c_read, mxc_i2c_write,
  751. mxc_i2c_set_bus_speed,
  752. CONFIG_SYS_MXC_I2C5_SPEED,
  753. CONFIG_SYS_MXC_I2C5_SLAVE, 4)
  754. #endif
  755. #ifdef CONFIG_SYS_I2C_MXC_I2C6
  756. U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
  757. mxc_i2c_read, mxc_i2c_write,
  758. mxc_i2c_set_bus_speed,
  759. CONFIG_SYS_MXC_I2C6_SPEED,
  760. CONFIG_SYS_MXC_I2C6_SLAVE, 5)
  761. #endif
  762. #ifdef CONFIG_SYS_I2C_MXC_I2C7
  763. U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
  764. mxc_i2c_read, mxc_i2c_write,
  765. mxc_i2c_set_bus_speed,
  766. CONFIG_SYS_MXC_I2C7_SPEED,
  767. CONFIG_SYS_MXC_I2C7_SLAVE, 6)
  768. #endif
  769. #ifdef CONFIG_SYS_I2C_MXC_I2C8
  770. U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
  771. mxc_i2c_read, mxc_i2c_write,
  772. mxc_i2c_set_bus_speed,
  773. CONFIG_SYS_MXC_I2C8_SPEED,
  774. CONFIG_SYS_MXC_I2C8_SLAVE, 7)
  775. #endif
  776. #else
  777. static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  778. {
  779. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  780. return bus_i2c_set_bus_speed(i2c_bus, speed);
  781. }
  782. static int mxc_i2c_probe(struct udevice *bus)
  783. {
  784. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  785. const void *fdt = gd->fdt_blob;
  786. int node = dev_of_offset(bus);
  787. fdt_addr_t addr;
  788. int ret, ret2;
  789. i2c_bus->driver_data = dev_get_driver_data(bus);
  790. addr = dev_read_addr(bus);
  791. if (addr == FDT_ADDR_T_NONE)
  792. return -EINVAL;
  793. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  794. if (i2c_fused((ulong)addr)) {
  795. printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
  796. (ulong)addr);
  797. return -ENODEV;
  798. }
  799. }
  800. i2c_bus->base = addr;
  801. i2c_bus->index = dev_seq(bus);
  802. i2c_bus->bus = bus;
  803. /* Enable clk */
  804. #if CONFIG_IS_ENABLED(CLK)
  805. ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
  806. if (ret) {
  807. printf("Failed to get i2c clk\n");
  808. return ret;
  809. }
  810. ret = clk_enable(&i2c_bus->per_clk);
  811. if (ret) {
  812. printf("Failed to enable i2c clk\n");
  813. return ret;
  814. }
  815. #else
  816. ret = enable_i2c_clk(1, dev_seq(bus));
  817. if (ret < 0)
  818. return ret;
  819. #endif
  820. /*
  821. * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
  822. * Use gpio to force bus idle when necessary.
  823. */
  824. ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
  825. if (ret < 0) {
  826. debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
  827. dev_seq(bus), i2c_bus->base);
  828. } else {
  829. ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
  830. "scl-gpios", 0, &i2c_bus->scl_gpio,
  831. GPIOD_IS_OUT);
  832. ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
  833. "sda-gpios", 0, &i2c_bus->sda_gpio,
  834. GPIOD_IS_OUT);
  835. if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
  836. !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
  837. ret || ret2) {
  838. dev_err(bus,
  839. "i2c bus %d at 0x%2lx, fail to request scl/sda gpio\n",
  840. dev_seq(bus), i2c_bus->base);
  841. return -EINVAL;
  842. }
  843. }
  844. /*
  845. * Pinmux settings are in board file now, until pinmux is supported,
  846. * we can set pinmux here in probe function.
  847. */
  848. debug("i2c : controller bus %d at %lu , speed %d: ",
  849. dev_seq(bus), i2c_bus->base,
  850. i2c_bus->speed);
  851. return 0;
  852. }
  853. /* Sends: S Addr Wr [A|NA] P */
  854. static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  855. u32 chip_flags)
  856. {
  857. int ret;
  858. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  859. ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
  860. if (ret < 0) {
  861. debug("%s failed, ret = %d\n", __func__, ret);
  862. return ret;
  863. }
  864. i2c_imx_stop(i2c_bus);
  865. return 0;
  866. }
  867. static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  868. {
  869. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  870. int ret = 0;
  871. ulong base = i2c_bus->base;
  872. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  873. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  874. int read_mode;
  875. /* Here address len is set to -1 to not send any address at first.
  876. * Otherwise i2c_init_transfer will send the chip address with write
  877. * mode set. This is wrong if the 1st message is read.
  878. */
  879. ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
  880. if (ret < 0) {
  881. debug("i2c_init_transfer error: %d\n", ret);
  882. return ret;
  883. }
  884. read_mode = -1; /* So it's always different on the first message */
  885. for (; nmsgs > 0; nmsgs--, msg++) {
  886. const int msg_is_read = !!(msg->flags & I2C_M_RD);
  887. debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
  888. msg->len, msg_is_read ? 'R' : 'W');
  889. if (msg_is_read != read_mode) {
  890. /* Send repeated start if not 1st message */
  891. if (read_mode != -1) {
  892. debug("i2c_xfer: [RSTART]\n");
  893. ret = readb(base + (I2CR << reg_shift));
  894. ret |= I2CR_RSTA;
  895. writeb(ret, base + (I2CR << reg_shift));
  896. }
  897. debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
  898. msg_is_read ? 'R' : 'W');
  899. ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
  900. if (ret < 0) {
  901. debug("i2c_xfer: [STOP]\n");
  902. i2c_imx_stop(i2c_bus);
  903. break;
  904. }
  905. read_mode = msg_is_read;
  906. }
  907. if (msg->flags & I2C_M_RD)
  908. ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
  909. msg->len, nmsgs == 1 ||
  910. (msg->flags & I2C_M_STOP));
  911. else
  912. ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
  913. msg->len);
  914. if (ret < 0)
  915. break;
  916. }
  917. if (ret)
  918. debug("i2c_write: error sending\n");
  919. i2c_imx_stop(i2c_bus);
  920. return ret;
  921. }
  922. static const struct dm_i2c_ops mxc_i2c_ops = {
  923. .xfer = mxc_i2c_xfer,
  924. .probe_chip = mxc_i2c_probe_chip,
  925. .set_bus_speed = mxc_i2c_set_bus_speed,
  926. };
  927. static const struct udevice_id mxc_i2c_ids[] = {
  928. { .compatible = "fsl,imx21-i2c", },
  929. { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
  930. {}
  931. };
  932. U_BOOT_DRIVER(i2c_mxc) = {
  933. .name = "i2c_mxc",
  934. .id = UCLASS_I2C,
  935. .of_match = mxc_i2c_ids,
  936. .probe = mxc_i2c_probe,
  937. .priv_auto = sizeof(struct mxc_i2c_bus),
  938. .ops = &mxc_i2c_ops,
  939. .flags = DM_FLAG_PRE_RELOC,
  940. };
  941. #endif