fsl_i2c.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2006,2009 Freescale Semiconductor, Inc.
  4. *
  5. * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. * Changes for multibus/multiadapter I2C support.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <i2c.h> /* Functional interface */
  11. #include <log.h>
  12. #include <time.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <asm/fsl_i2c.h> /* HW definitions */
  16. #include <clk.h>
  17. #include <dm.h>
  18. #include <mapmem.h>
  19. #include <linux/delay.h>
  20. /* The maximum number of microseconds we will wait until another master has
  21. * released the bus. If not defined in the board header file, then use a
  22. * generic value.
  23. */
  24. #ifndef CONFIG_I2C_MBB_TIMEOUT
  25. #define CONFIG_I2C_MBB_TIMEOUT 100000
  26. #endif
  27. /* The maximum number of microseconds we will wait for a read or write
  28. * operation to complete. If not defined in the board header file, then use a
  29. * generic value.
  30. */
  31. #ifndef CONFIG_I2C_TIMEOUT
  32. #define CONFIG_I2C_TIMEOUT 100000
  33. #endif
  34. #define I2C_READ_BIT 1
  35. #define I2C_WRITE_BIT 0
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #if !CONFIG_IS_ENABLED(DM_I2C)
  38. static const struct fsl_i2c_base *i2c_base[4] = {
  39. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
  40. #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  41. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
  42. #endif
  43. #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  44. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
  45. #endif
  46. #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  47. (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
  48. #endif
  49. };
  50. #endif
  51. /* I2C speed map for a DFSR value of 1 */
  52. #ifdef __M68K__
  53. /*
  54. * Map I2C frequency dividers to FDR and DFSR values
  55. *
  56. * This structure is used to define the elements of a table that maps I2C
  57. * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
  58. * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
  59. * Sampling Rate (DFSR) registers.
  60. *
  61. * The actual table should be defined in the board file, and it must be called
  62. * fsl_i2c_speed_map[].
  63. *
  64. * The last entry of the table must have a value of {-1, X}, where X is same
  65. * FDR/DFSR values as the second-to-last entry. This guarantees that any
  66. * search through the array will always find a match.
  67. *
  68. * The values of the divider must be in increasing numerical order, i.e.
  69. * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
  70. *
  71. * For this table, the values are based on a value of 1 for the DFSR
  72. * register. See the application note AN2919 "Determining the I2C Frequency
  73. * Divider Ratio for SCL"
  74. *
  75. * ColdFire I2C frequency dividers for FDR values are different from
  76. * PowerPC. The protocol to use the I2C module is still the same.
  77. * A different table is defined and are based on MCF5xxx user manual.
  78. *
  79. */
  80. static const struct {
  81. unsigned short divider;
  82. u8 fdr;
  83. } fsl_i2c_speed_map[] = {
  84. {20, 32}, {22, 33}, {24, 34}, {26, 35},
  85. {28, 0}, {28, 36}, {30, 1}, {32, 37},
  86. {34, 2}, {36, 38}, {40, 3}, {40, 39},
  87. {44, 4}, {48, 5}, {48, 40}, {56, 6},
  88. {56, 41}, {64, 42}, {68, 7}, {72, 43},
  89. {80, 8}, {80, 44}, {88, 9}, {96, 41},
  90. {104, 10}, {112, 42}, {128, 11}, {128, 43},
  91. {144, 12}, {160, 13}, {160, 48}, {192, 14},
  92. {192, 49}, {224, 50}, {240, 15}, {256, 51},
  93. {288, 16}, {320, 17}, {320, 52}, {384, 18},
  94. {384, 53}, {448, 54}, {480, 19}, {512, 55},
  95. {576, 20}, {640, 21}, {640, 56}, {768, 22},
  96. {768, 57}, {960, 23}, {896, 58}, {1024, 59},
  97. {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
  98. {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
  99. {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
  100. {-1, 31}
  101. };
  102. #endif
  103. /**
  104. * Set the I2C bus speed for a given I2C device
  105. *
  106. * @param base: the I2C device registers
  107. * @i2c_clk: I2C bus clock frequency
  108. * @speed: the desired speed of the bus
  109. *
  110. * The I2C device must be stopped before calling this function.
  111. *
  112. * The return value is the actual bus speed that is set.
  113. */
  114. static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
  115. uint i2c_clk, uint speed)
  116. {
  117. ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
  118. /*
  119. * We want to choose an FDR/DFSR that generates an I2C bus speed that
  120. * is equal to or lower than the requested speed. That means that we
  121. * want the first divider that is equal to or greater than the
  122. * calculated divider.
  123. */
  124. #ifdef __PPC__
  125. u8 dfsr, fdr = 0x31; /* Default if no FDR found */
  126. /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
  127. ushort a, b, ga, gb;
  128. ulong c_div, est_div;
  129. #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
  130. dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
  131. #else
  132. /* Condition 1: dfsr <= 50/T */
  133. dfsr = (5 * (i2c_clk / 1000)) / 100000;
  134. #endif
  135. #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
  136. fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
  137. speed = i2c_clk / divider; /* Fake something */
  138. #else
  139. debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
  140. if (!dfsr)
  141. dfsr = 1;
  142. est_div = ~0;
  143. for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
  144. for (gb = 0; gb < 8; gb++) {
  145. b = 16 << gb;
  146. c_div = b * (a + ((3 * dfsr) / b) * 2);
  147. if (c_div > divider && c_div < est_div) {
  148. ushort bin_gb, bin_ga;
  149. est_div = c_div;
  150. bin_gb = gb << 2;
  151. bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
  152. fdr = bin_gb | bin_ga;
  153. speed = i2c_clk / est_div;
  154. debug("FDR: 0x%.2x, ", fdr);
  155. debug("div: %ld, ", est_div);
  156. debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
  157. debug("a: %d, b: %d, speed: %d\n", a, b, speed);
  158. /* Condition 2 not accounted for */
  159. debug("Tr <= %d ns\n",
  160. (b - 3 * dfsr) * 1000000 /
  161. (i2c_clk / 1000));
  162. }
  163. }
  164. if (a == 20)
  165. a += 2;
  166. if (a == 24)
  167. a += 4;
  168. }
  169. debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
  170. debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
  171. #endif
  172. writeb(dfsr, &base->dfsrr); /* set default filter */
  173. writeb(fdr, &base->fdr); /* set bus speed */
  174. #else
  175. uint i;
  176. for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
  177. if (fsl_i2c_speed_map[i].divider >= divider) {
  178. u8 fdr;
  179. fdr = fsl_i2c_speed_map[i].fdr;
  180. speed = i2c_clk / fsl_i2c_speed_map[i].divider;
  181. writeb(fdr, &base->fdr); /* set bus speed */
  182. break;
  183. }
  184. #endif
  185. return speed;
  186. }
  187. #if !CONFIG_IS_ENABLED(DM_I2C)
  188. static uint get_i2c_clock(int bus)
  189. {
  190. if (bus)
  191. return gd->arch.i2c2_clk; /* I2C2 clock */
  192. else
  193. return gd->arch.i2c1_clk; /* I2C1 clock */
  194. }
  195. #endif
  196. static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
  197. {
  198. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  199. unsigned long long timeval = 0;
  200. int ret = -1;
  201. uint flags = 0;
  202. #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  203. uint svr = get_svr();
  204. if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
  205. (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
  206. flags = I2C_CR_BIT6;
  207. #endif
  208. writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
  209. timeval = get_ticks();
  210. while (!(readb(&base->sr) & I2C_SR_MBB)) {
  211. if ((get_ticks() - timeval) > timeout)
  212. goto err;
  213. }
  214. if (readb(&base->sr) & I2C_SR_MAL) {
  215. /* SDA is stuck low */
  216. writeb(0, &base->cr);
  217. udelay(100);
  218. writeb(I2C_CR_MSTA | flags, &base->cr);
  219. writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
  220. }
  221. readb(&base->dr);
  222. timeval = get_ticks();
  223. while (!(readb(&base->sr) & I2C_SR_MIF)) {
  224. if ((get_ticks() - timeval) > timeout)
  225. goto err;
  226. }
  227. ret = 0;
  228. err:
  229. writeb(I2C_CR_MEN | flags, &base->cr);
  230. writeb(0, &base->sr);
  231. udelay(100);
  232. return ret;
  233. }
  234. static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
  235. slaveadd, int i2c_clk, int busnum)
  236. {
  237. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  238. unsigned long long timeval;
  239. #ifdef CONFIG_SYS_I2C_INIT_BOARD
  240. /* Call board specific i2c bus reset routine before accessing the
  241. * environment, which might be in a chip on that bus. For details
  242. * about this problem see doc/I2C_Edge_Conditions.
  243. */
  244. i2c_init_board();
  245. #endif
  246. writeb(0, &base->cr); /* stop I2C controller */
  247. udelay(5); /* let it shutdown in peace */
  248. set_i2c_bus_speed(base, i2c_clk, speed);
  249. writeb(slaveadd << 1, &base->adr);/* write slave address */
  250. writeb(0x0, &base->sr); /* clear status register */
  251. writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
  252. timeval = get_ticks();
  253. while (readb(&base->sr) & I2C_SR_MBB) {
  254. if ((get_ticks() - timeval) < timeout)
  255. continue;
  256. if (fsl_i2c_fixup(base))
  257. debug("i2c_init: BUS#%d failed to init\n",
  258. busnum);
  259. break;
  260. }
  261. }
  262. static int i2c_wait4bus(const struct fsl_i2c_base *base)
  263. {
  264. unsigned long long timeval = get_ticks();
  265. const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
  266. while (readb(&base->sr) & I2C_SR_MBB) {
  267. if ((get_ticks() - timeval) > timeout)
  268. return -1;
  269. }
  270. return 0;
  271. }
  272. static int i2c_wait(const struct fsl_i2c_base *base, int write)
  273. {
  274. u32 csr;
  275. unsigned long long timeval = get_ticks();
  276. const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
  277. do {
  278. csr = readb(&base->sr);
  279. if (!(csr & I2C_SR_MIF))
  280. continue;
  281. /* Read again to allow register to stabilise */
  282. csr = readb(&base->sr);
  283. writeb(0x0, &base->sr);
  284. if (csr & I2C_SR_MAL) {
  285. debug("%s: MAL\n", __func__);
  286. return -1;
  287. }
  288. if (!(csr & I2C_SR_MCF)) {
  289. debug("%s: unfinished\n", __func__);
  290. return -1;
  291. }
  292. if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
  293. debug("%s: No RXACK\n", __func__);
  294. return -1;
  295. }
  296. return 0;
  297. } while ((get_ticks() - timeval) < timeout);
  298. debug("%s: timed out\n", __func__);
  299. return -1;
  300. }
  301. static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
  302. u8 dir, int rsta)
  303. {
  304. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
  305. | (rsta ? I2C_CR_RSTA : 0),
  306. &base->cr);
  307. writeb((dev << 1) | dir, &base->dr);
  308. if (i2c_wait(base, I2C_WRITE_BIT) < 0)
  309. return 0;
  310. return 1;
  311. }
  312. static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
  313. int length)
  314. {
  315. int i;
  316. for (i = 0; i < length; i++) {
  317. writeb(data[i], &base->dr);
  318. if (i2c_wait(base, I2C_WRITE_BIT) < 0)
  319. break;
  320. }
  321. return i;
  322. }
  323. static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
  324. int length)
  325. {
  326. int i;
  327. writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
  328. &base->cr);
  329. /* dummy read */
  330. readb(&base->dr);
  331. for (i = 0; i < length; i++) {
  332. if (i2c_wait(base, I2C_READ_BIT) < 0)
  333. break;
  334. /* Generate ack on last next to last byte */
  335. if (i == length - 2)
  336. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
  337. &base->cr);
  338. /* Do not generate stop on last byte */
  339. if (i == length - 1)
  340. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
  341. &base->cr);
  342. data[i] = readb(&base->dr);
  343. }
  344. return i;
  345. }
  346. static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
  347. int olen, u8 *data, int dlen)
  348. {
  349. int ret = -1; /* signal error */
  350. if (i2c_wait4bus(base) < 0)
  351. return -1;
  352. /* Some drivers use offset lengths in excess of 4 bytes. These drivers
  353. * adhere to the following convention:
  354. * - the offset length is passed as negative (that is, the absolute
  355. * value of olen is the actual offset length)
  356. * - the offset itself is passed in data, which is overwritten by the
  357. * subsequent read operation
  358. */
  359. if (olen < 0) {
  360. if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
  361. ret = __i2c_write_data(base, data, -olen);
  362. if (ret != -olen)
  363. return -1;
  364. if (dlen && i2c_write_addr(base, chip_addr,
  365. I2C_READ_BIT, 1) != 0)
  366. ret = __i2c_read_data(base, data, dlen);
  367. } else {
  368. if ((!dlen || olen > 0) &&
  369. i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
  370. __i2c_write_data(base, offset, olen) == olen)
  371. ret = 0; /* No error so far */
  372. if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
  373. olen ? 1 : 0) != 0)
  374. ret = __i2c_read_data(base, data, dlen);
  375. }
  376. writeb(I2C_CR_MEN, &base->cr);
  377. if (i2c_wait4bus(base)) /* Wait until STOP */
  378. debug("i2c_read: wait4bus timed out\n");
  379. if (ret == dlen)
  380. return 0;
  381. return -1;
  382. }
  383. static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
  384. u8 *offset, int olen, u8 *data, int dlen)
  385. {
  386. int ret = -1; /* signal error */
  387. if (i2c_wait4bus(base) < 0)
  388. return -1;
  389. if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
  390. __i2c_write_data(base, offset, olen) == olen) {
  391. ret = __i2c_write_data(base, data, dlen);
  392. }
  393. writeb(I2C_CR_MEN, &base->cr);
  394. if (i2c_wait4bus(base)) /* Wait until STOP */
  395. debug("i2c_write: wait4bus timed out\n");
  396. if (ret == dlen)
  397. return 0;
  398. return -1;
  399. }
  400. static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
  401. {
  402. /* For unknown reason the controller will ACK when
  403. * probing for a slave with the same address, so skip
  404. * it.
  405. */
  406. if (chip == (readb(&base->adr) >> 1))
  407. return -1;
  408. return __i2c_read(base, chip, 0, 0, NULL, 0);
  409. }
  410. static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
  411. uint speed, int i2c_clk)
  412. {
  413. writeb(0, &base->cr); /* stop controller */
  414. set_i2c_bus_speed(base, i2c_clk, speed);
  415. writeb(I2C_CR_MEN, &base->cr); /* start controller */
  416. return 0;
  417. }
  418. #if !CONFIG_IS_ENABLED(DM_I2C)
  419. static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  420. {
  421. __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
  422. get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
  423. }
  424. static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
  425. {
  426. return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
  427. }
  428. static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
  429. int olen, u8 *data, int dlen)
  430. {
  431. u8 *o = (u8 *)&offset;
  432. return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
  433. olen, data, dlen);
  434. }
  435. static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
  436. int olen, u8 *data, int dlen)
  437. {
  438. u8 *o = (u8 *)&offset;
  439. return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
  440. olen, data, dlen);
  441. }
  442. static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  443. {
  444. return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
  445. get_i2c_clock(adap->hwadapnr));
  446. }
  447. /*
  448. * Register fsl i2c adapters
  449. */
  450. U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  451. fsl_i2c_write, fsl_i2c_set_bus_speed,
  452. CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
  453. 0)
  454. #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  455. U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  456. fsl_i2c_write, fsl_i2c_set_bus_speed,
  457. CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
  458. 1)
  459. #endif
  460. #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  461. U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  462. fsl_i2c_write, fsl_i2c_set_bus_speed,
  463. CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
  464. 2)
  465. #endif
  466. #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  467. U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
  468. fsl_i2c_write, fsl_i2c_set_bus_speed,
  469. CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
  470. 3)
  471. #endif
  472. #else /* CONFIG_DM_I2C */
  473. static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  474. u32 chip_flags)
  475. {
  476. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  477. return __i2c_probe_chip(dev->base, chip_addr);
  478. }
  479. static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
  480. {
  481. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  482. return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
  483. }
  484. static int fsl_i2c_of_to_plat(struct udevice *bus)
  485. {
  486. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  487. struct clk clock;
  488. dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
  489. if (!dev->base)
  490. return -ENOMEM;
  491. dev->index = dev_read_u32_default(bus, "cell-index", -1);
  492. dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
  493. 0x7f);
  494. dev->speed = dev_read_u32_default(bus, "clock-frequency",
  495. I2C_SPEED_FAST_RATE);
  496. if (!clk_get_by_index(bus, 0, &clock))
  497. dev->i2c_clk = clk_get_rate(&clock);
  498. else
  499. dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
  500. gd->arch.i2c1_clk;
  501. return 0;
  502. }
  503. static int fsl_i2c_probe(struct udevice *bus)
  504. {
  505. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  506. __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
  507. dev->index);
  508. return 0;
  509. }
  510. static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  511. {
  512. struct fsl_i2c_dev *dev = dev_get_priv(bus);
  513. struct i2c_msg *dmsg, *omsg, dummy;
  514. memset(&dummy, 0, sizeof(struct i2c_msg));
  515. /* We expect either two messages (one with an offset and one with the
  516. * actual data) or one message (just data)
  517. */
  518. if (nmsgs > 2 || nmsgs == 0) {
  519. debug("%s: Only one or two messages are supported.", __func__);
  520. return -1;
  521. }
  522. omsg = nmsgs == 1 ? &dummy : msg;
  523. dmsg = nmsgs == 1 ? msg : msg + 1;
  524. if (dmsg->flags & I2C_M_RD)
  525. return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
  526. dmsg->buf, dmsg->len);
  527. else
  528. return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
  529. dmsg->buf, dmsg->len);
  530. }
  531. static const struct dm_i2c_ops fsl_i2c_ops = {
  532. .xfer = fsl_i2c_xfer,
  533. .probe_chip = fsl_i2c_probe_chip,
  534. .set_bus_speed = fsl_i2c_set_bus_speed,
  535. };
  536. static const struct udevice_id fsl_i2c_ids[] = {
  537. { .compatible = "fsl-i2c", },
  538. { /* sentinel */ }
  539. };
  540. U_BOOT_DRIVER(i2c_fsl) = {
  541. .name = "i2c_fsl",
  542. .id = UCLASS_I2C,
  543. .of_match = fsl_i2c_ids,
  544. .probe = fsl_i2c_probe,
  545. .of_to_plat = fsl_i2c_of_to_plat,
  546. .priv_auto = sizeof(struct fsl_i2c_dev),
  547. .ops = &fsl_i2c_ops,
  548. };
  549. #endif /* CONFIG_DM_I2C */