designware_i2c.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <i2c.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <pci.h>
  13. #include <reset.h>
  14. #include <asm/io.h>
  15. #include <linux/delay.h>
  16. #include "designware_i2c.h"
  17. #include <dm/device_compat.h>
  18. #include <linux/err.h>
  19. /*
  20. * This assigned unique hex value is constant and is derived from the two ASCII
  21. * letters 'DW' followed by a 16-bit unsigned number
  22. */
  23. #define DW_I2C_COMP_TYPE 0x44570140
  24. #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  25. static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  26. {
  27. u32 ena = enable ? IC_ENABLE_0B : 0;
  28. writel(ena, &i2c_base->ic_enable);
  29. return 0;
  30. }
  31. #else
  32. static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  33. {
  34. u32 ena = enable ? IC_ENABLE_0B : 0;
  35. int timeout = 100;
  36. do {
  37. writel(ena, &i2c_base->ic_enable);
  38. if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  39. return 0;
  40. /*
  41. * Wait 10 times the signaling period of the highest I2C
  42. * transfer supported by the driver (for 400KHz this is
  43. * 25us) as described in the DesignWare I2C databook.
  44. */
  45. udelay(25);
  46. } while (timeout--);
  47. printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  48. return -ETIMEDOUT;
  49. }
  50. #endif
  51. /* High and low times in different speed modes (in ns) */
  52. enum {
  53. /* SDA Hold Time */
  54. DEFAULT_SDA_HOLD_TIME = 300,
  55. };
  56. /**
  57. * calc_counts() - Convert a period to a number of IC clk cycles
  58. *
  59. * @ic_clk: Input clock in Hz
  60. * @period_ns: Period to represent, in ns
  61. * @return calculated count
  62. */
  63. static uint calc_counts(uint ic_clk, uint period_ns)
  64. {
  65. return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  66. }
  67. /**
  68. * struct i2c_mode_info - Information about an I2C speed mode
  69. *
  70. * Each speed mode has its own characteristics. This struct holds these to aid
  71. * calculations in dw_i2c_calc_timing().
  72. *
  73. * @speed: Speed in Hz
  74. * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  75. * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  76. * @def_rise_time_ns: Default rise time in ns
  77. * @def_fall_time_ns: Default fall time in ns
  78. */
  79. struct i2c_mode_info {
  80. int speed;
  81. int min_scl_hightime_ns;
  82. int min_scl_lowtime_ns;
  83. int def_rise_time_ns;
  84. int def_fall_time_ns;
  85. };
  86. static const struct i2c_mode_info info_for_mode[] = {
  87. [IC_SPEED_MODE_STANDARD] = {
  88. I2C_SPEED_STANDARD_RATE,
  89. MIN_SS_SCL_HIGHTIME,
  90. MIN_SS_SCL_LOWTIME,
  91. 1000,
  92. 300,
  93. },
  94. [IC_SPEED_MODE_FAST] = {
  95. I2C_SPEED_FAST_RATE,
  96. MIN_FS_SCL_HIGHTIME,
  97. MIN_FS_SCL_LOWTIME,
  98. 300,
  99. 300,
  100. },
  101. [IC_SPEED_MODE_FAST_PLUS] = {
  102. I2C_SPEED_FAST_PLUS_RATE,
  103. MIN_FP_SCL_HIGHTIME,
  104. MIN_FP_SCL_LOWTIME,
  105. 260,
  106. 500,
  107. },
  108. [IC_SPEED_MODE_HIGH] = {
  109. I2C_SPEED_HIGH_RATE,
  110. MIN_HS_SCL_HIGHTIME,
  111. MIN_HS_SCL_LOWTIME,
  112. 120,
  113. 120,
  114. },
  115. };
  116. /**
  117. * dw_i2c_calc_timing() - Calculate the timings to use for a bus
  118. *
  119. * @priv: Bus private information (NULL if not using driver model)
  120. * @mode: Speed mode to use
  121. * @ic_clk: IC clock speed in Hz
  122. * @spk_cnt: Spike-suppression count
  123. * @config: Returns value to use
  124. * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
  125. */
  126. static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
  127. int ic_clk, int spk_cnt,
  128. struct dw_i2c_speed_config *config)
  129. {
  130. int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
  131. int hcnt, lcnt, period_cnt, diff, tot;
  132. int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
  133. const struct i2c_mode_info *info;
  134. /*
  135. * Find the period, rise, fall, min tlow, and min thigh in terms of
  136. * counts of the IC clock
  137. */
  138. info = &info_for_mode[mode];
  139. period_cnt = ic_clk / info->speed;
  140. scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
  141. priv->scl_rise_time_ns : info->def_rise_time_ns;
  142. scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
  143. priv->scl_fall_time_ns : info->def_fall_time_ns;
  144. rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
  145. fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
  146. min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
  147. min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
  148. debug("dw_i2c: mode %d, ic_clk %d, speed %d, period %d rise %d fall %d tlow %d thigh %d spk %d\n",
  149. mode, ic_clk, info->speed, period_cnt, rise_cnt, fall_cnt,
  150. min_tlow_cnt, min_thigh_cnt, spk_cnt);
  151. /*
  152. * Back-solve for hcnt and lcnt according to the following equations:
  153. * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
  154. * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
  155. */
  156. hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
  157. lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
  158. if (hcnt < 0 || lcnt < 0) {
  159. debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
  160. return log_msg_ret("counts", -EINVAL);
  161. }
  162. /*
  163. * Now add things back up to ensure the period is hit. If it is off,
  164. * split the difference and bias to lcnt for remainder
  165. */
  166. tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
  167. if (tot < period_cnt) {
  168. diff = (period_cnt - tot) / 2;
  169. hcnt += diff;
  170. lcnt += diff;
  171. tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
  172. lcnt += period_cnt - tot;
  173. }
  174. config->scl_lcnt = lcnt;
  175. config->scl_hcnt = hcnt;
  176. /* Use internal default unless other value is specified */
  177. sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
  178. priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
  179. config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
  180. debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
  181. config->sda_hold);
  182. return 0;
  183. }
  184. /**
  185. * calc_bus_speed() - Calculate the config to use for a particular i2c speed
  186. *
  187. * @priv: Private information for the driver (NULL if not using driver model)
  188. * @i2c_base: Registers for the I2C controller
  189. * @speed: Required i2c speed in Hz
  190. * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
  191. * @config: Returns the config to use for this speed
  192. * @return 0 if OK, -ve on error
  193. */
  194. static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int speed,
  195. ulong bus_clk, struct dw_i2c_speed_config *config)
  196. {
  197. const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
  198. enum i2c_speed_mode i2c_spd;
  199. int spk_cnt;
  200. int ret;
  201. if (priv)
  202. scl_sda_cfg = priv->scl_sda_cfg;
  203. /* Allow high speed if there is no config, or the config allows it */
  204. if (speed >= I2C_SPEED_HIGH_RATE)
  205. i2c_spd = IC_SPEED_MODE_HIGH;
  206. else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
  207. i2c_spd = IC_SPEED_MODE_FAST_PLUS;
  208. else if (speed >= I2C_SPEED_FAST_RATE)
  209. i2c_spd = IC_SPEED_MODE_FAST;
  210. else
  211. i2c_spd = IC_SPEED_MODE_STANDARD;
  212. /* Check is high speed possible and fall back to fast mode if not */
  213. if (i2c_spd == IC_SPEED_MODE_HIGH) {
  214. u32 comp_param1;
  215. comp_param1 = readl(&regs->comp_param1);
  216. if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
  217. != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
  218. i2c_spd = IC_SPEED_MODE_FAST;
  219. }
  220. /* Get the proper spike-suppression count based on target speed */
  221. if (!priv || !priv->has_spk_cnt)
  222. spk_cnt = 0;
  223. else if (i2c_spd >= IC_SPEED_MODE_HIGH)
  224. spk_cnt = readl(&regs->hs_spklen);
  225. else
  226. spk_cnt = readl(&regs->fs_spklen);
  227. if (scl_sda_cfg) {
  228. config->sda_hold = scl_sda_cfg->sda_hold;
  229. if (i2c_spd == IC_SPEED_MODE_STANDARD) {
  230. config->scl_hcnt = scl_sda_cfg->ss_hcnt;
  231. config->scl_lcnt = scl_sda_cfg->ss_lcnt;
  232. } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
  233. config->scl_hcnt = scl_sda_cfg->hs_hcnt;
  234. config->scl_lcnt = scl_sda_cfg->hs_lcnt;
  235. } else {
  236. config->scl_hcnt = scl_sda_cfg->fs_hcnt;
  237. config->scl_lcnt = scl_sda_cfg->fs_lcnt;
  238. }
  239. } else {
  240. ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
  241. config);
  242. if (ret)
  243. return log_msg_ret("gen_confg", ret);
  244. }
  245. config->speed_mode = i2c_spd;
  246. return 0;
  247. }
  248. /**
  249. * _dw_i2c_set_bus_speed() - Set the i2c speed
  250. *
  251. * @priv: Private information for the driver (NULL if not using driver model)
  252. * @i2c_base: Registers for the I2C controller
  253. * @speed: Required i2c speed in Hz
  254. * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
  255. * @return 0 if OK, -ve on error
  256. */
  257. static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
  258. unsigned int speed, unsigned int bus_clk)
  259. {
  260. struct dw_i2c_speed_config config;
  261. unsigned int cntl;
  262. unsigned int ena;
  263. int ret;
  264. ret = calc_bus_speed(priv, i2c_base, speed, bus_clk, &config);
  265. if (ret)
  266. return ret;
  267. /* Get enable setting for restore later */
  268. ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
  269. /* to set speed cltr must be disabled */
  270. dw_i2c_enable(i2c_base, false);
  271. cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  272. switch (config.speed_mode) {
  273. case IC_SPEED_MODE_HIGH:
  274. cntl |= IC_CON_SPD_HS;
  275. writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
  276. writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
  277. break;
  278. case IC_SPEED_MODE_STANDARD:
  279. cntl |= IC_CON_SPD_SS;
  280. writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
  281. writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
  282. break;
  283. case IC_SPEED_MODE_FAST_PLUS:
  284. case IC_SPEED_MODE_FAST:
  285. default:
  286. cntl |= IC_CON_SPD_FS;
  287. writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
  288. writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
  289. break;
  290. }
  291. writel(cntl, &i2c_base->ic_con);
  292. /* Configure SDA Hold Time if required */
  293. if (config.sda_hold)
  294. writel(config.sda_hold, &i2c_base->ic_sda_hold);
  295. /* Restore back i2c now speed set */
  296. if (ena == IC_ENABLE_0B)
  297. dw_i2c_enable(i2c_base, true);
  298. if (priv)
  299. priv->config = config;
  300. return 0;
  301. }
  302. int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
  303. struct dw_i2c_speed_config *config)
  304. {
  305. struct dw_i2c *priv = dev_get_priv(dev);
  306. ulong rate;
  307. int ret;
  308. #if CONFIG_IS_ENABLED(CLK)
  309. rate = clk_get_rate(&priv->clk);
  310. if (IS_ERR_VALUE(rate))
  311. return log_msg_ret("clk", -EINVAL);
  312. #else
  313. rate = IC_CLK;
  314. #endif
  315. ret = calc_bus_speed(priv, priv->regs, speed_hz, rate, config);
  316. if (ret)
  317. printf("%s: ret=%d\n", __func__, ret);
  318. if (ret)
  319. return log_msg_ret("calc_bus_speed", ret);
  320. return 0;
  321. }
  322. /*
  323. * i2c_setaddress - Sets the target slave address
  324. * @i2c_addr: target i2c address
  325. *
  326. * Sets the target slave address.
  327. */
  328. static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
  329. {
  330. /* Disable i2c */
  331. dw_i2c_enable(i2c_base, false);
  332. writel(i2c_addr, &i2c_base->ic_tar);
  333. /* Enable i2c */
  334. dw_i2c_enable(i2c_base, true);
  335. }
  336. /*
  337. * i2c_flush_rxfifo - Flushes the i2c RX FIFO
  338. *
  339. * Flushes the i2c RX FIFO
  340. */
  341. static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
  342. {
  343. while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
  344. readl(&i2c_base->ic_cmd_data);
  345. }
  346. /*
  347. * i2c_wait_for_bb - Waits for bus busy
  348. *
  349. * Waits for bus busy
  350. */
  351. static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
  352. {
  353. unsigned long start_time_bb = get_timer(0);
  354. while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
  355. !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
  356. /* Evaluate timeout */
  357. if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
  358. return 1;
  359. }
  360. return 0;
  361. }
  362. static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
  363. int alen)
  364. {
  365. if (i2c_wait_for_bb(i2c_base))
  366. return 1;
  367. i2c_setaddress(i2c_base, chip);
  368. while (alen) {
  369. alen--;
  370. /* high byte address going out first */
  371. writel((addr >> (alen * 8)) & 0xff,
  372. &i2c_base->ic_cmd_data);
  373. }
  374. return 0;
  375. }
  376. static int i2c_xfer_finish(struct i2c_regs *i2c_base)
  377. {
  378. ulong start_stop_det = get_timer(0);
  379. while (1) {
  380. if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
  381. readl(&i2c_base->ic_clr_stop_det);
  382. break;
  383. } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
  384. break;
  385. }
  386. }
  387. if (i2c_wait_for_bb(i2c_base)) {
  388. printf("Timed out waiting for bus\n");
  389. return 1;
  390. }
  391. i2c_flush_rxfifo(i2c_base);
  392. return 0;
  393. }
  394. /*
  395. * i2c_read - Read from i2c memory
  396. * @chip: target i2c address
  397. * @addr: address to read from
  398. * @alen:
  399. * @buffer: buffer for read data
  400. * @len: no of bytes to be read
  401. *
  402. * Read from i2c memory.
  403. */
  404. static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
  405. int alen, u8 *buffer, int len)
  406. {
  407. unsigned long start_time_rx;
  408. unsigned int active = 0;
  409. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  410. /*
  411. * EEPROM chips that implement "address overflow" are ones
  412. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  413. * address and the extra bits end up in the "chip address"
  414. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  415. * four 256 byte chips.
  416. *
  417. * Note that we consider the length of the address field to
  418. * still be one byte because the extra address bits are
  419. * hidden in the chip address.
  420. */
  421. dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  422. addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
  423. debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
  424. addr);
  425. #endif
  426. if (i2c_xfer_init(i2c_base, dev, addr, alen))
  427. return 1;
  428. start_time_rx = get_timer(0);
  429. while (len) {
  430. if (!active) {
  431. /*
  432. * Avoid writing to ic_cmd_data multiple times
  433. * in case this loop spins too quickly and the
  434. * ic_status RFNE bit isn't set after the first
  435. * write. Subsequent writes to ic_cmd_data can
  436. * trigger spurious i2c transfer.
  437. */
  438. if (len == 1)
  439. writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
  440. else
  441. writel(IC_CMD, &i2c_base->ic_cmd_data);
  442. active = 1;
  443. }
  444. if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
  445. *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
  446. len--;
  447. start_time_rx = get_timer(0);
  448. active = 0;
  449. } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
  450. return 1;
  451. }
  452. }
  453. return i2c_xfer_finish(i2c_base);
  454. }
  455. /*
  456. * i2c_write - Write to i2c memory
  457. * @chip: target i2c address
  458. * @addr: address to read from
  459. * @alen:
  460. * @buffer: buffer for read data
  461. * @len: no of bytes to be read
  462. *
  463. * Write to i2c memory.
  464. */
  465. static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
  466. int alen, u8 *buffer, int len)
  467. {
  468. int nb = len;
  469. unsigned long start_time_tx;
  470. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  471. /*
  472. * EEPROM chips that implement "address overflow" are ones
  473. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  474. * address and the extra bits end up in the "chip address"
  475. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  476. * four 256 byte chips.
  477. *
  478. * Note that we consider the length of the address field to
  479. * still be one byte because the extra address bits are
  480. * hidden in the chip address.
  481. */
  482. dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  483. addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
  484. debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
  485. addr);
  486. #endif
  487. if (i2c_xfer_init(i2c_base, dev, addr, alen))
  488. return 1;
  489. start_time_tx = get_timer(0);
  490. while (len) {
  491. if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
  492. if (--len == 0) {
  493. writel(*buffer | IC_STOP,
  494. &i2c_base->ic_cmd_data);
  495. } else {
  496. writel(*buffer, &i2c_base->ic_cmd_data);
  497. }
  498. buffer++;
  499. start_time_tx = get_timer(0);
  500. } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
  501. printf("Timed out. i2c write Failed\n");
  502. return 1;
  503. }
  504. }
  505. return i2c_xfer_finish(i2c_base);
  506. }
  507. /*
  508. * __dw_i2c_init - Init function
  509. * @speed: required i2c speed
  510. * @slaveaddr: slave address for the device
  511. *
  512. * Initialization function.
  513. */
  514. static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
  515. {
  516. int ret;
  517. /* Disable i2c */
  518. ret = dw_i2c_enable(i2c_base, false);
  519. if (ret)
  520. return ret;
  521. writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
  522. &i2c_base->ic_con);
  523. writel(IC_RX_TL, &i2c_base->ic_rx_tl);
  524. writel(IC_TX_TL, &i2c_base->ic_tx_tl);
  525. writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
  526. #if !CONFIG_IS_ENABLED(DM_I2C)
  527. _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
  528. writel(slaveaddr, &i2c_base->ic_sar);
  529. #endif
  530. /* Enable i2c */
  531. ret = dw_i2c_enable(i2c_base, true);
  532. if (ret)
  533. return ret;
  534. return 0;
  535. }
  536. #if !CONFIG_IS_ENABLED(DM_I2C)
  537. /*
  538. * The legacy I2C functions. These need to get removed once
  539. * all users of this driver are converted to DM.
  540. */
  541. static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
  542. {
  543. switch (adap->hwadapnr) {
  544. #if CONFIG_SYS_I2C_BUS_MAX >= 4
  545. case 3:
  546. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
  547. #endif
  548. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  549. case 2:
  550. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
  551. #endif
  552. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  553. case 1:
  554. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
  555. #endif
  556. case 0:
  557. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
  558. default:
  559. printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
  560. }
  561. return NULL;
  562. }
  563. static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
  564. unsigned int speed)
  565. {
  566. adap->speed = speed;
  567. return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
  568. }
  569. static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  570. {
  571. __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
  572. }
  573. static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
  574. int alen, u8 *buffer, int len)
  575. {
  576. return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
  577. }
  578. static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
  579. int alen, u8 *buffer, int len)
  580. {
  581. return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
  582. }
  583. /* dw_i2c_probe - Probe the i2c chip */
  584. static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
  585. {
  586. struct i2c_regs *i2c_base = i2c_get_base(adap);
  587. u32 tmp;
  588. int ret;
  589. /*
  590. * Try to read the first location of the chip.
  591. */
  592. ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
  593. if (ret)
  594. dw_i2c_init(adap, adap->speed, adap->slaveaddr);
  595. return ret;
  596. }
  597. U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  598. dw_i2c_write, dw_i2c_set_bus_speed,
  599. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
  600. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  601. U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  602. dw_i2c_write, dw_i2c_set_bus_speed,
  603. CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
  604. #endif
  605. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  606. U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  607. dw_i2c_write, dw_i2c_set_bus_speed,
  608. CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
  609. #endif
  610. #if CONFIG_SYS_I2C_BUS_MAX >= 4
  611. U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  612. dw_i2c_write, dw_i2c_set_bus_speed,
  613. CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
  614. #endif
  615. #else /* CONFIG_DM_I2C */
  616. /* The DM I2C functions */
  617. static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  618. int nmsgs)
  619. {
  620. struct dw_i2c *i2c = dev_get_priv(bus);
  621. int ret;
  622. debug("i2c_xfer: %d messages\n", nmsgs);
  623. for (; nmsgs > 0; nmsgs--, msg++) {
  624. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  625. if (msg->flags & I2C_M_RD) {
  626. ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
  627. msg->buf, msg->len);
  628. } else {
  629. ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
  630. msg->buf, msg->len);
  631. }
  632. if (ret) {
  633. debug("i2c_write: error sending\n");
  634. return -EREMOTEIO;
  635. }
  636. }
  637. return 0;
  638. }
  639. static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  640. {
  641. struct dw_i2c *i2c = dev_get_priv(bus);
  642. ulong rate;
  643. #if CONFIG_IS_ENABLED(CLK)
  644. rate = clk_get_rate(&i2c->clk);
  645. if (IS_ERR_VALUE(rate))
  646. return log_ret(-EINVAL);
  647. #else
  648. rate = IC_CLK;
  649. #endif
  650. return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
  651. }
  652. static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  653. uint chip_flags)
  654. {
  655. struct dw_i2c *i2c = dev_get_priv(bus);
  656. struct i2c_regs *i2c_base = i2c->regs;
  657. u32 tmp;
  658. int ret;
  659. /* Try to read the first location of the chip */
  660. ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
  661. if (ret)
  662. __dw_i2c_init(i2c_base, 0, 0);
  663. return ret;
  664. }
  665. int designware_i2c_of_to_plat(struct udevice *bus)
  666. {
  667. struct dw_i2c *priv = dev_get_priv(bus);
  668. int ret;
  669. if (!priv->regs)
  670. priv->regs = dev_read_addr_ptr(bus);
  671. dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
  672. dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
  673. dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
  674. ret = reset_get_bulk(bus, &priv->resets);
  675. if (ret) {
  676. if (ret != -ENOTSUPP)
  677. dev_warn(bus, "Can't get reset: %d\n", ret);
  678. } else {
  679. reset_deassert_bulk(&priv->resets);
  680. }
  681. #if CONFIG_IS_ENABLED(CLK)
  682. ret = clk_get_by_index(bus, 0, &priv->clk);
  683. if (ret)
  684. return ret;
  685. ret = clk_enable(&priv->clk);
  686. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  687. clk_free(&priv->clk);
  688. dev_err(bus, "failed to enable clock\n");
  689. return ret;
  690. }
  691. #endif
  692. return 0;
  693. }
  694. int designware_i2c_probe(struct udevice *bus)
  695. {
  696. struct dw_i2c *priv = dev_get_priv(bus);
  697. uint comp_type;
  698. comp_type = readl(&priv->regs->comp_type);
  699. if (comp_type != DW_I2C_COMP_TYPE) {
  700. log_err("I2C bus %s has unknown type %#x\n", bus->name,
  701. comp_type);
  702. return -ENXIO;
  703. }
  704. log_debug("I2C bus %s version %#x\n", bus->name,
  705. readl(&priv->regs->comp_version));
  706. return __dw_i2c_init(priv->regs, 0, 0);
  707. }
  708. int designware_i2c_remove(struct udevice *dev)
  709. {
  710. struct dw_i2c *priv = dev_get_priv(dev);
  711. #if CONFIG_IS_ENABLED(CLK)
  712. clk_disable(&priv->clk);
  713. clk_free(&priv->clk);
  714. #endif
  715. return reset_release_bulk(&priv->resets);
  716. }
  717. const struct dm_i2c_ops designware_i2c_ops = {
  718. .xfer = designware_i2c_xfer,
  719. .probe_chip = designware_i2c_probe_chip,
  720. .set_bus_speed = designware_i2c_set_bus_speed,
  721. };
  722. static const struct udevice_id designware_i2c_ids[] = {
  723. { .compatible = "snps,designware-i2c" },
  724. { }
  725. };
  726. U_BOOT_DRIVER(i2c_designware) = {
  727. .name = "i2c_designware",
  728. .id = UCLASS_I2C,
  729. .of_match = designware_i2c_ids,
  730. .of_to_plat = designware_i2c_of_to_plat,
  731. .probe = designware_i2c_probe,
  732. .priv_auto = sizeof(struct dw_i2c),
  733. .remove = designware_i2c_remove,
  734. .flags = DM_FLAG_OS_PREPARE,
  735. .ops = &designware_i2c_ops,
  736. };
  737. #endif /* CONFIG_DM_I2C */