main.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  7. * Based on code from spd_sdram.c
  8. * Author: James Yang [at freescale.com]
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <i2c.h>
  13. #include <fsl_ddr_sdram.h>
  14. #include <fsl_ddr.h>
  15. #include <init.h>
  16. #include <log.h>
  17. #include <asm/bitops.h>
  18. /*
  19. * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
  20. * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
  21. * all Power SoCs. But it could be different for ARM SoCs. For example,
  22. * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
  23. * 0x00_8000_0000 ~ 0x00_ffff_ffff
  24. * 0x80_8000_0000 ~ 0xff_ffff_ffff
  25. */
  26. #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
  27. #ifdef CONFIG_MPC83xx
  28. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
  29. #else
  30. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
  31. #endif
  32. #endif
  33. #ifdef CONFIG_PPC
  34. #include <asm/fsl_law.h>
  35. void fsl_ddr_set_lawbar(
  36. const common_timing_params_t *memctl_common_params,
  37. unsigned int memctl_interleaved,
  38. unsigned int ctrl_num);
  39. #endif
  40. void fsl_ddr_set_intl3r(const unsigned int granule_size);
  41. #if defined(SPD_EEPROM_ADDRESS) || \
  42. defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  43. defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  44. #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  45. u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  46. [0][0] = SPD_EEPROM_ADDRESS,
  47. };
  48. #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  49. u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  50. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  51. [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
  52. };
  53. #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  54. u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  55. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  56. [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
  57. };
  58. #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  59. u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  60. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  61. [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
  62. [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
  63. [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
  64. };
  65. #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  66. u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  67. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  68. [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
  69. [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
  70. };
  71. #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  72. u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  73. [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
  74. [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
  75. [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
  76. [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
  77. [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
  78. [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
  79. };
  80. #endif
  81. #if CONFIG_IS_ENABLED(DM_I2C)
  82. #define DEV_TYPE struct udevice
  83. #else
  84. /* Local udevice */
  85. struct ludevice {
  86. u8 chip;
  87. };
  88. #define DEV_TYPE struct ludevice
  89. #endif
  90. #define SPD_SPA0_ADDRESS 0x36
  91. #define SPD_SPA1_ADDRESS 0x37
  92. static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr,
  93. int alen, uint8_t *buf, int len)
  94. {
  95. int ret;
  96. #if CONFIG_IS_ENABLED(DM_I2C)
  97. ret = dm_i2c_read(dev, 0, buf, len);
  98. #else
  99. ret = i2c_read(dev->chip, addr, alen, buf, len);
  100. #endif
  101. return ret;
  102. }
  103. #ifdef CONFIG_SYS_FSL_DDR4
  104. static int ddr_i2c_dummy_write(unsigned int chip_addr)
  105. {
  106. uint8_t buf = 0;
  107. #if CONFIG_IS_ENABLED(DM_I2C)
  108. struct udevice *dev;
  109. int ret;
  110. ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr,
  111. 1, &dev);
  112. if (ret) {
  113. printf("%s: Cannot find udev for a bus %d\n", __func__,
  114. CONFIG_SYS_SPD_BUS_NUM);
  115. return ret;
  116. }
  117. return dm_i2c_write(dev, 0, &buf, 1);
  118. #else
  119. return i2c_write(chip_addr, 0, 1, &buf, 1);
  120. #endif
  121. return 0;
  122. }
  123. #endif
  124. static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  125. {
  126. int ret;
  127. DEV_TYPE *dev;
  128. #if CONFIG_IS_ENABLED(DM_I2C)
  129. ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
  130. 1, &dev);
  131. if (ret) {
  132. printf("%s: Cannot find udev for a bus %d\n", __func__,
  133. CONFIG_SYS_SPD_BUS_NUM);
  134. return;
  135. }
  136. #else /* Non DM I2C support - will be removed */
  137. struct ludevice ldev = {
  138. .chip = i2c_address,
  139. };
  140. dev = &ldev;
  141. i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  142. #endif
  143. #ifdef CONFIG_SYS_FSL_DDR4
  144. /*
  145. * DDR4 SPD has 384 to 512 bytes
  146. * To access the lower 256 bytes, we need to set EE page address to 0
  147. * To access the upper 256 bytes, we need to set EE page address to 1
  148. * See Jedec standar No. 21-C for detail
  149. */
  150. ddr_i2c_dummy_write(SPD_SPA0_ADDRESS);
  151. ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256);
  152. if (!ret) {
  153. ddr_i2c_dummy_write(SPD_SPA1_ADDRESS);
  154. ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256),
  155. min(256,
  156. (int)sizeof(generic_spd_eeprom_t)
  157. - 256));
  158. }
  159. #else
  160. ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd,
  161. sizeof(generic_spd_eeprom_t));
  162. #endif
  163. if (ret) {
  164. if (i2c_address ==
  165. #ifdef SPD_EEPROM_ADDRESS
  166. SPD_EEPROM_ADDRESS
  167. #elif defined(SPD_EEPROM_ADDRESS1)
  168. SPD_EEPROM_ADDRESS1
  169. #endif
  170. ) {
  171. printf("DDR: failed to read SPD from address %u\n",
  172. i2c_address);
  173. } else {
  174. debug("DDR: failed to read SPD from address %u\n",
  175. i2c_address);
  176. }
  177. memset(spd, 0, sizeof(generic_spd_eeprom_t));
  178. }
  179. }
  180. __attribute__((weak, alias("__get_spd")))
  181. void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
  182. /* This function allows boards to update SPD address */
  183. __weak void update_spd_address(unsigned int ctrl_num,
  184. unsigned int slot,
  185. unsigned int *addr)
  186. {
  187. }
  188. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  189. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
  190. {
  191. unsigned int i;
  192. unsigned int i2c_address = 0;
  193. if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
  194. printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  195. return;
  196. }
  197. for (i = 0; i < dimm_slots_per_ctrl; i++) {
  198. i2c_address = spd_i2c_addr[ctrl_num][i];
  199. update_spd_address(ctrl_num, i, &i2c_address);
  200. get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  201. }
  202. }
  203. #else
  204. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  205. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
  206. {
  207. }
  208. #endif /* SPD_EEPROM_ADDRESSx */
  209. /*
  210. * ASSUMPTIONS:
  211. * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
  212. * - Same memory data bus width on all controllers
  213. *
  214. * NOTES:
  215. *
  216. * The memory controller and associated documentation use confusing
  217. * terminology when referring to the orgranization of DRAM.
  218. *
  219. * Here is a terminology translation table:
  220. *
  221. * memory controller/documention |industry |this code |signals
  222. * -------------------------------|-----------|-----------|-----------------
  223. * physical bank/bank |rank |rank |chip select (CS)
  224. * logical bank/sub-bank |bank |bank |bank address (BA)
  225. * page/row |row |page |row address
  226. * ??? |column |column |column address
  227. *
  228. * The naming confusion is further exacerbated by the descriptions of the
  229. * memory controller interleaving feature, where accesses are interleaved
  230. * _BETWEEN_ two seperate memory controllers. This is configured only in
  231. * CS0_CONFIG[INTLV_CTL] of each memory controller.
  232. *
  233. * memory controller documentation | number of chip selects
  234. * | per memory controller supported
  235. * --------------------------------|-----------------------------------------
  236. * cache line interleaving | 1 (CS0 only)
  237. * page interleaving | 1 (CS0 only)
  238. * bank interleaving | 1 (CS0 only)
  239. * superbank interleraving | depends on bank (chip select)
  240. * | interleraving [rank interleaving]
  241. * | mode used on every memory controller
  242. *
  243. * Even further confusing is the existence of the interleaving feature
  244. * _WITHIN_ each memory controller. The feature is referred to in
  245. * documentation as chip select interleaving or bank interleaving,
  246. * although it is configured in the DDR_SDRAM_CFG field.
  247. *
  248. * Name of field | documentation name | this code
  249. * -----------------------------|-----------------------|------------------
  250. * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
  251. * | interleaving
  252. */
  253. const char *step_string_tbl[] = {
  254. "STEP_GET_SPD",
  255. "STEP_COMPUTE_DIMM_PARMS",
  256. "STEP_COMPUTE_COMMON_PARMS",
  257. "STEP_GATHER_OPTS",
  258. "STEP_ASSIGN_ADDRESSES",
  259. "STEP_COMPUTE_REGS",
  260. "STEP_PROGRAM_REGS",
  261. "STEP_ALL"
  262. };
  263. const char * step_to_string(unsigned int step) {
  264. unsigned int s = __ilog2(step);
  265. if ((1 << s) != step)
  266. return step_string_tbl[7];
  267. if (s >= ARRAY_SIZE(step_string_tbl)) {
  268. printf("Error for the step in %s\n", __func__);
  269. s = 0;
  270. }
  271. return step_string_tbl[s];
  272. }
  273. static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
  274. unsigned int dbw_cap_adj[])
  275. {
  276. unsigned int i, j;
  277. unsigned long long total_mem, current_mem_base, total_ctlr_mem;
  278. unsigned long long rank_density, ctlr_density = 0;
  279. unsigned int first_ctrl = pinfo->first_ctrl;
  280. unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
  281. /*
  282. * If a reduced data width is requested, but the SPD
  283. * specifies a physically wider device, adjust the
  284. * computed dimm capacities accordingly before
  285. * assigning addresses.
  286. */
  287. for (i = first_ctrl; i <= last_ctrl; i++) {
  288. unsigned int found = 0;
  289. switch (pinfo->memctl_opts[i].data_bus_width) {
  290. case 2:
  291. /* 16-bit */
  292. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  293. unsigned int dw;
  294. if (!pinfo->dimm_params[i][j].n_ranks)
  295. continue;
  296. dw = pinfo->dimm_params[i][j].primary_sdram_width;
  297. if ((dw == 72 || dw == 64)) {
  298. dbw_cap_adj[i] = 2;
  299. break;
  300. } else if ((dw == 40 || dw == 32)) {
  301. dbw_cap_adj[i] = 1;
  302. break;
  303. }
  304. }
  305. break;
  306. case 1:
  307. /* 32-bit */
  308. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  309. unsigned int dw;
  310. dw = pinfo->dimm_params[i][j].data_width;
  311. if (pinfo->dimm_params[i][j].n_ranks
  312. && (dw == 72 || dw == 64)) {
  313. /*
  314. * FIXME: can't really do it
  315. * like this because this just
  316. * further reduces the memory
  317. */
  318. found = 1;
  319. break;
  320. }
  321. }
  322. if (found) {
  323. dbw_cap_adj[i] = 1;
  324. }
  325. break;
  326. case 0:
  327. /* 64-bit */
  328. break;
  329. default:
  330. printf("unexpected data bus width "
  331. "specified controller %u\n", i);
  332. return 1;
  333. }
  334. debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
  335. }
  336. current_mem_base = pinfo->mem_base;
  337. total_mem = 0;
  338. if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
  339. rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
  340. dbw_cap_adj[first_ctrl];
  341. switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
  342. FSL_DDR_CS0_CS1_CS2_CS3) {
  343. case FSL_DDR_CS0_CS1_CS2_CS3:
  344. ctlr_density = 4 * rank_density;
  345. break;
  346. case FSL_DDR_CS0_CS1:
  347. case FSL_DDR_CS0_CS1_AND_CS2_CS3:
  348. ctlr_density = 2 * rank_density;
  349. break;
  350. case FSL_DDR_CS2_CS3:
  351. default:
  352. ctlr_density = rank_density;
  353. break;
  354. }
  355. debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
  356. rank_density, ctlr_density);
  357. for (i = first_ctrl; i <= last_ctrl; i++) {
  358. if (pinfo->memctl_opts[i].memctl_interleaving) {
  359. switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
  360. case FSL_DDR_256B_INTERLEAVING:
  361. case FSL_DDR_CACHE_LINE_INTERLEAVING:
  362. case FSL_DDR_PAGE_INTERLEAVING:
  363. case FSL_DDR_BANK_INTERLEAVING:
  364. case FSL_DDR_SUPERBANK_INTERLEAVING:
  365. total_ctlr_mem = 2 * ctlr_density;
  366. break;
  367. case FSL_DDR_3WAY_1KB_INTERLEAVING:
  368. case FSL_DDR_3WAY_4KB_INTERLEAVING:
  369. case FSL_DDR_3WAY_8KB_INTERLEAVING:
  370. total_ctlr_mem = 3 * ctlr_density;
  371. break;
  372. case FSL_DDR_4WAY_1KB_INTERLEAVING:
  373. case FSL_DDR_4WAY_4KB_INTERLEAVING:
  374. case FSL_DDR_4WAY_8KB_INTERLEAVING:
  375. total_ctlr_mem = 4 * ctlr_density;
  376. break;
  377. default:
  378. panic("Unknown interleaving mode");
  379. }
  380. pinfo->common_timing_params[i].base_address =
  381. current_mem_base;
  382. pinfo->common_timing_params[i].total_mem =
  383. total_ctlr_mem;
  384. total_mem = current_mem_base + total_ctlr_mem;
  385. debug("ctrl %d base 0x%llx\n", i, current_mem_base);
  386. debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
  387. } else {
  388. /* when 3rd controller not interleaved */
  389. current_mem_base = total_mem;
  390. total_ctlr_mem = 0;
  391. pinfo->common_timing_params[i].base_address =
  392. current_mem_base;
  393. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  394. unsigned long long cap =
  395. pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
  396. pinfo->dimm_params[i][j].base_address =
  397. current_mem_base;
  398. debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
  399. current_mem_base += cap;
  400. total_ctlr_mem += cap;
  401. }
  402. debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
  403. pinfo->common_timing_params[i].total_mem =
  404. total_ctlr_mem;
  405. total_mem += total_ctlr_mem;
  406. }
  407. }
  408. } else {
  409. /*
  410. * Simple linear assignment if memory
  411. * controllers are not interleaved.
  412. */
  413. for (i = first_ctrl; i <= last_ctrl; i++) {
  414. total_ctlr_mem = 0;
  415. pinfo->common_timing_params[i].base_address =
  416. current_mem_base;
  417. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  418. /* Compute DIMM base addresses. */
  419. unsigned long long cap =
  420. pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
  421. pinfo->dimm_params[i][j].base_address =
  422. current_mem_base;
  423. debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
  424. current_mem_base += cap;
  425. total_ctlr_mem += cap;
  426. }
  427. debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
  428. pinfo->common_timing_params[i].total_mem =
  429. total_ctlr_mem;
  430. total_mem += total_ctlr_mem;
  431. }
  432. }
  433. debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
  434. return total_mem;
  435. }
  436. /* Use weak function to allow board file to override the address assignment */
  437. __attribute__((weak, alias("__step_assign_addresses")))
  438. unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
  439. unsigned int dbw_cap_adj[]);
  440. unsigned long long
  441. fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  442. unsigned int size_only)
  443. {
  444. unsigned int i, j;
  445. unsigned long long total_mem = 0;
  446. int assert_reset = 0;
  447. unsigned int first_ctrl = pinfo->first_ctrl;
  448. unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
  449. __maybe_unused int retval;
  450. __maybe_unused bool goodspd = false;
  451. __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
  452. fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
  453. common_timing_params_t *timing_params = pinfo->common_timing_params;
  454. if (pinfo->board_need_mem_reset)
  455. assert_reset = pinfo->board_need_mem_reset();
  456. /* data bus width capacity adjust shift amount */
  457. unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
  458. for (i = first_ctrl; i <= last_ctrl; i++)
  459. dbw_capacity_adjust[i] = 0;
  460. debug("starting at step %u (%s)\n",
  461. start_step, step_to_string(start_step));
  462. switch (start_step) {
  463. case STEP_GET_SPD:
  464. #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  465. /* STEP 1: Gather all DIMM SPD data */
  466. for (i = first_ctrl; i <= last_ctrl; i++) {
  467. fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
  468. dimm_slots_per_ctrl);
  469. }
  470. case STEP_COMPUTE_DIMM_PARMS:
  471. /* STEP 2: Compute DIMM parameters from SPD data */
  472. for (i = first_ctrl; i <= last_ctrl; i++) {
  473. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  474. generic_spd_eeprom_t *spd =
  475. &(pinfo->spd_installed_dimms[i][j]);
  476. dimm_params_t *pdimm =
  477. &(pinfo->dimm_params[i][j]);
  478. retval = compute_dimm_parameters(
  479. i, spd, pdimm, j);
  480. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  481. if (!j && retval) {
  482. printf("SPD error on controller %d! "
  483. "Trying fallback to raw timing "
  484. "calculation\n", i);
  485. retval = fsl_ddr_get_dimm_params(pdimm,
  486. i, j);
  487. }
  488. #else
  489. if (retval == 2) {
  490. printf("Error: compute_dimm_parameters"
  491. " non-zero returned FATAL value "
  492. "for memctl=%u dimm=%u\n", i, j);
  493. return 0;
  494. }
  495. #endif
  496. if (retval) {
  497. debug("Warning: compute_dimm_parameters"
  498. " non-zero return value for memctl=%u "
  499. "dimm=%u\n", i, j);
  500. } else {
  501. goodspd = true;
  502. }
  503. }
  504. }
  505. if (!goodspd) {
  506. /*
  507. * No valid SPD found
  508. * Throw an error if this is for main memory, i.e.
  509. * first_ctrl == 0. Otherwise, siliently return 0
  510. * as the memory size.
  511. */
  512. if (first_ctrl == 0)
  513. printf("Error: No valid SPD detected.\n");
  514. return 0;
  515. }
  516. #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
  517. case STEP_COMPUTE_DIMM_PARMS:
  518. for (i = first_ctrl; i <= last_ctrl; i++) {
  519. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  520. dimm_params_t *pdimm =
  521. &(pinfo->dimm_params[i][j]);
  522. fsl_ddr_get_dimm_params(pdimm, i, j);
  523. }
  524. }
  525. debug("Filling dimm parameters from board specific file\n");
  526. #endif
  527. case STEP_COMPUTE_COMMON_PARMS:
  528. /*
  529. * STEP 3: Compute a common set of timing parameters
  530. * suitable for all of the DIMMs on each memory controller
  531. */
  532. for (i = first_ctrl; i <= last_ctrl; i++) {
  533. debug("Computing lowest common DIMM"
  534. " parameters for memctl=%u\n", i);
  535. compute_lowest_common_dimm_parameters
  536. (i,
  537. pinfo->dimm_params[i],
  538. &timing_params[i],
  539. CONFIG_DIMM_SLOTS_PER_CTLR);
  540. }
  541. case STEP_GATHER_OPTS:
  542. /* STEP 4: Gather configuration requirements from user */
  543. for (i = first_ctrl; i <= last_ctrl; i++) {
  544. debug("Reloading memory controller "
  545. "configuration options for memctl=%u\n", i);
  546. /*
  547. * This "reloads" the memory controller options
  548. * to defaults. If the user "edits" an option,
  549. * next_step points to the step after this,
  550. * which is currently STEP_ASSIGN_ADDRESSES.
  551. */
  552. populate_memctl_options(
  553. &timing_params[i],
  554. &pinfo->memctl_opts[i],
  555. pinfo->dimm_params[i], i);
  556. /*
  557. * For RDIMMs, JEDEC spec requires clocks to be stable
  558. * before reset signal is deasserted. For the boards
  559. * using fixed parameters, this function should be
  560. * be called from board init file.
  561. */
  562. if (timing_params[i].all_dimms_registered)
  563. assert_reset = 1;
  564. }
  565. if (assert_reset && !size_only) {
  566. if (pinfo->board_mem_reset) {
  567. debug("Asserting mem reset\n");
  568. pinfo->board_mem_reset();
  569. } else {
  570. debug("Asserting mem reset missing\n");
  571. }
  572. }
  573. case STEP_ASSIGN_ADDRESSES:
  574. /* STEP 5: Assign addresses to chip selects */
  575. check_interleaving_options(pinfo);
  576. total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
  577. debug("Total mem %llu assigned\n", total_mem);
  578. case STEP_COMPUTE_REGS:
  579. /* STEP 6: compute controller register values */
  580. debug("FSL Memory ctrl register computation\n");
  581. for (i = first_ctrl; i <= last_ctrl; i++) {
  582. if (timing_params[i].ndimms_present == 0) {
  583. memset(&ddr_reg[i], 0,
  584. sizeof(fsl_ddr_cfg_regs_t));
  585. continue;
  586. }
  587. compute_fsl_memctl_config_regs
  588. (i,
  589. &pinfo->memctl_opts[i],
  590. &ddr_reg[i], &timing_params[i],
  591. pinfo->dimm_params[i],
  592. dbw_capacity_adjust[i],
  593. size_only);
  594. }
  595. default:
  596. break;
  597. }
  598. {
  599. /*
  600. * Compute the amount of memory available just by
  601. * looking for the highest valid CSn_BNDS value.
  602. * This allows us to also experiment with using
  603. * only CS0 when using dual-rank DIMMs.
  604. */
  605. unsigned int max_end = 0;
  606. for (i = first_ctrl; i <= last_ctrl; i++) {
  607. for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
  608. fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
  609. if (reg->cs[j].config & 0x80000000) {
  610. unsigned int end;
  611. /*
  612. * 0xfffffff is a special value we put
  613. * for unused bnds
  614. */
  615. if (reg->cs[j].bnds == 0xffffffff)
  616. continue;
  617. end = reg->cs[j].bnds & 0xffff;
  618. if (end > max_end) {
  619. max_end = end;
  620. }
  621. }
  622. }
  623. }
  624. total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
  625. 0xFFFFFFULL) - pinfo->mem_base;
  626. }
  627. return total_mem;
  628. }
  629. phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
  630. {
  631. unsigned int i, first_ctrl, last_ctrl;
  632. #ifdef CONFIG_PPC
  633. unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
  634. #endif
  635. unsigned long long total_memory;
  636. int deassert_reset = 0;
  637. first_ctrl = pinfo->first_ctrl;
  638. last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
  639. /* Compute it once normally. */
  640. #ifdef CONFIG_FSL_DDR_INTERACTIVE
  641. if (tstc() && (getchar() == 'd')) { /* we got a key press of 'd' */
  642. total_memory = fsl_ddr_interactive(pinfo, 0);
  643. } else if (fsl_ddr_interactive_env_var_exists()) {
  644. total_memory = fsl_ddr_interactive(pinfo, 1);
  645. } else
  646. #endif
  647. total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
  648. /* setup 3-way interleaving before enabling DDRC */
  649. switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
  650. case FSL_DDR_3WAY_1KB_INTERLEAVING:
  651. case FSL_DDR_3WAY_4KB_INTERLEAVING:
  652. case FSL_DDR_3WAY_8KB_INTERLEAVING:
  653. fsl_ddr_set_intl3r(
  654. pinfo->memctl_opts[first_ctrl].
  655. memctl_interleaving_mode);
  656. break;
  657. default:
  658. break;
  659. }
  660. /*
  661. * Program configuration registers.
  662. * JEDEC specs requires clocks to be stable before deasserting reset
  663. * for RDIMMs. Clocks start after chip select is enabled and clock
  664. * control register is set. During step 1, all controllers have their
  665. * registers set but not enabled. Step 2 proceeds after deasserting
  666. * reset through board FPGA or GPIO.
  667. * For non-registered DIMMs, initialization can go through but it is
  668. * also OK to follow the same flow.
  669. */
  670. if (pinfo->board_need_mem_reset)
  671. deassert_reset = pinfo->board_need_mem_reset();
  672. for (i = first_ctrl; i <= last_ctrl; i++) {
  673. if (pinfo->common_timing_params[i].all_dimms_registered)
  674. deassert_reset = 1;
  675. }
  676. for (i = first_ctrl; i <= last_ctrl; i++) {
  677. debug("Programming controller %u\n", i);
  678. if (pinfo->common_timing_params[i].ndimms_present == 0) {
  679. debug("No dimms present on controller %u; "
  680. "skipping programming\n", i);
  681. continue;
  682. }
  683. /*
  684. * The following call with step = 1 returns before enabling
  685. * the controller. It has to finish with step = 2 later.
  686. */
  687. fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
  688. deassert_reset ? 1 : 0);
  689. }
  690. if (deassert_reset) {
  691. /* Use board FPGA or GPIO to deassert reset signal */
  692. if (pinfo->board_mem_de_reset) {
  693. debug("Deasserting mem reset\n");
  694. pinfo->board_mem_de_reset();
  695. } else {
  696. debug("Deasserting mem reset missing\n");
  697. }
  698. for (i = first_ctrl; i <= last_ctrl; i++) {
  699. /* Call with step = 2 to continue initialization */
  700. fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
  701. i, 2);
  702. }
  703. }
  704. #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
  705. fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
  706. #endif
  707. #ifdef CONFIG_PPC
  708. /* program LAWs */
  709. for (i = first_ctrl; i <= last_ctrl; i++) {
  710. if (pinfo->memctl_opts[i].memctl_interleaving) {
  711. switch (pinfo->memctl_opts[i].
  712. memctl_interleaving_mode) {
  713. case FSL_DDR_CACHE_LINE_INTERLEAVING:
  714. case FSL_DDR_PAGE_INTERLEAVING:
  715. case FSL_DDR_BANK_INTERLEAVING:
  716. case FSL_DDR_SUPERBANK_INTERLEAVING:
  717. if (i % 2)
  718. break;
  719. if (i == 0) {
  720. law_memctl = LAW_TRGT_IF_DDR_INTRLV;
  721. fsl_ddr_set_lawbar(
  722. &pinfo->common_timing_params[i],
  723. law_memctl, i);
  724. }
  725. #if CONFIG_SYS_NUM_DDR_CTLRS > 3
  726. else if (i == 2) {
  727. law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
  728. fsl_ddr_set_lawbar(
  729. &pinfo->common_timing_params[i],
  730. law_memctl, i);
  731. }
  732. #endif
  733. break;
  734. case FSL_DDR_3WAY_1KB_INTERLEAVING:
  735. case FSL_DDR_3WAY_4KB_INTERLEAVING:
  736. case FSL_DDR_3WAY_8KB_INTERLEAVING:
  737. law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
  738. if (i == 0) {
  739. fsl_ddr_set_lawbar(
  740. &pinfo->common_timing_params[i],
  741. law_memctl, i);
  742. }
  743. break;
  744. case FSL_DDR_4WAY_1KB_INTERLEAVING:
  745. case FSL_DDR_4WAY_4KB_INTERLEAVING:
  746. case FSL_DDR_4WAY_8KB_INTERLEAVING:
  747. law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
  748. if (i == 0)
  749. fsl_ddr_set_lawbar(
  750. &pinfo->common_timing_params[i],
  751. law_memctl, i);
  752. /* place holder for future 4-way interleaving */
  753. break;
  754. default:
  755. break;
  756. }
  757. } else {
  758. switch (i) {
  759. case 0:
  760. law_memctl = LAW_TRGT_IF_DDR_1;
  761. break;
  762. case 1:
  763. law_memctl = LAW_TRGT_IF_DDR_2;
  764. break;
  765. case 2:
  766. law_memctl = LAW_TRGT_IF_DDR_3;
  767. break;
  768. case 3:
  769. law_memctl = LAW_TRGT_IF_DDR_4;
  770. break;
  771. default:
  772. break;
  773. }
  774. fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
  775. law_memctl, i);
  776. }
  777. }
  778. #endif
  779. debug("total_memory by %s = %llu\n", __func__, total_memory);
  780. #if !defined(CONFIG_PHYS_64BIT)
  781. /* Check for 4G or more. Bad. */
  782. if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
  783. puts("Detected ");
  784. print_size(total_memory, " of memory\n");
  785. printf(" This U-Boot only supports < 4G of DDR\n");
  786. printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
  787. printf(" "); /* re-align to match init_dram print */
  788. total_memory = CONFIG_MAX_MEM_MAPPED;
  789. }
  790. #endif
  791. return total_memory;
  792. }
  793. /*
  794. * fsl_ddr_sdram(void) -- this is the main function to be
  795. * called by dram_init() in the board file.
  796. *
  797. * It returns amount of memory configured in bytes.
  798. */
  799. phys_size_t fsl_ddr_sdram(void)
  800. {
  801. fsl_ddr_info_t info;
  802. /* Reset info structure. */
  803. memset(&info, 0, sizeof(fsl_ddr_info_t));
  804. info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
  805. info.first_ctrl = 0;
  806. info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
  807. info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
  808. info.board_need_mem_reset = board_need_mem_reset;
  809. info.board_mem_reset = board_assert_mem_reset;
  810. info.board_mem_de_reset = board_deassert_mem_reset;
  811. remove_unused_controllers(&info);
  812. return __fsl_ddr_sdram(&info);
  813. }
  814. #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
  815. phys_size_t fsl_other_ddr_sdram(unsigned long long base,
  816. unsigned int first_ctrl,
  817. unsigned int num_ctrls,
  818. unsigned int dimm_slots_per_ctrl,
  819. int (*board_need_reset)(void),
  820. void (*board_reset)(void),
  821. void (*board_de_reset)(void))
  822. {
  823. fsl_ddr_info_t info;
  824. /* Reset info structure. */
  825. memset(&info, 0, sizeof(fsl_ddr_info_t));
  826. info.mem_base = base;
  827. info.first_ctrl = first_ctrl;
  828. info.num_ctrls = num_ctrls;
  829. info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
  830. info.board_need_mem_reset = board_need_reset;
  831. info.board_mem_reset = board_reset;
  832. info.board_mem_de_reset = board_de_reset;
  833. return __fsl_ddr_sdram(&info);
  834. }
  835. #endif
  836. /*
  837. * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
  838. * size of the total memory without setting ddr control registers.
  839. */
  840. phys_size_t
  841. fsl_ddr_sdram_size(void)
  842. {
  843. fsl_ddr_info_t info;
  844. unsigned long long total_memory = 0;
  845. memset(&info, 0 , sizeof(fsl_ddr_info_t));
  846. info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
  847. info.first_ctrl = 0;
  848. info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
  849. info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
  850. info.board_need_mem_reset = NULL;
  851. remove_unused_controllers(&info);
  852. /* Compute it once normally. */
  853. total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
  854. return total_memory;
  855. }