board_k2g.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K2G EVM : Board initialization
  4. *
  5. * (C) Copyright 2015
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <eeprom.h>
  10. #include <env.h>
  11. #include <hang.h>
  12. #include <image.h>
  13. #include <init.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/ti-common/keystone_net.h>
  16. #include <asm/arch/psc_defs.h>
  17. #include <asm/arch/mmc_host_def.h>
  18. #include <fdtdec.h>
  19. #include <i2c.h>
  20. #include <remoteproc.h>
  21. #include <linux/bitops.h>
  22. #include <linux/delay.h>
  23. #include "mux-k2g.h"
  24. #include "../common/board_detect.h"
  25. #define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
  26. const unsigned int sysclk_array[MAX_SYSCLK] = {
  27. 19200000,
  28. 24000000,
  29. 25000000,
  30. 26000000,
  31. };
  32. unsigned int get_external_clk(u32 clk)
  33. {
  34. unsigned int clk_freq;
  35. u8 sysclk_index = get_sysclk_index();
  36. switch (clk) {
  37. case sys_clk:
  38. clk_freq = sysclk_array[sysclk_index];
  39. break;
  40. case pa_clk:
  41. clk_freq = sysclk_array[sysclk_index];
  42. break;
  43. case tetris_clk:
  44. clk_freq = sysclk_array[sysclk_index];
  45. break;
  46. case ddr3a_clk:
  47. clk_freq = sysclk_array[sysclk_index];
  48. break;
  49. case uart_clk:
  50. clk_freq = sysclk_array[sysclk_index];
  51. break;
  52. default:
  53. clk_freq = 0;
  54. break;
  55. }
  56. return clk_freq;
  57. }
  58. int speeds[DEVSPEED_NUMSPDS] = {
  59. SPD400,
  60. SPD600,
  61. SPD800,
  62. SPD900,
  63. SPD1000,
  64. SPD900,
  65. SPD800,
  66. SPD600,
  67. SPD400,
  68. SPD200,
  69. };
  70. static int dev_speeds[DEVSPEED_NUMSPDS] = {
  71. SPD600,
  72. SPD800,
  73. SPD900,
  74. SPD1000,
  75. SPD900,
  76. SPD800,
  77. SPD600,
  78. SPD400,
  79. };
  80. static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
  81. [SYSCLK_19MHz] = {
  82. [SPD400] = {MAIN_PLL, 125, 3, 2},
  83. [SPD600] = {MAIN_PLL, 125, 2, 2},
  84. [SPD800] = {MAIN_PLL, 250, 3, 2},
  85. [SPD900] = {MAIN_PLL, 187, 2, 2},
  86. [SPD1000] = {MAIN_PLL, 104, 1, 2},
  87. },
  88. [SYSCLK_24MHz] = {
  89. [SPD400] = {MAIN_PLL, 100, 3, 2},
  90. [SPD600] = {MAIN_PLL, 300, 6, 2},
  91. [SPD800] = {MAIN_PLL, 200, 3, 2},
  92. [SPD900] = {MAIN_PLL, 75, 1, 2},
  93. [SPD1000] = {MAIN_PLL, 250, 3, 2},
  94. },
  95. [SYSCLK_25MHz] = {
  96. [SPD400] = {MAIN_PLL, 32, 1, 2},
  97. [SPD600] = {MAIN_PLL, 48, 1, 2},
  98. [SPD800] = {MAIN_PLL, 64, 1, 2},
  99. [SPD900] = {MAIN_PLL, 72, 1, 2},
  100. [SPD1000] = {MAIN_PLL, 80, 1, 2},
  101. },
  102. [SYSCLK_26MHz] = {
  103. [SPD400] = {MAIN_PLL, 400, 13, 2},
  104. [SPD600] = {MAIN_PLL, 230, 5, 2},
  105. [SPD800] = {MAIN_PLL, 123, 2, 2},
  106. [SPD900] = {MAIN_PLL, 69, 1, 2},
  107. [SPD1000] = {MAIN_PLL, 384, 5, 2},
  108. },
  109. };
  110. static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
  111. [SYSCLK_19MHz] = {
  112. [SPD200] = {TETRIS_PLL, 625, 6, 10},
  113. [SPD400] = {TETRIS_PLL, 125, 1, 6},
  114. [SPD600] = {TETRIS_PLL, 125, 1, 4},
  115. [SPD800] = {TETRIS_PLL, 333, 2, 4},
  116. [SPD900] = {TETRIS_PLL, 187, 2, 2},
  117. [SPD1000] = {TETRIS_PLL, 104, 1, 2},
  118. },
  119. [SYSCLK_24MHz] = {
  120. [SPD200] = {TETRIS_PLL, 250, 3, 10},
  121. [SPD400] = {TETRIS_PLL, 100, 1, 6},
  122. [SPD600] = {TETRIS_PLL, 100, 1, 4},
  123. [SPD800] = {TETRIS_PLL, 400, 3, 4},
  124. [SPD900] = {TETRIS_PLL, 75, 1, 2},
  125. [SPD1000] = {TETRIS_PLL, 250, 3, 2},
  126. },
  127. [SYSCLK_25MHz] = {
  128. [SPD200] = {TETRIS_PLL, 80, 1, 10},
  129. [SPD400] = {TETRIS_PLL, 96, 1, 6},
  130. [SPD600] = {TETRIS_PLL, 96, 1, 4},
  131. [SPD800] = {TETRIS_PLL, 128, 1, 4},
  132. [SPD900] = {TETRIS_PLL, 72, 1, 2},
  133. [SPD1000] = {TETRIS_PLL, 80, 1, 2},
  134. },
  135. [SYSCLK_26MHz] = {
  136. [SPD200] = {TETRIS_PLL, 307, 4, 10},
  137. [SPD400] = {TETRIS_PLL, 369, 4, 6},
  138. [SPD600] = {TETRIS_PLL, 369, 4, 4},
  139. [SPD800] = {TETRIS_PLL, 123, 1, 4},
  140. [SPD900] = {TETRIS_PLL, 69, 1, 2},
  141. [SPD1000] = {TETRIS_PLL, 384, 5, 2},
  142. },
  143. };
  144. static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
  145. [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
  146. [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
  147. [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
  148. [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
  149. };
  150. static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
  151. [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
  152. [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
  153. [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
  154. [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
  155. };
  156. static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
  157. [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
  158. [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
  159. [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
  160. [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
  161. };
  162. static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
  163. [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
  164. [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
  165. [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
  166. [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
  167. };
  168. struct pll_init_data *get_pll_init_data(int pll)
  169. {
  170. int speed;
  171. struct pll_init_data *data = NULL;
  172. u8 sysclk_index = get_sysclk_index();
  173. switch (pll) {
  174. case MAIN_PLL:
  175. speed = get_max_dev_speed(dev_speeds);
  176. data = &main_pll_config[sysclk_index][speed];
  177. break;
  178. case TETRIS_PLL:
  179. speed = get_max_arm_speed(speeds);
  180. data = &tetris_pll_config[sysclk_index][speed];
  181. break;
  182. case NSS_PLL:
  183. data = &nss_pll_config[sysclk_index];
  184. break;
  185. case UART_PLL:
  186. data = &uart_pll_config[sysclk_index];
  187. break;
  188. case DDR3_PLL:
  189. if (cpu_revision() & CPU_66AK2G1x) {
  190. speed = get_max_arm_speed(speeds);
  191. if (speed == SPD1000)
  192. data = &ddr3_pll_config_1066[sysclk_index];
  193. else
  194. data = &ddr3_pll_config_800[sysclk_index];
  195. } else {
  196. data = &ddr3_pll_config_800[sysclk_index];
  197. }
  198. break;
  199. default:
  200. data = NULL;
  201. }
  202. return data;
  203. }
  204. s16 divn_val[16] = {
  205. -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
  206. };
  207. #if defined(CONFIG_MMC)
  208. int board_mmc_init(struct bd_info *bis)
  209. {
  210. if (psc_enable_module(KS2_LPSC_MMC)) {
  211. printf("%s module enabled failed\n", __func__);
  212. return -1;
  213. }
  214. if (board_is_k2g_gp() || board_is_k2g_g1())
  215. omap_mmc_init(0, 0, 0, -1, -1);
  216. omap_mmc_init(1, 0, 0, -1, -1);
  217. return 0;
  218. }
  219. #endif
  220. #if defined(CONFIG_MULTI_DTB_FIT)
  221. int board_fit_config_name_match(const char *name)
  222. {
  223. bool eeprom_read = board_ti_was_eeprom_read();
  224. if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
  225. return 0;
  226. else if (!strcmp(name, "keystone-k2g-evm") &&
  227. (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
  228. return 0;
  229. else if (!strcmp(name, "keystone-k2g-ice") &&
  230. (board_ti_is("66AK2GIC") || board_is_k2g_i1()))
  231. return 0;
  232. else
  233. return -1;
  234. }
  235. #endif
  236. #if defined(CONFIG_DTB_RESELECT)
  237. static int k2g_alt_board_detect(void)
  238. {
  239. #if !CONFIG_IS_ENABLED(DM_I2C)
  240. int rc;
  241. rc = i2c_set_bus_num(1);
  242. if (rc)
  243. return rc;
  244. rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
  245. if (rc)
  246. return rc;
  247. #else
  248. struct udevice *bus, *dev;
  249. int rc;
  250. rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
  251. if (rc)
  252. return rc;
  253. rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
  254. if (rc)
  255. return rc;
  256. #endif
  257. ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
  258. return 0;
  259. }
  260. static void k2g_reset_mux_config(void)
  261. {
  262. /* Unlock the reset mux register */
  263. clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
  264. /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
  265. clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
  266. RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
  267. /* lock the reset mux register to prevent any spurious writes. */
  268. setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
  269. }
  270. int embedded_dtb_select(void)
  271. {
  272. int rc;
  273. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  274. CONFIG_EEPROM_CHIP_ADDRESS);
  275. if (rc) {
  276. rc = k2g_alt_board_detect();
  277. if (rc) {
  278. printf("Unable to do board detection\n");
  279. return -1;
  280. }
  281. }
  282. fdtdec_setup();
  283. k2g_mux_config();
  284. k2g_reset_mux_config();
  285. if (board_is_k2g_gp() || board_is_k2g_g1()) {
  286. /* deassert FLASH_HOLD */
  287. clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
  288. BIT(9));
  289. setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
  290. BIT(9));
  291. } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
  292. /* GBE Phy workaround. For Phy to latch the input
  293. * configuration, a GPIO reset is asserted at the
  294. * Phy reset pin to latch configuration correctly after SoC
  295. * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
  296. * board. Just do a low to high transition.
  297. */
  298. clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
  299. BIT(10));
  300. setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
  301. BIT(10));
  302. /* Delay just to get a transition to high */
  303. udelay(100);
  304. setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
  305. BIT(10));
  306. }
  307. return 0;
  308. }
  309. #endif
  310. #ifdef CONFIG_BOARD_LATE_INIT
  311. int board_late_init(void)
  312. {
  313. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
  314. int rc;
  315. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  316. CONFIG_EEPROM_CHIP_ADDRESS);
  317. if (rc)
  318. printf("ti_i2c_eeprom_init failed %d\n", rc);
  319. board_ti_set_ethaddr(1);
  320. #endif
  321. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  322. if (board_is_k2g_gp())
  323. env_set("board_name", "66AK2GGP\0");
  324. else if (board_is_k2g_g1())
  325. env_set("board_name", "66AK2GG1\0");
  326. else if (board_is_k2g_ice())
  327. env_set("board_name", "66AK2GIC\0");
  328. else if (board_is_k2g_i1())
  329. env_set("board_name", "66AK2GI1\0");
  330. #endif
  331. return 0;
  332. }
  333. #endif
  334. #ifdef CONFIG_BOARD_EARLY_INIT_F
  335. int board_early_init_f(void)
  336. {
  337. init_plls();
  338. k2g_mux_config();
  339. return 0;
  340. }
  341. #endif
  342. #ifdef CONFIG_SPL_BUILD
  343. void spl_init_keystone_plls(void)
  344. {
  345. init_plls();
  346. }
  347. #endif
  348. #ifdef CONFIG_TI_SECURE_DEVICE
  349. void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
  350. {
  351. int id = env_get_ulong("dev_pmmc", 10, 0);
  352. int ret;
  353. if (!rproc_is_initialized())
  354. rproc_init();
  355. ret = rproc_load(id, pmmc_image, pmmc_size);
  356. printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
  357. id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
  358. if (!ret)
  359. rproc_start(id);
  360. }
  361. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
  362. #endif