board.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM43XX based boards
  6. *
  7. * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <eeprom.h>
  11. #include <image.h>
  12. #include <asm/global_data.h>
  13. #include <dm/uclass.h>
  14. #include <env.h>
  15. #include <fdt_support.h>
  16. #include <i2c.h>
  17. #include <init.h>
  18. #include <net.h>
  19. #include <linux/errno.h>
  20. #include <spl.h>
  21. #include <usb.h>
  22. #include <asm/omap_sec_common.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/arch/mux.h>
  26. #include <asm/arch/ddr_defs.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/emif.h>
  29. #include <asm/omap_common.h>
  30. #include "../common/board_detect.h"
  31. #include "board.h"
  32. #include <power/pmic.h>
  33. #include <power/tps65218.h>
  34. #include <power/tps62362.h>
  35. #include <linux/usb/gadget.h>
  36. #include <dwc3-uboot.h>
  37. #include <dwc3-omap-uboot.h>
  38. #include <ti-usb-phy-uboot.h>
  39. DECLARE_GLOBAL_DATA_PTR;
  40. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  41. /*
  42. * Read header information from EEPROM into global structure.
  43. */
  44. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  45. void do_board_detect(void)
  46. {
  47. /* Ensure I2C is initialized for EEPROM access*/
  48. gpi2c_init();
  49. if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  50. CONFIG_EEPROM_CHIP_ADDRESS))
  51. printf("ti_i2c_eeprom_init failed\n");
  52. }
  53. #endif
  54. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  55. const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  56. { /* 19.2 MHz */
  57. {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
  58. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  59. {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
  60. {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
  61. {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
  62. {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
  63. },
  64. { /* 24 MHz */
  65. {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
  66. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  67. {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
  68. {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
  69. {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
  70. {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
  71. },
  72. { /* 25 MHz */
  73. {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
  74. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  75. {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
  76. {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
  77. {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
  78. {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
  79. },
  80. { /* 26 MHz */
  81. {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
  82. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  83. {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
  84. {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
  85. {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
  86. {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
  87. },
  88. };
  89. const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  90. {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
  91. {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
  92. {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
  93. {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
  94. };
  95. const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  96. {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  97. {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
  98. {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
  99. {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
  100. };
  101. const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
  102. {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
  103. {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
  104. {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
  105. {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
  106. };
  107. const struct dpll_params gp_evm_dpll_ddr = {
  108. 50, 2, 1, -1, 2, -1, -1};
  109. static const struct dpll_params idk_dpll_ddr = {
  110. 400, 23, 1, -1, 2, -1, -1
  111. };
  112. static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
  113. 0x00500050,
  114. 0x00350035,
  115. 0x00350035,
  116. 0x00350035,
  117. 0x00350035,
  118. 0x00350035,
  119. 0x00000000,
  120. 0x00000000,
  121. 0x00000000,
  122. 0x00000000,
  123. 0x00000000,
  124. 0x00000000,
  125. 0x00000000,
  126. 0x00000000,
  127. 0x00000000,
  128. 0x00000000,
  129. 0x00000000,
  130. 0x00000000,
  131. 0x40001000,
  132. 0x08102040
  133. };
  134. const struct ctrl_ioregs ioregs_lpddr2 = {
  135. .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
  136. .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
  137. .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
  138. .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  139. .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  140. .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  141. .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  142. .emif_sdram_config_ext = 0x1,
  143. };
  144. const struct emif_regs emif_regs_lpddr2 = {
  145. .sdram_config = 0x808012BA,
  146. .ref_ctrl = 0x0000040D,
  147. .sdram_tim1 = 0xEA86B411,
  148. .sdram_tim2 = 0x103A094A,
  149. .sdram_tim3 = 0x0F6BA37F,
  150. .read_idle_ctrl = 0x00050000,
  151. .zq_config = 0x50074BE4,
  152. .temp_alert_config = 0x0,
  153. .emif_rd_wr_lvl_rmp_win = 0x0,
  154. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  155. .emif_rd_wr_lvl_ctl = 0x0,
  156. .emif_ddr_phy_ctlr_1 = 0x0E284006,
  157. .emif_rd_wr_exec_thresh = 0x80000405,
  158. .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
  159. .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
  160. .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
  161. .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
  162. .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
  163. .emif_prio_class_serv_map = 0x80000001,
  164. .emif_connect_id_serv_1_map = 0x80000094,
  165. .emif_connect_id_serv_2_map = 0x00000000,
  166. .emif_cos_config = 0x000FFFFF
  167. };
  168. const struct ctrl_ioregs ioregs_ddr3 = {
  169. .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
  170. .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
  171. .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
  172. .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
  173. .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
  174. .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  175. .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  176. .emif_sdram_config_ext = 0xc163,
  177. };
  178. const struct emif_regs ddr3_emif_regs_400Mhz = {
  179. .sdram_config = 0x638413B2,
  180. .ref_ctrl = 0x00000C30,
  181. .sdram_tim1 = 0xEAAAD4DB,
  182. .sdram_tim2 = 0x266B7FDA,
  183. .sdram_tim3 = 0x107F8678,
  184. .read_idle_ctrl = 0x00050000,
  185. .zq_config = 0x50074BE4,
  186. .temp_alert_config = 0x0,
  187. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  188. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  189. .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
  190. .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
  191. .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
  192. .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
  193. .emif_rd_wr_lvl_rmp_win = 0x0,
  194. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  195. .emif_rd_wr_lvl_ctl = 0x0,
  196. .emif_rd_wr_exec_thresh = 0x80000405,
  197. .emif_prio_class_serv_map = 0x80000001,
  198. .emif_connect_id_serv_1_map = 0x80000094,
  199. .emif_connect_id_serv_2_map = 0x00000000,
  200. .emif_cos_config = 0x000FFFFF
  201. };
  202. /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
  203. const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
  204. .sdram_config = 0x638413B2,
  205. .ref_ctrl = 0x00000C30,
  206. .sdram_tim1 = 0xEAAAD4DB,
  207. .sdram_tim2 = 0x266B7FDA,
  208. .sdram_tim3 = 0x107F8678,
  209. .read_idle_ctrl = 0x00050000,
  210. .zq_config = 0x50074BE4,
  211. .temp_alert_config = 0x0,
  212. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  213. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  214. .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
  215. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  216. .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
  217. .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
  218. .emif_rd_wr_exec_thresh = 0x80000405,
  219. .emif_prio_class_serv_map = 0x80000001,
  220. .emif_connect_id_serv_1_map = 0x80000094,
  221. .emif_connect_id_serv_2_map = 0x00000000,
  222. .emif_cos_config = 0x000FFFFF
  223. };
  224. /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
  225. const struct emif_regs ddr3_emif_regs_400Mhz_production = {
  226. .sdram_config = 0x638413B2,
  227. .ref_ctrl = 0x00000C30,
  228. .sdram_tim1 = 0xEAAAD4DB,
  229. .sdram_tim2 = 0x266B7FDA,
  230. .sdram_tim3 = 0x107F8678,
  231. .read_idle_ctrl = 0x00050000,
  232. .zq_config = 0x50074BE4,
  233. .temp_alert_config = 0x0,
  234. .emif_ddr_phy_ctlr_1 = 0x00048008,
  235. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  236. .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
  237. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  238. .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
  239. .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
  240. .emif_rd_wr_exec_thresh = 0x80000405,
  241. .emif_prio_class_serv_map = 0x80000001,
  242. .emif_connect_id_serv_1_map = 0x80000094,
  243. .emif_connect_id_serv_2_map = 0x00000000,
  244. .emif_cos_config = 0x000FFFFF
  245. };
  246. static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
  247. .sdram_config = 0x638413b2,
  248. .sdram_config2 = 0x00000000,
  249. .ref_ctrl = 0x00000c30,
  250. .sdram_tim1 = 0xeaaad4db,
  251. .sdram_tim2 = 0x266b7fda,
  252. .sdram_tim3 = 0x107f8678,
  253. .read_idle_ctrl = 0x00050000,
  254. .zq_config = 0x50074be4,
  255. .temp_alert_config = 0x0,
  256. .emif_ddr_phy_ctlr_1 = 0x0e084008,
  257. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  258. .emif_ddr_ext_phy_ctrl_2 = 0x89,
  259. .emif_ddr_ext_phy_ctrl_3 = 0x90,
  260. .emif_ddr_ext_phy_ctrl_4 = 0x8e,
  261. .emif_ddr_ext_phy_ctrl_5 = 0x8d,
  262. .emif_rd_wr_lvl_rmp_win = 0x0,
  263. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  264. .emif_rd_wr_lvl_ctl = 0x00000000,
  265. .emif_rd_wr_exec_thresh = 0x80000000,
  266. .emif_prio_class_serv_map = 0x80000001,
  267. .emif_connect_id_serv_1_map = 0x80000094,
  268. .emif_connect_id_serv_2_map = 0x00000000,
  269. .emif_cos_config = 0x000FFFFF
  270. };
  271. static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
  272. .sdram_config = 0x61a11b32,
  273. .sdram_config2 = 0x00000000,
  274. .ref_ctrl = 0x00000c30,
  275. .sdram_tim1 = 0xeaaad4db,
  276. .sdram_tim2 = 0x266b7fda,
  277. .sdram_tim3 = 0x107f8678,
  278. .read_idle_ctrl = 0x00050000,
  279. .zq_config = 0x50074be4,
  280. .temp_alert_config = 0x00000000,
  281. .emif_ddr_phy_ctlr_1 = 0x00008009,
  282. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  283. .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
  284. .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
  285. .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
  286. .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
  287. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  288. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  289. .emif_rd_wr_lvl_ctl = 0x00000000,
  290. .emif_rd_wr_exec_thresh = 0x00000405,
  291. .emif_prio_class_serv_map = 0x00000000,
  292. .emif_connect_id_serv_1_map = 0x00000000,
  293. .emif_connect_id_serv_2_map = 0x00000000,
  294. .emif_cos_config = 0x00ffffff
  295. };
  296. void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
  297. {
  298. if (board_is_eposevm()) {
  299. *regs = ext_phy_ctrl_const_base_lpddr2;
  300. *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
  301. }
  302. return;
  303. }
  304. const struct dpll_params *get_dpll_ddr_params(void)
  305. {
  306. int ind = get_sys_clk_index();
  307. if (board_is_eposevm())
  308. return &epos_evm_dpll_ddr[ind];
  309. else if (board_is_evm() || board_is_sk())
  310. return &gp_evm_dpll_ddr;
  311. else if (board_is_idk())
  312. return &idk_dpll_ddr;
  313. printf(" Board '%s' not supported\n", board_ti_get_name());
  314. return NULL;
  315. }
  316. /*
  317. * get_opp_offset:
  318. * Returns the index for safest OPP of the device to boot.
  319. * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
  320. * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
  321. * This data is read from dev_attribute register which is e-fused.
  322. * A'1' in bit indicates OPP disabled and not available, a '0' indicates
  323. * OPP available. Lowest OPP starts with min_off. So returning the
  324. * bit with rightmost '0'.
  325. */
  326. static int get_opp_offset(int max_off, int min_off)
  327. {
  328. struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
  329. int opp, offset, i;
  330. /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
  331. opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
  332. for (i = max_off; i >= min_off; i--) {
  333. offset = opp & (1 << i);
  334. if (!offset)
  335. return i;
  336. }
  337. return min_off;
  338. }
  339. const struct dpll_params *get_dpll_mpu_params(void)
  340. {
  341. int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
  342. u32 ind = get_sys_clk_index();
  343. return &dpll_mpu[ind][opp];
  344. }
  345. const struct dpll_params *get_dpll_core_params(void)
  346. {
  347. int ind = get_sys_clk_index();
  348. return &dpll_core[ind];
  349. }
  350. const struct dpll_params *get_dpll_per_params(void)
  351. {
  352. int ind = get_sys_clk_index();
  353. return &dpll_per[ind];
  354. }
  355. void scale_vcores_generic(u32 m)
  356. {
  357. int mpu_vdd, ddr_volt;
  358. #if !CONFIG_IS_ENABLED(DM_I2C)
  359. if (i2c_probe(TPS65218_CHIP_PM))
  360. return;
  361. #else
  362. if (power_tps65218_init(0))
  363. return;
  364. #endif
  365. switch (m) {
  366. case 1000:
  367. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
  368. break;
  369. case 800:
  370. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
  371. break;
  372. case 720:
  373. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
  374. break;
  375. case 600:
  376. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
  377. break;
  378. case 300:
  379. mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
  380. break;
  381. default:
  382. puts("Unknown MPU clock, not scaling\n");
  383. return;
  384. }
  385. /* Set DCDC1 (CORE) voltage to 1.1V */
  386. if (tps65218_voltage_update(TPS65218_DCDC1,
  387. TPS65218_DCDC_VOLT_SEL_1100MV)) {
  388. printf("%s failure\n", __func__);
  389. return;
  390. }
  391. /* Set DCDC2 (MPU) voltage */
  392. if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
  393. printf("%s failure\n", __func__);
  394. return;
  395. }
  396. if (board_is_eposevm())
  397. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
  398. else
  399. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
  400. /* Set DCDC3 (DDR) voltage */
  401. if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
  402. printf("%s failure\n", __func__);
  403. return;
  404. }
  405. }
  406. void scale_vcores_idk(u32 m)
  407. {
  408. int mpu_vdd;
  409. #if !CONFIG_IS_ENABLED(DM_I2C)
  410. if (i2c_probe(TPS62362_I2C_ADDR))
  411. return;
  412. #else
  413. if (power_tps62362_init(0))
  414. return;
  415. #endif
  416. switch (m) {
  417. case 1000:
  418. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  419. break;
  420. case 800:
  421. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
  422. break;
  423. case 720:
  424. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
  425. break;
  426. case 600:
  427. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
  428. break;
  429. case 300:
  430. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  431. break;
  432. default:
  433. puts("Unknown MPU clock, not scaling\n");
  434. return;
  435. }
  436. /* Set VDD_MPU voltage */
  437. if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
  438. printf("%s failure\n", __func__);
  439. return;
  440. }
  441. }
  442. void gpi2c_init(void)
  443. {
  444. /* When needed to be invoked prior to BSS initialization */
  445. static bool first_time = true;
  446. if (first_time) {
  447. enable_i2c0_pin_mux();
  448. #if !CONFIG_IS_ENABLED(DM_I2C)
  449. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  450. CONFIG_SYS_OMAP24_I2C_SLAVE);
  451. #endif
  452. first_time = false;
  453. }
  454. }
  455. void scale_vcores(void)
  456. {
  457. const struct dpll_params *mpu_params;
  458. /* Ensure I2C is initialized for PMIC configuration */
  459. gpi2c_init();
  460. /* Get the frequency */
  461. mpu_params = get_dpll_mpu_params();
  462. if (board_is_idk())
  463. scale_vcores_idk(mpu_params->m);
  464. else
  465. scale_vcores_generic(mpu_params->m);
  466. }
  467. void set_uart_mux_conf(void)
  468. {
  469. enable_uart0_pin_mux();
  470. }
  471. void set_mux_conf_regs(void)
  472. {
  473. enable_board_pin_mux();
  474. }
  475. static void enable_vtt_regulator(void)
  476. {
  477. u32 temp;
  478. /* enable module */
  479. writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
  480. /* enable output for GPIO5_7 */
  481. writel(GPIO_SETDATAOUT(7),
  482. AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
  483. temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  484. temp = temp & ~(GPIO_OE_ENABLE(7));
  485. writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  486. }
  487. enum {
  488. RTC_BOARD_EPOS = 1,
  489. RTC_BOARD_EVM14,
  490. RTC_BOARD_EVM12,
  491. RTC_BOARD_GPEVM,
  492. RTC_BOARD_SK,
  493. };
  494. /*
  495. * In the rtc_only+DRR in self-refresh boot path we have the board type info
  496. * in the rtc scratch pad register hence we bypass the costly i2c reads to
  497. * eeprom and directly programthe board name string
  498. */
  499. void rtc_only_update_board_type(u32 btype)
  500. {
  501. const char *name = "";
  502. const char *rev = "1.0";
  503. switch (btype) {
  504. case RTC_BOARD_EPOS:
  505. name = "AM43EPOS";
  506. break;
  507. case RTC_BOARD_EVM14:
  508. name = "AM43__GP";
  509. rev = "1.4";
  510. break;
  511. case RTC_BOARD_EVM12:
  512. name = "AM43__GP";
  513. rev = "1.2";
  514. break;
  515. case RTC_BOARD_GPEVM:
  516. name = "AM43__GP";
  517. break;
  518. case RTC_BOARD_SK:
  519. name = "AM43__SK";
  520. break;
  521. }
  522. ti_i2c_eeprom_am_set(name, rev);
  523. }
  524. u32 rtc_only_get_board_type(void)
  525. {
  526. if (board_is_eposevm())
  527. return RTC_BOARD_EPOS;
  528. else if (board_is_evm_14_or_later())
  529. return RTC_BOARD_EVM14;
  530. else if (board_is_evm_12_or_later())
  531. return RTC_BOARD_EVM12;
  532. else if (board_is_gpevm())
  533. return RTC_BOARD_GPEVM;
  534. else if (board_is_sk())
  535. return RTC_BOARD_SK;
  536. return 0;
  537. }
  538. void sdram_init(void)
  539. {
  540. /*
  541. * EPOS EVM has 1GB LPDDR2 connected to EMIF.
  542. * GP EMV has 1GB DDR3 connected to EMIF
  543. * along with VTT regulator.
  544. */
  545. if (board_is_eposevm()) {
  546. config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
  547. } else if (board_is_evm_14_or_later()) {
  548. enable_vtt_regulator();
  549. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  550. &ddr3_emif_regs_400Mhz_production, 0);
  551. } else if (board_is_evm_12_or_later()) {
  552. enable_vtt_regulator();
  553. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  554. &ddr3_emif_regs_400Mhz_beta, 0);
  555. } else if (board_is_evm()) {
  556. enable_vtt_regulator();
  557. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  558. &ddr3_emif_regs_400Mhz, 0);
  559. } else if (board_is_sk()) {
  560. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  561. &ddr3_sk_emif_regs_400Mhz, 0);
  562. } else if (board_is_idk()) {
  563. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  564. &ddr3_idk_emif_regs_400Mhz, 0);
  565. }
  566. }
  567. #endif
  568. /* setup board specific PMIC */
  569. int power_init_board(void)
  570. {
  571. int rc;
  572. #if !CONFIG_IS_ENABLED(DM_I2C)
  573. struct pmic *p = NULL;
  574. #endif
  575. if (board_is_idk()) {
  576. rc = power_tps62362_init(0);
  577. if (rc)
  578. goto done;
  579. #if !CONFIG_IS_ENABLED(DM_I2C)
  580. p = pmic_get("TPS62362");
  581. if (!p || pmic_probe(p))
  582. goto done;
  583. #endif
  584. puts("PMIC: TPS62362\n");
  585. } else {
  586. rc = power_tps65218_init(0);
  587. if (rc)
  588. goto done;
  589. #if !CONFIG_IS_ENABLED(DM_I2C)
  590. p = pmic_get("TPS65218_PMIC");
  591. if (!p || pmic_probe(p))
  592. goto done;
  593. #endif
  594. puts("PMIC: TPS65218\n");
  595. }
  596. done:
  597. return 0;
  598. }
  599. int board_init(void)
  600. {
  601. struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
  602. u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
  603. modena_init0_bw_integer, modena_init0_watermark_0;
  604. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  605. gpmc_init();
  606. /*
  607. * Call this to initialize *ctrl again
  608. */
  609. hw_data_init();
  610. /* Clear all important bits for DSS errata that may need to be tweaked*/
  611. mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
  612. MREQPRIO_0_SAB_INIT0_MASK;
  613. mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
  614. modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
  615. BW_LIMITER_BW_FRAC_MASK;
  616. modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
  617. BW_LIMITER_BW_INT_MASK;
  618. modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
  619. BW_LIMITER_BW_WATERMARK_MASK;
  620. /* Setting MReq Priority of the DSS*/
  621. mreqprio_0 |= 0x77;
  622. /*
  623. * Set L3 Fast Configuration Register
  624. * Limiting bandwith for ARM core to 700 MBPS
  625. */
  626. modena_init0_bw_fractional |= 0x10;
  627. modena_init0_bw_integer |= 0x3;
  628. writel(mreqprio_0, &cdev->mreqprio_0);
  629. writel(mreqprio_1, &cdev->mreqprio_1);
  630. writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
  631. writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
  632. writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
  633. return 0;
  634. }
  635. #ifdef CONFIG_BOARD_LATE_INIT
  636. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  637. static int device_okay(const char *path)
  638. {
  639. int node;
  640. node = fdt_path_offset(gd->fdt_blob, path);
  641. if (node < 0)
  642. return 0;
  643. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  644. }
  645. #endif
  646. int board_late_init(void)
  647. {
  648. struct udevice *dev;
  649. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  650. set_board_info_env(NULL);
  651. /*
  652. * Default FIT boot on HS devices. Non FIT images are not allowed
  653. * on HS devices.
  654. */
  655. if (get_device_type() == HS_DEVICE)
  656. env_set("boot_fit", "1");
  657. #endif
  658. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  659. if (device_okay("/ocp/omap_dwc3@48380000"))
  660. enable_usb_clocks(0);
  661. if (device_okay("/ocp/omap_dwc3@483c0000"))
  662. enable_usb_clocks(1);
  663. #endif
  664. /* Just probe the potentially supported cdce913 device */
  665. uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
  666. return 0;
  667. }
  668. #endif
  669. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  670. #ifdef CONFIG_USB_DWC3
  671. static struct dwc3_device usb_otg_ss1 = {
  672. .maximum_speed = USB_SPEED_HIGH,
  673. .base = USB_OTG_SS1_BASE,
  674. .tx_fifo_resize = false,
  675. .index = 0,
  676. };
  677. static struct dwc3_omap_device usb_otg_ss1_glue = {
  678. .base = (void *)USB_OTG_SS1_GLUE_BASE,
  679. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  680. .index = 0,
  681. };
  682. static struct ti_usb_phy_device usb_phy1_device = {
  683. .usb2_phy_power = (void *)USB2_PHY1_POWER,
  684. .index = 0,
  685. };
  686. static struct dwc3_device usb_otg_ss2 = {
  687. .maximum_speed = USB_SPEED_HIGH,
  688. .base = USB_OTG_SS2_BASE,
  689. .tx_fifo_resize = false,
  690. .index = 1,
  691. };
  692. static struct dwc3_omap_device usb_otg_ss2_glue = {
  693. .base = (void *)USB_OTG_SS2_GLUE_BASE,
  694. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  695. .index = 1,
  696. };
  697. static struct ti_usb_phy_device usb_phy2_device = {
  698. .usb2_phy_power = (void *)USB2_PHY2_POWER,
  699. .index = 1,
  700. };
  701. int usb_gadget_handle_interrupts(int index)
  702. {
  703. u32 status;
  704. status = dwc3_omap_uboot_interrupt_status(index);
  705. if (status)
  706. dwc3_uboot_handle_interrupt(index);
  707. return 0;
  708. }
  709. #endif /* CONFIG_USB_DWC3 */
  710. #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
  711. int board_usb_init(int index, enum usb_init_type init)
  712. {
  713. enable_usb_clocks(index);
  714. #ifdef CONFIG_USB_DWC3
  715. switch (index) {
  716. case 0:
  717. if (init == USB_INIT_DEVICE) {
  718. usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
  719. usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  720. dwc3_omap_uboot_init(&usb_otg_ss1_glue);
  721. ti_usb_phy_uboot_init(&usb_phy1_device);
  722. dwc3_uboot_init(&usb_otg_ss1);
  723. }
  724. break;
  725. case 1:
  726. if (init == USB_INIT_DEVICE) {
  727. usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
  728. usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  729. ti_usb_phy_uboot_init(&usb_phy2_device);
  730. dwc3_omap_uboot_init(&usb_otg_ss2_glue);
  731. dwc3_uboot_init(&usb_otg_ss2);
  732. }
  733. break;
  734. default:
  735. printf("Invalid Controller Index\n");
  736. }
  737. #endif
  738. return 0;
  739. }
  740. int board_usb_cleanup(int index, enum usb_init_type init)
  741. {
  742. #ifdef CONFIG_USB_DWC3
  743. switch (index) {
  744. case 0:
  745. case 1:
  746. if (init == USB_INIT_DEVICE) {
  747. ti_usb_phy_uboot_exit(index);
  748. dwc3_uboot_exit(index);
  749. dwc3_omap_uboot_exit(index);
  750. }
  751. break;
  752. default:
  753. printf("Invalid Controller Index\n");
  754. }
  755. #endif
  756. disable_usb_clocks(index);
  757. return 0;
  758. }
  759. #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
  760. #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  761. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  762. int ft_board_setup(void *blob, struct bd_info *bd)
  763. {
  764. ft_cpu_setup(blob, bd);
  765. return 0;
  766. }
  767. #endif
  768. #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
  769. int board_fit_config_name_match(const char *name)
  770. {
  771. bool eeprom_read = board_ti_was_eeprom_read();
  772. if (!strcmp(name, "am4372-generic") && !eeprom_read)
  773. return 0;
  774. else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
  775. return 0;
  776. else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
  777. return 0;
  778. else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
  779. return 0;
  780. else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
  781. return 0;
  782. else
  783. return -1;
  784. }
  785. #endif
  786. #ifdef CONFIG_DTB_RESELECT
  787. int embedded_dtb_select(void)
  788. {
  789. do_board_detect();
  790. fdtdec_setup();
  791. return 0;
  792. }
  793. #endif
  794. #ifdef CONFIG_TI_SECURE_DEVICE
  795. void board_fit_image_post_process(void **p_image, size_t *p_size)
  796. {
  797. secure_boot_verify_image(p_image, p_size);
  798. }
  799. void board_tee_image_process(ulong tee_image, size_t tee_size)
  800. {
  801. secure_tee_install((u32)tee_image);
  802. }
  803. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  804. #endif