mux.c 16 KB

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  1. /*
  2. * mux.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <common.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/mux.h>
  19. #include <asm/io.h>
  20. #include <i2c.h>
  21. #include "../common/board_detect.h"
  22. #include "board.h"
  23. static struct module_pin_mux uart0_pin_mux[] = {
  24. {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
  25. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
  26. {-1},
  27. };
  28. static struct module_pin_mux uart1_pin_mux[] = {
  29. {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
  30. {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
  31. {-1},
  32. };
  33. static struct module_pin_mux uart2_pin_mux[] = {
  34. {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
  35. {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
  36. {-1},
  37. };
  38. static struct module_pin_mux uart3_pin_mux[] = {
  39. {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
  40. {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
  41. {-1},
  42. };
  43. static struct module_pin_mux uart4_pin_mux[] = {
  44. {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
  45. {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
  46. {-1},
  47. };
  48. static struct module_pin_mux uart5_pin_mux[] = {
  49. {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
  50. {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
  51. {-1},
  52. };
  53. static struct module_pin_mux mmc0_pin_mux[] = {
  54. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
  55. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
  56. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
  57. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
  58. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
  59. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
  60. {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
  61. {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */
  62. {-1},
  63. };
  64. static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
  65. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
  66. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
  67. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
  68. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
  69. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
  70. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
  71. {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
  72. {-1},
  73. };
  74. static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
  75. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
  76. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
  77. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
  78. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
  79. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
  80. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
  81. {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
  82. {-1},
  83. };
  84. static struct module_pin_mux mmc1_pin_mux[] = {
  85. {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
  86. {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
  87. {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
  88. {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
  89. {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  90. {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
  91. {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
  92. {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
  93. {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
  94. {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
  95. {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
  96. {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
  97. {-1},
  98. };
  99. static struct module_pin_mux i2c0_pin_mux[] = {
  100. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
  101. PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
  102. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
  103. PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
  104. {-1},
  105. };
  106. static struct module_pin_mux i2c1_pin_mux[] = {
  107. {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
  108. PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
  109. {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
  110. PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
  111. {-1},
  112. };
  113. static struct module_pin_mux spi0_pin_mux[] = {
  114. {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
  115. {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
  116. PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
  117. {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
  118. {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
  119. PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
  120. {-1},
  121. };
  122. static struct module_pin_mux gpio0_7_pin_mux[] = {
  123. {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
  124. {-1},
  125. };
  126. static struct module_pin_mux gpio0_18_pin_mux[] = {
  127. {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */
  128. {-1},
  129. };
  130. static struct module_pin_mux rgmii1_pin_mux[] = {
  131. {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
  132. {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
  133. {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
  134. {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
  135. {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
  136. {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
  137. {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
  138. {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
  139. {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
  140. {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
  141. {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
  142. {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
  143. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  144. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  145. {-1},
  146. };
  147. static struct module_pin_mux mii1_pin_mux[] = {
  148. {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
  149. {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
  150. {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
  151. {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
  152. {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
  153. {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
  154. {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
  155. {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
  156. {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
  157. {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
  158. {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
  159. {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
  160. {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
  161. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
  162. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  163. {-1},
  164. };
  165. static struct module_pin_mux rmii1_pin_mux[] = {
  166. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  167. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
  168. {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */
  169. {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */
  170. {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
  171. {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
  172. {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
  173. {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */
  174. {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */
  175. {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
  176. {-1},
  177. };
  178. #ifdef CONFIG_MTD_RAW_NAND
  179. static struct module_pin_mux nand_pin_mux[] = {
  180. {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
  181. {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
  182. {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
  183. {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
  184. {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
  185. {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
  186. {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
  187. {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
  188. #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  189. {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
  190. {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
  191. {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
  192. {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
  193. {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
  194. {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
  195. {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
  196. {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
  197. #endif
  198. {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
  199. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
  200. {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
  201. {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
  202. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
  203. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
  204. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
  205. {-1},
  206. };
  207. #elif defined(CONFIG_NOR)
  208. static struct module_pin_mux bone_norcape_pin_mux[] = {
  209. {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
  210. {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
  211. {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
  212. {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
  213. {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
  214. {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
  215. {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
  216. {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
  217. {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
  218. {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
  219. {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
  220. {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
  221. {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
  222. {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
  223. {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
  224. {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
  225. {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
  226. {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
  227. {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
  228. {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
  229. {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
  230. {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
  231. {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
  232. {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
  233. {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
  234. {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
  235. {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
  236. {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
  237. {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
  238. {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
  239. {-1},
  240. };
  241. #endif
  242. static struct module_pin_mux uart3_icev2_pin_mux[] = {
  243. {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
  244. {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */
  245. {-1},
  246. };
  247. #if defined(CONFIG_NOR_BOOT)
  248. void enable_norboot_pin_mux(void)
  249. {
  250. configure_module_pin_mux(bone_norcape_pin_mux);
  251. }
  252. #endif
  253. void enable_uart0_pin_mux(void)
  254. {
  255. configure_module_pin_mux(uart0_pin_mux);
  256. }
  257. void enable_uart1_pin_mux(void)
  258. {
  259. configure_module_pin_mux(uart1_pin_mux);
  260. }
  261. void enable_uart2_pin_mux(void)
  262. {
  263. configure_module_pin_mux(uart2_pin_mux);
  264. }
  265. void enable_uart3_pin_mux(void)
  266. {
  267. configure_module_pin_mux(uart3_pin_mux);
  268. }
  269. void enable_uart4_pin_mux(void)
  270. {
  271. configure_module_pin_mux(uart4_pin_mux);
  272. }
  273. void enable_uart5_pin_mux(void)
  274. {
  275. configure_module_pin_mux(uart5_pin_mux);
  276. }
  277. void enable_i2c0_pin_mux(void)
  278. {
  279. configure_module_pin_mux(i2c0_pin_mux);
  280. }
  281. /*
  282. * The AM335x GP EVM, if daughter card(s) are connected, can have 8
  283. * different profiles. These profiles determine what peripherals are
  284. * valid and need pinmux to be configured.
  285. */
  286. #define PROFILE_NONE 0x0
  287. #define PROFILE_0 (1 << 0)
  288. #define PROFILE_1 (1 << 1)
  289. #define PROFILE_2 (1 << 2)
  290. #define PROFILE_3 (1 << 3)
  291. #define PROFILE_4 (1 << 4)
  292. #define PROFILE_5 (1 << 5)
  293. #define PROFILE_6 (1 << 6)
  294. #define PROFILE_7 (1 << 7)
  295. #define PROFILE_MASK 0x7
  296. #define PROFILE_ALL 0xFF
  297. /* CPLD registers */
  298. #define I2C_CPLD_ADDR 0x35
  299. #define CFG_REG 0x10
  300. static unsigned short detect_daughter_board_profile(void)
  301. {
  302. unsigned short val;
  303. #if !CONFIG_IS_ENABLED(DM_I2C)
  304. if (i2c_probe(I2C_CPLD_ADDR))
  305. return PROFILE_NONE;
  306. if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
  307. return PROFILE_NONE;
  308. #else
  309. struct udevice *dev = NULL;
  310. int rc;
  311. rc = i2c_get_chip_for_busnum(0, I2C_CPLD_ADDR, 1, &dev);
  312. if (rc)
  313. return PROFILE_NONE;
  314. rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2);
  315. if (rc)
  316. return PROFILE_NONE;
  317. #endif
  318. return (1 << (val & PROFILE_MASK));
  319. }
  320. void enable_board_pin_mux(void)
  321. {
  322. /* Do board-specific muxes. */
  323. if (board_is_bone()) {
  324. /* Beaglebone pinmux */
  325. configure_module_pin_mux(mii1_pin_mux);
  326. configure_module_pin_mux(mmc0_pin_mux);
  327. #if defined(CONFIG_MTD_RAW_NAND)
  328. configure_module_pin_mux(nand_pin_mux);
  329. #elif defined(CONFIG_NOR)
  330. configure_module_pin_mux(bone_norcape_pin_mux);
  331. #else
  332. configure_module_pin_mux(mmc1_pin_mux);
  333. #endif
  334. } else if (board_is_gp_evm()) {
  335. /* General Purpose EVM */
  336. unsigned short profile = detect_daughter_board_profile();
  337. configure_module_pin_mux(rgmii1_pin_mux);
  338. configure_module_pin_mux(mmc0_pin_mux);
  339. /* In profile #2 i2c1 and spi0 conflict. */
  340. if (profile & ~PROFILE_2)
  341. configure_module_pin_mux(i2c1_pin_mux);
  342. /* Profiles 2 & 3 don't have NAND */
  343. #ifdef CONFIG_MTD_RAW_NAND
  344. if (profile & ~(PROFILE_2 | PROFILE_3))
  345. configure_module_pin_mux(nand_pin_mux);
  346. #endif
  347. else if (profile == PROFILE_2) {
  348. configure_module_pin_mux(mmc1_pin_mux);
  349. configure_module_pin_mux(spi0_pin_mux);
  350. }
  351. } else if (board_is_idk()) {
  352. /* Industrial Motor Control (IDK) */
  353. configure_module_pin_mux(mii1_pin_mux);
  354. configure_module_pin_mux(mmc0_no_cd_pin_mux);
  355. } else if (board_is_evm_sk()) {
  356. /* Starter Kit EVM */
  357. configure_module_pin_mux(i2c1_pin_mux);
  358. configure_module_pin_mux(gpio0_7_pin_mux);
  359. configure_module_pin_mux(rgmii1_pin_mux);
  360. configure_module_pin_mux(mmc0_pin_mux_sk_evm);
  361. } else if (board_is_bone_lt()) {
  362. if (board_is_bben()) {
  363. /* SanCloud Beaglebone LT Enhanced pinmux */
  364. configure_module_pin_mux(rgmii1_pin_mux);
  365. } else {
  366. /* Beaglebone LT pinmux */
  367. configure_module_pin_mux(mii1_pin_mux);
  368. }
  369. /* Beaglebone LT pinmux */
  370. configure_module_pin_mux(mmc0_pin_mux);
  371. #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_EMMC_BOOT)
  372. configure_module_pin_mux(nand_pin_mux);
  373. #elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
  374. configure_module_pin_mux(bone_norcape_pin_mux);
  375. #else
  376. configure_module_pin_mux(mmc1_pin_mux);
  377. #endif
  378. } else if (board_is_pb()) {
  379. configure_module_pin_mux(mii1_pin_mux);
  380. configure_module_pin_mux(mmc0_pin_mux);
  381. } else if (board_is_icev2()) {
  382. configure_module_pin_mux(mmc0_pin_mux);
  383. configure_module_pin_mux(gpio0_18_pin_mux);
  384. configure_module_pin_mux(uart3_icev2_pin_mux);
  385. configure_module_pin_mux(rmii1_pin_mux);
  386. configure_module_pin_mux(spi0_pin_mux);
  387. } else {
  388. /* Unknown board. We might still be able to boot. */
  389. puts("Bad EEPROM or unknown board, cannot configure pinmux.");
  390. }
  391. }