trats.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Samsung Electronics
  4. * Heungjun Kim <riverful.kim@samsung.com>
  5. * Kyungmin Park <kyungmin.park@samsung.com>
  6. * Donghwa Lee <dh09.lee@samsung.com>
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <lcd.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/gpio.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/pinmux.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/mipi_dsim.h>
  18. #include <asm/arch/watchdog.h>
  19. #include <asm/arch/power.h>
  20. #include <linux/delay.h>
  21. #include <power/pmic.h>
  22. #include <usb/dwc2_udc.h>
  23. #include <power/max8997_pmic.h>
  24. #include <power/max8997_muic.h>
  25. #include <power/battery.h>
  26. #include <power/max17042_fg.h>
  27. #include <power/pmic.h>
  28. #include <libtizen.h>
  29. #include <usb.h>
  30. #include <usb_mass_storage.h>
  31. #include "setup.h"
  32. unsigned int board_rev;
  33. #ifdef CONFIG_REVISION_TAG
  34. u32 get_board_rev(void)
  35. {
  36. return board_rev;
  37. }
  38. #endif
  39. static void check_hw_revision(void);
  40. struct dwc2_plat_otg_data s5pc210_otg_data;
  41. int exynos_init(void)
  42. {
  43. check_hw_revision();
  44. printf("HW Revision:\t0x%x\n", board_rev);
  45. return 0;
  46. }
  47. #if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
  48. static void trats_low_power_mode(void)
  49. {
  50. struct exynos4_clock *clk =
  51. (struct exynos4_clock *)samsung_get_base_clock();
  52. struct exynos4_power *pwr =
  53. (struct exynos4_power *)samsung_get_base_power();
  54. /* Power down CORE1 */
  55. /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
  56. writel(0x0, &pwr->arm_core1_configuration);
  57. /* Change the APLL frequency */
  58. /* ENABLE (1 enable) | LOCKED (1 locked) */
  59. /* [31] | [29] */
  60. /* FSEL | MDIV | PDIV | SDIV */
  61. /* [27] | [25:16] | [13:8] | [2:0] */
  62. writel(0xa0c80604, &clk->apll_con0);
  63. /* Change CPU0 clock divider */
  64. /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
  65. /* [30:28] | [26:24] | [22:20] | [18:16] */
  66. /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
  67. /* [14:12] | [10:8] | [6:4] | [2:0] */
  68. writel(0x00000100, &clk->div_cpu0);
  69. /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
  70. while (readl(&clk->div_stat_cpu0) & 0x1111111)
  71. continue;
  72. /* Change clock divider ratio for DMC */
  73. /* DMCP_RATIO | DMCD_RATIO */
  74. /* [22:20] | [18:16] */
  75. /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
  76. /* [14:12] | [10:8] | [6:4] | [2:0] */
  77. writel(0x13113117, &clk->div_dmc0);
  78. /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
  79. while (readl(&clk->div_stat_dmc0) & 0x11111111)
  80. continue;
  81. /* Turn off unnecessary power domains */
  82. writel(0x0, &pwr->xxti_configuration); /* XXTI */
  83. writel(0x0, &pwr->cam_configuration); /* CAM */
  84. writel(0x0, &pwr->tv_configuration); /* TV */
  85. writel(0x0, &pwr->mfc_configuration); /* MFC */
  86. writel(0x0, &pwr->g3d_configuration); /* G3D */
  87. writel(0x0, &pwr->gps_configuration); /* GPS */
  88. writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
  89. /* Turn off unnecessary clocks */
  90. writel(0x0, &clk->gate_ip_cam); /* CAM */
  91. writel(0x0, &clk->gate_ip_tv); /* TV */
  92. writel(0x0, &clk->gate_ip_mfc); /* MFC */
  93. writel(0x0, &clk->gate_ip_g3d); /* G3D */
  94. writel(0x0, &clk->gate_ip_image); /* IMAGE */
  95. writel(0x0, &clk->gate_ip_gps); /* GPS */
  96. }
  97. #endif
  98. int exynos_power_init(void)
  99. {
  100. #if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
  101. int chrg, ret;
  102. struct power_battery *pb;
  103. struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
  104. /*
  105. * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
  106. * to logical I2C adapter 0
  107. *
  108. * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
  109. * to logical I2C adapter 1
  110. */
  111. ret = power_fg_init(I2C_9);
  112. ret |= power_muic_init(I2C_5);
  113. ret |= power_bat_init(0);
  114. if (ret)
  115. return ret;
  116. p_fg = pmic_get("MAX17042_FG");
  117. if (!p_fg) {
  118. puts("MAX17042_FG: Not found\n");
  119. return -ENODEV;
  120. }
  121. p_chrg = pmic_get("MAX8997_PMIC");
  122. if (!p_chrg) {
  123. puts("MAX8997_PMIC: Not found\n");
  124. return -ENODEV;
  125. }
  126. p_muic = pmic_get("MAX8997_MUIC");
  127. if (!p_muic) {
  128. puts("MAX8997_MUIC: Not found\n");
  129. return -ENODEV;
  130. }
  131. p_bat = pmic_get("BAT_TRATS");
  132. if (!p_bat) {
  133. puts("BAT_TRATS: Not found\n");
  134. return -ENODEV;
  135. }
  136. p_fg->parent = p_bat;
  137. p_chrg->parent = p_bat;
  138. p_muic->parent = p_bat;
  139. p_bat->low_power_mode = trats_low_power_mode;
  140. p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
  141. pb = p_bat->pbat;
  142. chrg = p_muic->chrg->chrg_type(p_muic);
  143. debug("CHARGER TYPE: %d\n", chrg);
  144. if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
  145. puts("No battery detected\n");
  146. return 0;
  147. }
  148. p_fg->fg->fg_battery_check(p_fg, p_bat);
  149. if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
  150. puts("CHARGE Battery !\n");
  151. #endif
  152. return 0;
  153. }
  154. static unsigned int get_hw_revision(void)
  155. {
  156. int hwrev = 0;
  157. char str[10];
  158. int i;
  159. /* hw_rev[3:0] == GPE1[3:0] */
  160. for (i = 0; i < 4; i++) {
  161. int pin = i + EXYNOS4_GPIO_E10;
  162. sprintf(str, "hw_rev%d", i);
  163. gpio_request(pin, str);
  164. gpio_cfg_pin(pin, S5P_GPIO_INPUT);
  165. gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
  166. }
  167. udelay(1);
  168. for (i = 0; i < 4; i++)
  169. hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
  170. debug("hwrev 0x%x\n", hwrev);
  171. return hwrev;
  172. }
  173. static void check_hw_revision(void)
  174. {
  175. int hwrev;
  176. hwrev = get_hw_revision();
  177. board_rev |= hwrev;
  178. }
  179. #ifdef CONFIG_USB_GADGET
  180. static int s5pc210_phy_control(int on)
  181. {
  182. struct udevice *dev;
  183. int reg, ret;
  184. ret = pmic_get("max8997-pmic", &dev);
  185. if (ret)
  186. return ret;
  187. if (on) {
  188. reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
  189. reg |= ENSAFEOUT1;
  190. ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
  191. if (ret) {
  192. puts("MAX8997 setting error!\n");
  193. return ret;
  194. }
  195. reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
  196. reg |= EN_LDO;
  197. ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
  198. if (ret) {
  199. puts("MAX8997 setting error!\n");
  200. return ret;
  201. }
  202. reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
  203. reg |= EN_LDO;
  204. ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
  205. if (ret) {
  206. puts("MAX8997 setting error!\n");
  207. return ret;
  208. }
  209. } else {
  210. reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
  211. reg &= DIS_LDO;
  212. ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
  213. if (ret) {
  214. puts("MAX8997 setting error!\n");
  215. return ret;
  216. }
  217. reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
  218. reg &= DIS_LDO;
  219. ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
  220. if (ret) {
  221. puts("MAX8997 setting error!\n");
  222. return ret;
  223. }
  224. reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
  225. reg &= ~ENSAFEOUT1;
  226. ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
  227. if (ret) {
  228. puts("MAX8997 setting error!\n");
  229. return ret;
  230. }
  231. }
  232. return 0;
  233. }
  234. struct dwc2_plat_otg_data s5pc210_otg_data = {
  235. .phy_control = s5pc210_phy_control,
  236. .regs_phy = EXYNOS4_USBPHY_BASE,
  237. .regs_otg = EXYNOS4_USBOTG_BASE,
  238. .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
  239. .usb_flags = PHY0_SLEEP,
  240. };
  241. int board_usb_init(int index, enum usb_init_type init)
  242. {
  243. debug("USB_udc_probe\n");
  244. return dwc2_udc_probe(&s5pc210_otg_data);
  245. }
  246. int g_dnl_board_usb_cable_connected(void)
  247. {
  248. #if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
  249. struct pmic *muic = pmic_get("MAX8997_MUIC");
  250. if (!muic)
  251. return 0;
  252. return !!muic->chrg->chrg_type(muic);
  253. #else
  254. return false;
  255. #endif
  256. }
  257. #endif
  258. static void pmic_reset(void)
  259. {
  260. gpio_direction_output(EXYNOS4_GPIO_X07, 1);
  261. gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
  262. }
  263. static void board_clock_init(void)
  264. {
  265. struct exynos4_clock *clk =
  266. (struct exynos4_clock *)samsung_get_base_clock();
  267. writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
  268. writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
  269. writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
  270. writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
  271. writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
  272. writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
  273. writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
  274. writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
  275. writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
  276. writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
  277. writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
  278. writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
  279. writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
  280. writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
  281. writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
  282. writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
  283. writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
  284. writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
  285. writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
  286. writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
  287. writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
  288. writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
  289. writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
  290. writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
  291. writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
  292. writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
  293. writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
  294. writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
  295. writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
  296. writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
  297. writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
  298. writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
  299. writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
  300. writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
  301. writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
  302. writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
  303. writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
  304. writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
  305. writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
  306. writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
  307. }
  308. static void board_power_init(void)
  309. {
  310. struct exynos4_power *pwr =
  311. (struct exynos4_power *)samsung_get_base_power();
  312. /* PS HOLD */
  313. writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
  314. /* Set power down */
  315. writel(0, (unsigned int)&pwr->cam_configuration);
  316. writel(0, (unsigned int)&pwr->tv_configuration);
  317. writel(0, (unsigned int)&pwr->mfc_configuration);
  318. writel(0, (unsigned int)&pwr->g3d_configuration);
  319. writel(0, (unsigned int)&pwr->lcd1_configuration);
  320. writel(0, (unsigned int)&pwr->gps_configuration);
  321. writel(0, (unsigned int)&pwr->gps_alive_configuration);
  322. /* It is necessary to power down core 1 */
  323. /* to successfully boot CPU1 in kernel */
  324. writel(0, (unsigned int)&pwr->arm_core1_configuration);
  325. }
  326. static void exynos_uart_init(void)
  327. {
  328. /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
  329. gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
  330. gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
  331. gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
  332. }
  333. int exynos_early_init_f(void)
  334. {
  335. wdt_stop();
  336. pmic_reset();
  337. board_clock_init();
  338. exynos_uart_init();
  339. board_power_init();
  340. return 0;
  341. }
  342. void exynos_reset_lcd(void)
  343. {
  344. gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
  345. gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
  346. udelay(10000);
  347. gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
  348. udelay(10000);
  349. gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
  350. }
  351. int lcd_power(void)
  352. {
  353. #if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
  354. int ret = 0;
  355. struct pmic *p = pmic_get("MAX8997_PMIC");
  356. if (!p)
  357. return -ENODEV;
  358. if (pmic_probe(p))
  359. return 0;
  360. /* LDO15 voltage: 2.2v */
  361. ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
  362. /* LDO13 voltage: 3.0v */
  363. ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
  364. if (ret) {
  365. puts("MAX8997 LDO setting error!\n");
  366. return -1;
  367. }
  368. #endif
  369. return 0;
  370. }
  371. int mipi_power(void)
  372. {
  373. #if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
  374. int ret = 0;
  375. struct pmic *p = pmic_get("MAX8997_PMIC");
  376. if (!p)
  377. return -ENODEV;
  378. if (pmic_probe(p))
  379. return 0;
  380. /* LDO3 voltage: 1.1v */
  381. ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
  382. /* LDO4 voltage: 1.8v */
  383. ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
  384. if (ret) {
  385. puts("MAX8997 LDO setting error!\n");
  386. return -1;
  387. }
  388. #endif
  389. return 0;
  390. }
  391. #ifdef CONFIG_LCD
  392. void exynos_lcd_misc_init(vidinfo_t *vid)
  393. {
  394. #ifdef CONFIG_TIZEN
  395. get_tizen_logo_info(vid);
  396. #endif
  397. #ifdef CONFIG_S6E8AX0
  398. s6e8ax0_init();
  399. env_set("lcdinfo", "lcd=s6e8ax0");
  400. #endif
  401. }
  402. #endif