t208xqds.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2013 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <env.h>
  9. #include <fdt_support.h>
  10. #include <i2c.h>
  11. #include <image.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <netdev.h>
  15. #include <asm/global_data.h>
  16. #include <linux/compiler.h>
  17. #include <asm/mmu.h>
  18. #include <asm/processor.h>
  19. #include <asm/immap_85xx.h>
  20. #include <asm/fsl_law.h>
  21. #include <asm/fsl_serdes.h>
  22. #include <asm/fsl_liodn.h>
  23. #include <fm_eth.h>
  24. #include "../common/qixis.h"
  25. #include "../common/vsc3316_3308.h"
  26. #include "../common/vid.h"
  27. #include "t208xqds.h"
  28. #include "t208xqds_qixis.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. int checkboard(void)
  31. {
  32. char buf[64];
  33. u8 sw;
  34. struct cpu_type *cpu = gd->arch.cpu;
  35. static const char *freq[4] = {
  36. "100.00MHZ(from 8T49N222A)", "125.00MHz",
  37. "156.25MHZ", "100.00MHz"
  38. };
  39. printf("Board: %sQDS, ", cpu->name);
  40. sw = QIXIS_READ(arch);
  41. printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  42. printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  43. #ifdef CONFIG_SDCARD
  44. puts("SD/MMC\n");
  45. #elif CONFIG_SPIFLASH
  46. puts("SPI\n");
  47. #else
  48. sw = QIXIS_READ(brdcfg[0]);
  49. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  50. if (sw < 0x8)
  51. printf("vBank%d\n", sw);
  52. else if (sw == 0x8)
  53. puts("Promjet\n");
  54. else if (sw == 0x9)
  55. puts("NAND\n");
  56. else
  57. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  58. #endif
  59. printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  60. qixis_read_tag(buf), (int)qixis_read_minor());
  61. /* the timestamp string contains "\n" at the end */
  62. printf(" on %s", qixis_read_time(buf));
  63. puts("SERDES Reference Clocks:\n");
  64. sw = QIXIS_READ(brdcfg[2]);
  65. printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  66. freq[(sw >> 4) & 0x3]);
  67. printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  68. freq[sw & 0x3]);
  69. return 0;
  70. }
  71. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  72. {
  73. int ret;
  74. #if CONFIG_IS_ENABLED(DM_I2C)
  75. struct udevice *dev;
  76. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  77. if (ret) {
  78. printf("%s: Cannot find udev for a bus %d\n", __func__,
  79. bus_num);
  80. return ret;
  81. }
  82. ret = dm_i2c_write(dev, 0, &ch, 1);
  83. #else
  84. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  85. #endif
  86. if (ret) {
  87. puts("PCA: failed to select proper channel\n");
  88. return ret;
  89. }
  90. return 0;
  91. }
  92. int i2c_multiplexer_select_vid_channel(u8 channel)
  93. {
  94. return select_i2c_ch_pca9547(channel, 0);
  95. }
  96. int brd_mux_lane_to_slot(void)
  97. {
  98. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  99. u32 srds_prtcl_s1;
  100. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  101. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  102. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  103. #if defined(CONFIG_TARGET_T2080QDS)
  104. u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  105. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  106. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  107. #endif
  108. switch (srds_prtcl_s1) {
  109. case 0:
  110. /* SerDes1 is not enabled */
  111. break;
  112. #if defined(CONFIG_TARGET_T2080QDS)
  113. case 0x1b:
  114. case 0x1c:
  115. case 0xa2:
  116. /* SD1(A:D) => SLOT3 SGMII
  117. * SD1(G:H) => SLOT1 SGMII
  118. */
  119. QIXIS_WRITE(brdcfg[12], 0x1a);
  120. break;
  121. case 0x94:
  122. case 0x95:
  123. /* SD1(A:B) => SLOT3 SGMII@1.25bps
  124. * SD1(C:D) => SFP Module, SGMII@3.125bps
  125. * SD1(E:H) => SLOT1 SGMII@1.25bps
  126. */
  127. case 0x96:
  128. /* SD1(A:B) => SLOT3 SGMII@1.25bps
  129. * SD1(C) => SFP Module, SGMII@3.125bps
  130. * SD1(D) => SFP Module, SGMII@1.25bps
  131. * SD1(E:H) => SLOT1 PCIe4 x4
  132. */
  133. QIXIS_WRITE(brdcfg[12], 0x3a);
  134. break;
  135. case 0x50:
  136. case 0x51:
  137. /* SD1(A:D) => SLOT3 XAUI
  138. * SD1(E) => SLOT1 PCIe4
  139. * SD1(F:H) => SLOT2 SGMII
  140. */
  141. QIXIS_WRITE(brdcfg[12], 0x15);
  142. break;
  143. case 0x66:
  144. case 0x67:
  145. /* SD1(A:D) => XFI cage
  146. * SD1(E:H) => SLOT1 PCIe4
  147. */
  148. QIXIS_WRITE(brdcfg[12], 0xfe);
  149. break;
  150. case 0x6a:
  151. case 0x6b:
  152. /* SD1(A:D) => XFI cage
  153. * SD1(E) => SLOT1 PCIe4
  154. * SD1(F:H) => SLOT2 SGMII
  155. */
  156. QIXIS_WRITE(brdcfg[12], 0xf1);
  157. break;
  158. case 0x6c:
  159. case 0x6d:
  160. /* SD1(A:B) => XFI cage
  161. * SD1(C:D) => SLOT3 SGMII
  162. * SD1(E:H) => SLOT1 PCIe4
  163. */
  164. QIXIS_WRITE(brdcfg[12], 0xda);
  165. break;
  166. case 0x6e:
  167. /* SD1(A:B) => SFP Module, XFI
  168. * SD1(C:D) => SLOT3 SGMII
  169. * SD1(E:F) => SLOT1 PCIe4 x2
  170. * SD1(G:H) => SLOT2 SGMII
  171. */
  172. QIXIS_WRITE(brdcfg[12], 0xd9);
  173. break;
  174. case 0xda:
  175. /* SD1(A:H) => SLOT3 PCIe3 x8
  176. */
  177. QIXIS_WRITE(brdcfg[12], 0x0);
  178. break;
  179. case 0xc8:
  180. /* SD1(A) => SLOT3 PCIe3 x1
  181. * SD1(B) => SFP Module, SGMII@1.25bps
  182. * SD1(C:D) => SFP Module, SGMII@3.125bps
  183. * SD1(E:F) => SLOT1 PCIe4 x2
  184. * SD1(G:H) => SLOT2 SGMII
  185. */
  186. QIXIS_WRITE(brdcfg[12], 0x79);
  187. break;
  188. case 0xab:
  189. /* SD1(A:D) => SLOT3 PCIe3 x4
  190. * SD1(E:H) => SLOT1 PCIe4 x4
  191. */
  192. QIXIS_WRITE(brdcfg[12], 0x1a);
  193. break;
  194. #elif defined(CONFIG_TARGET_T2081QDS)
  195. case 0x50:
  196. case 0x51:
  197. /* SD1(A:D) => SLOT2 XAUI
  198. * SD1(E) => SLOT1 PCIe4 x1
  199. * SD1(F:H) => SLOT3 SGMII
  200. */
  201. QIXIS_WRITE(brdcfg[12], 0x98);
  202. QIXIS_WRITE(brdcfg[13], 0x70);
  203. break;
  204. case 0x6a:
  205. case 0x6b:
  206. /* SD1(A:D) => XFI SFP Module
  207. * SD1(E) => SLOT1 PCIe4 x1
  208. * SD1(F:H) => SLOT3 SGMII
  209. */
  210. QIXIS_WRITE(brdcfg[12], 0x80);
  211. QIXIS_WRITE(brdcfg[13], 0x70);
  212. break;
  213. case 0x6c:
  214. case 0x6d:
  215. /* SD1(A:B) => XFI SFP Module
  216. * SD1(C:D) => SLOT2 SGMII
  217. * SD1(E:H) => SLOT1 PCIe4 x4
  218. */
  219. QIXIS_WRITE(brdcfg[12], 0xe8);
  220. QIXIS_WRITE(brdcfg[13], 0x0);
  221. break;
  222. case 0xaa:
  223. case 0xab:
  224. /* SD1(A:D) => SLOT2 PCIe3 x4
  225. * SD1(F:H) => SLOT1 SGMI4 x4
  226. */
  227. QIXIS_WRITE(brdcfg[12], 0xf8);
  228. QIXIS_WRITE(brdcfg[13], 0x0);
  229. break;
  230. case 0xca:
  231. case 0xcb:
  232. /* SD1(A) => SLOT2 PCIe3 x1
  233. * SD1(B) => SLOT7 SGMII
  234. * SD1(C) => SLOT6 SGMII
  235. * SD1(D) => SLOT5 SGMII
  236. * SD1(E) => SLOT1 PCIe4 x1
  237. * SD1(F:H) => SLOT3 SGMII
  238. */
  239. QIXIS_WRITE(brdcfg[12], 0x80);
  240. QIXIS_WRITE(brdcfg[13], 0x70);
  241. break;
  242. case 0xde:
  243. case 0xdf:
  244. /* SD1(A:D) => SLOT2 PCIe3 x4
  245. * SD1(E) => SLOT1 PCIe4 x1
  246. * SD1(F) => SLOT4 PCIe1 x1
  247. * SD1(G) => SLOT3 PCIe2 x1
  248. * SD1(H) => SLOT7 SGMII
  249. */
  250. QIXIS_WRITE(brdcfg[12], 0x98);
  251. QIXIS_WRITE(brdcfg[13], 0x25);
  252. break;
  253. case 0xf2:
  254. /* SD1(A) => SLOT2 PCIe3 x1
  255. * SD1(B:D) => SLOT7 SGMII
  256. * SD1(E) => SLOT1 PCIe4 x1
  257. * SD1(F) => SLOT4 PCIe1 x1
  258. * SD1(G) => SLOT3 PCIe2 x1
  259. * SD1(H) => SLOT7 SGMII
  260. */
  261. QIXIS_WRITE(brdcfg[12], 0x81);
  262. QIXIS_WRITE(brdcfg[13], 0xa5);
  263. break;
  264. #endif
  265. default:
  266. printf("WARNING: unsupported for SerDes1 Protocol %d\n",
  267. srds_prtcl_s1);
  268. return -1;
  269. }
  270. #ifdef CONFIG_TARGET_T2080QDS
  271. switch (srds_prtcl_s2) {
  272. case 0:
  273. /* SerDes2 is not enabled */
  274. break;
  275. case 0x01:
  276. case 0x02:
  277. /* SD2(A:H) => SLOT4 PCIe1 */
  278. QIXIS_WRITE(brdcfg[13], 0x10);
  279. break;
  280. case 0x15:
  281. case 0x16:
  282. /*
  283. * SD2(A:D) => SLOT4 PCIe1
  284. * SD2(E:F) => SLOT5 PCIe2
  285. * SD2(G:H) => SATA1,SATA2
  286. */
  287. QIXIS_WRITE(brdcfg[13], 0xb0);
  288. break;
  289. case 0x18:
  290. /*
  291. * SD2(A:D) => SLOT4 PCIe1
  292. * SD2(E:F) => SLOT5 Aurora
  293. * SD2(G:H) => SATA1,SATA2
  294. */
  295. QIXIS_WRITE(brdcfg[13], 0x78);
  296. break;
  297. case 0x1f:
  298. /*
  299. * SD2(A:D) => SLOT4 PCIe1
  300. * SD2(E:H) => SLOT5 PCIe2
  301. */
  302. QIXIS_WRITE(brdcfg[13], 0xa0);
  303. break;
  304. case 0x29:
  305. case 0x2d:
  306. case 0x2e:
  307. /*
  308. * SD2(A:D) => SLOT4 SRIO2
  309. * SD2(E:H) => SLOT5 SRIO1
  310. */
  311. QIXIS_WRITE(brdcfg[13], 0xa0);
  312. break;
  313. case 0x36:
  314. /*
  315. * SD2(A:D) => SLOT4 SRIO2
  316. * SD2(E:F) => Aurora
  317. * SD2(G:H) => SATA1,SATA2
  318. */
  319. QIXIS_WRITE(brdcfg[13], 0x78);
  320. break;
  321. default:
  322. printf("WARNING: unsupported for SerDes2 Protocol %d\n",
  323. srds_prtcl_s2);
  324. return -1;
  325. }
  326. #endif
  327. return 0;
  328. }
  329. static void esdhc_adapter_card_ident(void)
  330. {
  331. u8 card_id, value;
  332. card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
  333. switch (card_id) {
  334. case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
  335. value = QIXIS_READ(brdcfg[5]);
  336. value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
  337. QIXIS_WRITE(brdcfg[5], value);
  338. break;
  339. case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
  340. value = QIXIS_READ(pwr_ctl[1]);
  341. value |= QIXIS_EVDD_BY_SDHC_VS;
  342. QIXIS_WRITE(pwr_ctl[1], value);
  343. break;
  344. case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
  345. value = QIXIS_READ(brdcfg[5]);
  346. value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
  347. QIXIS_WRITE(brdcfg[5], value);
  348. break;
  349. default:
  350. break;
  351. }
  352. }
  353. int board_early_init_r(void)
  354. {
  355. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  356. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  357. /*
  358. * Remap Boot flash + PROMJET region to caching-inhibited
  359. * so that flash can be erased properly.
  360. */
  361. /* Flush d-cache and invalidate i-cache of any FLASH data */
  362. flush_dcache();
  363. invalidate_icache();
  364. if (flash_esel == -1) {
  365. /* very unlikely unless something is messed up */
  366. puts("Error: Could not find TLB for FLASH BASE\n");
  367. flash_esel = 2; /* give our best effort to continue */
  368. } else {
  369. /* invalidate existing TLB entry for flash + promjet */
  370. disable_tlb(flash_esel);
  371. }
  372. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  373. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  374. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  375. /* Disable remote I2C connection to qixis fpga */
  376. QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
  377. /*
  378. * Adjust core voltage according to voltage ID
  379. * This function changes I2C mux to channel 2.
  380. */
  381. if (adjust_vdd(0))
  382. printf("Warning: Adjusting core voltage failed.\n");
  383. brd_mux_lane_to_slot();
  384. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  385. esdhc_adapter_card_ident();
  386. return 0;
  387. }
  388. unsigned long get_board_sys_clk(void)
  389. {
  390. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  391. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  392. /* use accurate clock measurement */
  393. int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
  394. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  395. u32 val;
  396. val = freq * base;
  397. if (val) {
  398. debug("SYS Clock measurement is: %d\n", val);
  399. return val;
  400. } else {
  401. printf("Warning: SYS clock measurement is invalid, ");
  402. printf("using value from brdcfg1.\n");
  403. }
  404. #endif
  405. switch (sysclk_conf & 0x0F) {
  406. case QIXIS_SYSCLK_83:
  407. return 83333333;
  408. case QIXIS_SYSCLK_100:
  409. return 100000000;
  410. case QIXIS_SYSCLK_125:
  411. return 125000000;
  412. case QIXIS_SYSCLK_133:
  413. return 133333333;
  414. case QIXIS_SYSCLK_150:
  415. return 150000000;
  416. case QIXIS_SYSCLK_160:
  417. return 160000000;
  418. case QIXIS_SYSCLK_166:
  419. return 166666666;
  420. }
  421. return 66666666;
  422. }
  423. unsigned long get_board_ddr_clk(void)
  424. {
  425. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  426. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  427. /* use accurate clock measurement */
  428. int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
  429. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  430. u32 val;
  431. val = freq * base;
  432. if (val) {
  433. debug("DDR Clock measurement is: %d\n", val);
  434. return val;
  435. } else {
  436. printf("Warning: DDR clock measurement is invalid, ");
  437. printf("using value from brdcfg1.\n");
  438. }
  439. #endif
  440. switch ((ddrclk_conf & 0x30) >> 4) {
  441. case QIXIS_DDRCLK_100:
  442. return 100000000;
  443. case QIXIS_DDRCLK_125:
  444. return 125000000;
  445. case QIXIS_DDRCLK_133:
  446. return 133333333;
  447. }
  448. return 66666666;
  449. }
  450. int misc_init_r(void)
  451. {
  452. return 0;
  453. }
  454. int ft_board_setup(void *blob, struct bd_info *bd)
  455. {
  456. phys_addr_t base;
  457. phys_size_t size;
  458. ft_cpu_setup(blob, bd);
  459. base = env_get_bootm_low();
  460. size = env_get_bootm_size();
  461. fdt_fixup_memory(blob, (u64)base, (u64)size);
  462. #ifdef CONFIG_PCI
  463. pci_of_setup(blob, bd);
  464. #endif
  465. fdt_fixup_liodn(blob);
  466. fsl_fdt_fixup_dr_usb(blob, bd);
  467. #ifdef CONFIG_SYS_DPAA_FMAN
  468. #ifndef CONFIG_DM_ETH
  469. fdt_fixup_fman_ethernet(blob);
  470. #endif
  471. fdt_fixup_board_enet(blob);
  472. #endif
  473. return 0;
  474. }