lx2160a.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018-2020 NXP
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <asm/global_data.h>
  10. #include <dm/platform_data/serial_pl01x.h>
  11. #include <i2c.h>
  12. #include <malloc.h>
  13. #include <errno.h>
  14. #include <netdev.h>
  15. #include <fsl_ddr.h>
  16. #include <fsl_sec.h>
  17. #include <asm/io.h>
  18. #include <fdt_support.h>
  19. #include <linux/bitops.h>
  20. #include <linux/libfdt.h>
  21. #include <linux/delay.h>
  22. #include <fsl-mc/fsl_mc.h>
  23. #include <env_internal.h>
  24. #include <efi_loader.h>
  25. #include <asm/arch/mmu.h>
  26. #include <hwconfig.h>
  27. #include <asm/arch/clock.h>
  28. #include <asm/arch/config.h>
  29. #include <asm/arch/fsl_serdes.h>
  30. #include <asm/arch/soc.h>
  31. #include "../common/qixis.h"
  32. #include "../common/vid.h"
  33. #include <fsl_immap.h>
  34. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  35. #include "lx2160a.h"
  36. #ifdef CONFIG_EMC2305
  37. #include "../common/emc2305.h"
  38. #endif
  39. #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  40. #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
  41. #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
  42. #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
  43. #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
  44. #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
  45. #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
  46. #define SDHC1_BASE_PMUX_DSPI 2
  47. #define SDHC2_BASE_PMUX_DSPI 2
  48. #define IIC5_PMUX_SPI3 3
  49. #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
  50. DECLARE_GLOBAL_DATA_PTR;
  51. static struct pl01x_serial_plat serial0 = {
  52. #if CONFIG_CONS_INDEX == 0
  53. .base = CONFIG_SYS_SERIAL0,
  54. #elif CONFIG_CONS_INDEX == 1
  55. .base = CONFIG_SYS_SERIAL1,
  56. #else
  57. #error "Unsupported console index value."
  58. #endif
  59. .type = TYPE_PL011,
  60. };
  61. U_BOOT_DRVINFO(nxp_serial0) = {
  62. .name = "serial_pl01x",
  63. .plat = &serial0,
  64. };
  65. static struct pl01x_serial_plat serial1 = {
  66. .base = CONFIG_SYS_SERIAL1,
  67. .type = TYPE_PL011,
  68. };
  69. U_BOOT_DRVINFO(nxp_serial1) = {
  70. .name = "serial_pl01x",
  71. .plat = &serial1,
  72. };
  73. int select_i2c_ch_pca9547(u8 ch)
  74. {
  75. int ret;
  76. #if !CONFIG_IS_ENABLED(DM_I2C)
  77. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  78. #else
  79. struct udevice *dev;
  80. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  81. if (!ret)
  82. ret = dm_i2c_write(dev, 0, &ch, 1);
  83. #endif
  84. if (ret) {
  85. puts("PCA: failed to select proper channel\n");
  86. return ret;
  87. }
  88. return 0;
  89. }
  90. static void uart_get_clock(void)
  91. {
  92. serial0.clock = get_serial_clock();
  93. serial1.clock = get_serial_clock();
  94. }
  95. int board_early_init_f(void)
  96. {
  97. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  98. i2c_early_init_f();
  99. #endif
  100. /* get required clock for UART IP */
  101. uart_get_clock();
  102. #ifdef CONFIG_EMC2305
  103. select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
  104. emc2305_init(I2C_EMC2305_ADDR);
  105. set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
  106. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  107. #endif
  108. fsl_lsch3_early_init_f();
  109. return 0;
  110. }
  111. #ifdef CONFIG_OF_BOARD_FIXUP
  112. int board_fix_fdt(void *fdt)
  113. {
  114. char *reg_names, *reg_name;
  115. int names_len, old_name_len, new_name_len, remaining_names_len;
  116. struct str_map {
  117. char *old_str;
  118. char *new_str;
  119. } reg_names_map[] = {
  120. { "ccsr", "dbi" },
  121. { "pf_ctrl", "ctrl" }
  122. };
  123. int off = -1, i = 0;
  124. if (IS_SVR_REV(get_svr(), 1, 0))
  125. return 0;
  126. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
  127. while (off != -FDT_ERR_NOTFOUND) {
  128. fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
  129. strlen("fsl,ls-pcie") + 1);
  130. reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
  131. &names_len);
  132. if (!reg_names)
  133. continue;
  134. reg_name = reg_names;
  135. remaining_names_len = names_len - (reg_name - reg_names);
  136. i = 0;
  137. while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
  138. old_name_len = strlen(reg_names_map[i].old_str);
  139. new_name_len = strlen(reg_names_map[i].new_str);
  140. if (memcmp(reg_name, reg_names_map[i].old_str,
  141. old_name_len) == 0) {
  142. /* first only leave required bytes for new_str
  143. * and copy rest of the string after it
  144. */
  145. memcpy(reg_name + new_name_len,
  146. reg_name + old_name_len,
  147. remaining_names_len - old_name_len);
  148. /* Now copy new_str */
  149. memcpy(reg_name, reg_names_map[i].new_str,
  150. new_name_len);
  151. names_len -= old_name_len;
  152. names_len += new_name_len;
  153. i++;
  154. }
  155. reg_name = memchr(reg_name, '\0', remaining_names_len);
  156. if (!reg_name)
  157. break;
  158. reg_name += 1;
  159. remaining_names_len = names_len -
  160. (reg_name - reg_names);
  161. }
  162. fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
  163. off = fdt_node_offset_by_compatible(fdt, off,
  164. "fsl,lx2160a-pcie");
  165. }
  166. return 0;
  167. }
  168. #endif
  169. #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  170. void esdhc_dspi_status_fixup(void *blob)
  171. {
  172. const char esdhc0_path[] = "/soc/esdhc@2140000";
  173. const char esdhc1_path[] = "/soc/esdhc@2150000";
  174. const char dspi0_path[] = "/soc/spi@2100000";
  175. const char dspi1_path[] = "/soc/spi@2110000";
  176. const char dspi2_path[] = "/soc/spi@2120000";
  177. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  178. u32 sdhc1_base_pmux;
  179. u32 sdhc2_base_pmux;
  180. u32 iic5_pmux;
  181. /* Check RCW field sdhc1_base_pmux to enable/disable
  182. * esdhc0/dspi0 DT node
  183. */
  184. sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  185. & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
  186. sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
  187. if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
  188. do_fixup_by_path(blob, dspi0_path, "status", "okay",
  189. sizeof("okay"), 1);
  190. do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
  191. sizeof("disabled"), 1);
  192. } else {
  193. do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  194. sizeof("okay"), 1);
  195. do_fixup_by_path(blob, dspi0_path, "status", "disabled",
  196. sizeof("disabled"), 1);
  197. }
  198. /* Check RCW field sdhc2_base_pmux to enable/disable
  199. * esdhc1/dspi1 DT node
  200. */
  201. sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
  202. & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
  203. sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
  204. if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
  205. do_fixup_by_path(blob, dspi1_path, "status", "okay",
  206. sizeof("okay"), 1);
  207. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  208. sizeof("disabled"), 1);
  209. } else {
  210. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  211. sizeof("okay"), 1);
  212. do_fixup_by_path(blob, dspi1_path, "status", "disabled",
  213. sizeof("disabled"), 1);
  214. }
  215. /* Check RCW field IIC5 to enable dspi2 DT node */
  216. iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  217. & FSL_CHASSIS3_IIC5_PMUX_MASK;
  218. iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
  219. if (iic5_pmux == IIC5_PMUX_SPI3)
  220. do_fixup_by_path(blob, dspi2_path, "status", "okay",
  221. sizeof("okay"), 1);
  222. else
  223. do_fixup_by_path(blob, dspi2_path, "status", "disabled",
  224. sizeof("disabled"), 1);
  225. }
  226. #endif
  227. int esdhc_status_fixup(void *blob, const char *compat)
  228. {
  229. #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  230. /* Enable esdhc and dspi DT nodes based on RCW fields */
  231. esdhc_dspi_status_fixup(blob);
  232. #else
  233. /* Enable both esdhc DT nodes for LX2160ARDB */
  234. do_fixup_by_compat(blob, compat, "status", "okay",
  235. sizeof("okay"), 1);
  236. #endif
  237. return 0;
  238. }
  239. #if defined(CONFIG_VID)
  240. int i2c_multiplexer_select_vid_channel(u8 channel)
  241. {
  242. return select_i2c_ch_pca9547(channel);
  243. }
  244. int init_func_vid(void)
  245. {
  246. int set_vid;
  247. if (IS_SVR_REV(get_svr(), 1, 0))
  248. set_vid = adjust_vdd(800);
  249. else
  250. set_vid = adjust_vdd(0);
  251. if (set_vid < 0)
  252. printf("core voltage not adjusted\n");
  253. return 0;
  254. }
  255. #endif
  256. int checkboard(void)
  257. {
  258. enum boot_src src = get_boot_src();
  259. char buf[64];
  260. u8 sw;
  261. #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  262. int clock;
  263. static const char *const freq[] = {"100", "125", "156.25",
  264. "161.13", "322.26", "", "", "",
  265. "", "", "", "", "", "", "",
  266. "100 separate SSCG"};
  267. #endif
  268. cpu_name(buf);
  269. #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  270. printf("Board: %s-QDS, ", buf);
  271. #else
  272. printf("Board: %s-RDB, ", buf);
  273. #endif
  274. sw = QIXIS_READ(arch);
  275. printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
  276. if (src == BOOT_SOURCE_SD_MMC) {
  277. puts("SD\n");
  278. } else if (src == BOOT_SOURCE_SD_MMC2) {
  279. puts("eMMC\n");
  280. } else {
  281. sw = QIXIS_READ(brdcfg[0]);
  282. sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
  283. switch (sw) {
  284. case 0:
  285. case 4:
  286. puts("FlexSPI DEV#0\n");
  287. break;
  288. case 1:
  289. puts("FlexSPI DEV#1\n");
  290. break;
  291. case 2:
  292. case 3:
  293. puts("FlexSPI EMU\n");
  294. break;
  295. default:
  296. printf("invalid setting, xmap: %d\n", sw);
  297. break;
  298. }
  299. }
  300. #if defined(CONFIG_TARGET_LX2160ARDB)
  301. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  302. puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
  303. puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
  304. puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
  305. #else
  306. printf("FPGA: v%d (%s), build %d",
  307. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  308. (int)qixis_read_minor());
  309. /* the timestamp string contains "\n" at the end */
  310. printf(" on %s", qixis_read_time(buf));
  311. puts("SERDES1 Reference : ");
  312. sw = QIXIS_READ(brdcfg[2]);
  313. clock = sw >> 4;
  314. printf("Clock1 = %sMHz ", freq[clock]);
  315. #if defined(CONFIG_TARGET_LX2160AQDS)
  316. clock = sw & 0x0f;
  317. printf("Clock2 = %sMHz", freq[clock]);
  318. #endif
  319. sw = QIXIS_READ(brdcfg[3]);
  320. puts("\nSERDES2 Reference : ");
  321. clock = sw >> 4;
  322. printf("Clock1 = %sMHz ", freq[clock]);
  323. clock = sw & 0x0f;
  324. printf("Clock2 = %sMHz\n", freq[clock]);
  325. #if defined(CONFIG_TARGET_LX2160AQDS)
  326. sw = QIXIS_READ(brdcfg[12]);
  327. puts("SERDES3 Reference : ");
  328. clock = sw >> 4;
  329. printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
  330. #endif
  331. #endif
  332. return 0;
  333. }
  334. #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  335. /*
  336. * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
  337. */
  338. u8 qixis_esdhc_detect_quirk(void)
  339. {
  340. /*
  341. * SDHC1 Card ID:
  342. * Specifies the type of card installed in the SDHC1 adapter slot.
  343. * 000= (reserved)
  344. * 001= eMMC V4.5 adapter is installed.
  345. * 010= SD/MMC 3.3V adapter is installed.
  346. * 011= eMMC V4.4 adapter is installed.
  347. * 100= eMMC V5.0 adapter is installed.
  348. * 101= MMC card/Legacy (3.3V) adapter is installed.
  349. * 110= SDCard V2/V3 adapter installed.
  350. * 111= no adapter is installed.
  351. */
  352. return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
  353. QIXIS_ESDHC_NO_ADAPTER);
  354. }
  355. static void esdhc_adapter_card_ident(void)
  356. {
  357. u8 card_id, val;
  358. val = QIXIS_READ(sdhc1);
  359. card_id = val & QIXIS_SDID_MASK;
  360. switch (card_id) {
  361. case QIXIS_ESDHC_ADAPTER_TYPE_SD:
  362. /* Power cycle to card */
  363. val &= ~QIXIS_SDHC1_S1V3;
  364. QIXIS_WRITE(sdhc1, val);
  365. mdelay(1);
  366. val |= QIXIS_SDHC1_S1V3;
  367. QIXIS_WRITE(sdhc1, val);
  368. /* Route to SDHC1_VS */
  369. val = QIXIS_READ(brdcfg[11]);
  370. val |= QIXIS_SDHC1_VS;
  371. QIXIS_WRITE(brdcfg[11], val);
  372. break;
  373. default:
  374. break;
  375. }
  376. }
  377. int config_board_mux(void)
  378. {
  379. u8 reg11, reg5, reg13;
  380. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  381. u32 sdhc1_base_pmux;
  382. u32 sdhc2_base_pmux;
  383. u32 iic5_pmux;
  384. /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
  385. * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
  386. * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
  387. * Qixis and remote systems are isolated from the I2C1 bus.
  388. * Processor connections are still available.
  389. * SPI2 CS2_B controls EN25S64 SPI memory device.
  390. * SPI3 CS2_B controls EN25S64 SPI memory device.
  391. * EC2 connects to PHY #2 using RGMII protocol.
  392. * CLK_OUT connects to FPGA for clock measurement.
  393. */
  394. reg5 = QIXIS_READ(brdcfg[5]);
  395. reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
  396. QIXIS_WRITE(brdcfg[5], reg5);
  397. /* Check RCW field sdhc1_base_pmux
  398. * esdhc0 : sdhc1_base_pmux = 0
  399. * dspi0 : sdhc1_base_pmux = 2
  400. */
  401. sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  402. & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
  403. sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
  404. if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
  405. reg11 = QIXIS_READ(brdcfg[11]);
  406. reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
  407. QIXIS_WRITE(brdcfg[11], reg11);
  408. } else {
  409. /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
  410. * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
  411. * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
  412. */
  413. reg11 = QIXIS_READ(brdcfg[11]);
  414. reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
  415. QIXIS_WRITE(brdcfg[11], reg11);
  416. }
  417. /* Check RCW field sdhc2_base_pmux
  418. * esdhc1 : sdhc2_base_pmux = 0 (default)
  419. * dspi1 : sdhc2_base_pmux = 2
  420. */
  421. sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
  422. & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
  423. sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
  424. if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
  425. reg13 = QIXIS_READ(brdcfg[13]);
  426. reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
  427. QIXIS_WRITE(brdcfg[13], reg13);
  428. } else {
  429. reg13 = QIXIS_READ(brdcfg[13]);
  430. reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
  431. QIXIS_WRITE(brdcfg[13], reg13);
  432. }
  433. /* Check RCW field IIC5 to enable dspi2 DT nodei
  434. * dspi2: IIC5 = 3
  435. */
  436. iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  437. & FSL_CHASSIS3_IIC5_PMUX_MASK;
  438. iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
  439. if (iic5_pmux == IIC5_PMUX_SPI3) {
  440. /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
  441. reg11 = QIXIS_READ(brdcfg[11]);
  442. reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
  443. QIXIS_WRITE(brdcfg[11], reg11);
  444. /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
  445. * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
  446. * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
  447. */
  448. reg11 = QIXIS_READ(brdcfg[11]);
  449. reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
  450. QIXIS_WRITE(brdcfg[11], reg11);
  451. } else {
  452. /*
  453. * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
  454. * do not change it.
  455. * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
  456. */
  457. reg11 = QIXIS_READ(brdcfg[11]);
  458. if ((reg11 & 0x30) != 0x30) {
  459. reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
  460. QIXIS_WRITE(brdcfg[11], reg11);
  461. }
  462. /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
  463. * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
  464. * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
  465. */
  466. reg11 = QIXIS_READ(brdcfg[11]);
  467. reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
  468. QIXIS_WRITE(brdcfg[11], reg11);
  469. }
  470. return 0;
  471. }
  472. int board_early_init_r(void)
  473. {
  474. esdhc_adapter_card_ident();
  475. return 0;
  476. }
  477. #elif defined(CONFIG_TARGET_LX2160ARDB)
  478. int config_board_mux(void)
  479. {
  480. u8 brdcfg;
  481. brdcfg = QIXIS_READ(brdcfg[4]);
  482. /* The BRDCFG4 register controls general board configuration.
  483. *|-------------------------------------------|
  484. *|Field | Function |
  485. *|-------------------------------------------|
  486. *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
  487. *|CAN_EN | 0= CAN transceivers are disabled. |
  488. *| | 1= CAN transceivers are enabled. |
  489. *|-------------------------------------------|
  490. */
  491. brdcfg |= BIT_MASK(5);
  492. QIXIS_WRITE(brdcfg[4], brdcfg);
  493. return 0;
  494. }
  495. #else
  496. int config_board_mux(void)
  497. {
  498. return 0;
  499. }
  500. #endif
  501. unsigned long get_board_sys_clk(void)
  502. {
  503. #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  504. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  505. switch (sysclk_conf & 0x03) {
  506. case QIXIS_SYSCLK_100:
  507. return 100000000;
  508. case QIXIS_SYSCLK_125:
  509. return 125000000;
  510. case QIXIS_SYSCLK_133:
  511. return 133333333;
  512. }
  513. return 100000000;
  514. #else
  515. return 100000000;
  516. #endif
  517. }
  518. unsigned long get_board_ddr_clk(void)
  519. {
  520. #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  521. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  522. switch ((ddrclk_conf & 0x30) >> 4) {
  523. case QIXIS_DDRCLK_100:
  524. return 100000000;
  525. case QIXIS_DDRCLK_125:
  526. return 125000000;
  527. case QIXIS_DDRCLK_133:
  528. return 133333333;
  529. }
  530. return 100000000;
  531. #else
  532. return 100000000;
  533. #endif
  534. }
  535. int board_init(void)
  536. {
  537. #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
  538. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  539. #endif
  540. #ifdef CONFIG_ENV_IS_NOWHERE
  541. gd->env_addr = (ulong)&default_environment[0];
  542. #endif
  543. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  544. #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
  545. /* invert AQR107 IRQ pins polarity */
  546. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
  547. #endif
  548. #ifdef CONFIG_FSL_CAAM
  549. sec_init();
  550. #endif
  551. #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
  552. pci_init();
  553. #endif
  554. return 0;
  555. }
  556. void detail_board_ddr_info(void)
  557. {
  558. int i;
  559. u64 ddr_size = 0;
  560. puts("\nDDR ");
  561. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  562. ddr_size += gd->bd->bi_dram[i].size;
  563. print_size(ddr_size, "");
  564. print_ddr_info(0);
  565. }
  566. #ifdef CONFIG_MISC_INIT_R
  567. int misc_init_r(void)
  568. {
  569. config_board_mux();
  570. return 0;
  571. }
  572. #endif
  573. #ifdef CONFIG_FSL_MC_ENET
  574. extern int fdt_fixup_board_phy(void *fdt);
  575. void fdt_fixup_board_enet(void *fdt)
  576. {
  577. int offset;
  578. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  579. if (offset < 0)
  580. offset = fdt_path_offset(fdt, "/fsl-mc");
  581. if (offset < 0) {
  582. printf("%s: fsl-mc node not found in device tree (error %d)\n",
  583. __func__, offset);
  584. return;
  585. }
  586. if (get_mc_boot_status() == 0 &&
  587. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
  588. fdt_status_okay(fdt, offset);
  589. #ifndef CONFIG_DM_ETH
  590. fdt_fixup_board_phy(fdt);
  591. #endif
  592. } else {
  593. fdt_status_fail(fdt, offset);
  594. }
  595. }
  596. void board_quiesce_devices(void)
  597. {
  598. fsl_mc_ldpaa_exit(gd->bd);
  599. }
  600. #endif
  601. #ifdef CONFIG_OF_BOARD_SETUP
  602. int ft_board_setup(void *blob, struct bd_info *bd)
  603. {
  604. int i;
  605. u16 mc_memory_bank = 0;
  606. u64 *base;
  607. u64 *size;
  608. u64 mc_memory_base = 0;
  609. u64 mc_memory_size = 0;
  610. u16 total_memory_banks;
  611. ft_cpu_setup(blob, bd);
  612. fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
  613. if (mc_memory_base != 0)
  614. mc_memory_bank++;
  615. total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
  616. base = calloc(total_memory_banks, sizeof(u64));
  617. size = calloc(total_memory_banks, sizeof(u64));
  618. /* fixup DT for the three GPP DDR banks */
  619. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  620. base[i] = gd->bd->bi_dram[i].start;
  621. size[i] = gd->bd->bi_dram[i].size;
  622. }
  623. #ifdef CONFIG_RESV_RAM
  624. /* reduce size if reserved memory is within this bank */
  625. if (gd->arch.resv_ram >= base[0] &&
  626. gd->arch.resv_ram < base[0] + size[0])
  627. size[0] = gd->arch.resv_ram - base[0];
  628. else if (gd->arch.resv_ram >= base[1] &&
  629. gd->arch.resv_ram < base[1] + size[1])
  630. size[1] = gd->arch.resv_ram - base[1];
  631. else if (gd->arch.resv_ram >= base[2] &&
  632. gd->arch.resv_ram < base[2] + size[2])
  633. size[2] = gd->arch.resv_ram - base[2];
  634. #endif
  635. if (mc_memory_base != 0) {
  636. for (i = 0; i <= total_memory_banks; i++) {
  637. if (base[i] == 0 && size[i] == 0) {
  638. base[i] = mc_memory_base;
  639. size[i] = mc_memory_size;
  640. break;
  641. }
  642. }
  643. }
  644. fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
  645. #ifdef CONFIG_USB
  646. fsl_fdt_fixup_dr_usb(blob, bd);
  647. #endif
  648. #ifdef CONFIG_FSL_MC_ENET
  649. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  650. fdt_fixup_board_enet(blob);
  651. #endif
  652. fdt_fixup_icid(blob);
  653. return 0;
  654. }
  655. #endif
  656. void qixis_dump_switch(void)
  657. {
  658. int i, nr_of_cfgsw;
  659. QIXIS_WRITE(cms[0], 0x00);
  660. nr_of_cfgsw = QIXIS_READ(cms[1]);
  661. puts("DIP switch settings dump:\n");
  662. for (i = 1; i <= nr_of_cfgsw; i++) {
  663. QIXIS_WRITE(cms[0], i);
  664. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  665. }
  666. }