ls2080ardb.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. * Copyright 2017 NXP
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <errno.h>
  11. #include <netdev.h>
  12. #include <fsl_ifc.h>
  13. #include <fsl_ddr.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <hwconfig.h>
  17. #include <fdt_support.h>
  18. #include <linux/libfdt.h>
  19. #include <fsl-mc/fsl_mc.h>
  20. #include <env_internal.h>
  21. #include <efi_loader.h>
  22. #include <i2c.h>
  23. #include <asm/arch/mmu.h>
  24. #include <asm/arch/soc.h>
  25. #include <asm/arch/ppa.h>
  26. #include <fsl_sec.h>
  27. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  28. #ifdef CONFIG_FSL_QIXIS
  29. #include "../common/qixis.h"
  30. #include "ls2080ardb_qixis.h"
  31. #endif
  32. #include "../common/vid.h"
  33. #define PIN_MUX_SEL_SDHC 0x00
  34. #define PIN_MUX_SEL_DSPI 0x0a
  35. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  36. DECLARE_GLOBAL_DATA_PTR;
  37. enum {
  38. MUX_TYPE_SDHC,
  39. MUX_TYPE_DSPI,
  40. };
  41. unsigned long long get_qixis_addr(void)
  42. {
  43. unsigned long long addr;
  44. if (gd->flags & GD_FLG_RELOC)
  45. addr = QIXIS_BASE_PHYS;
  46. else
  47. addr = QIXIS_BASE_PHYS_EARLY;
  48. /*
  49. * IFC address under 256MB is mapped to 0x30000000, any address above
  50. * is mapped to 0x5_10000000 up to 4GB.
  51. */
  52. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  53. return addr;
  54. }
  55. int checkboard(void)
  56. {
  57. #ifdef CONFIG_FSL_QIXIS
  58. u8 sw;
  59. #endif
  60. char buf[15];
  61. cpu_name(buf);
  62. printf("Board: %s-RDB, ", buf);
  63. #ifdef CONFIG_TARGET_LS2081ARDB
  64. #ifdef CONFIG_FSL_QIXIS
  65. sw = QIXIS_READ(arch);
  66. printf("Board version: %c, ", (sw & 0xf) + 'A');
  67. sw = QIXIS_READ(brdcfg[0]);
  68. sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
  69. switch (sw) {
  70. case 0:
  71. puts("boot from QSPI DEV#0\n");
  72. puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  73. break;
  74. case 1:
  75. puts("boot from QSPI DEV#1\n");
  76. puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  77. break;
  78. case 2:
  79. puts("boot from QSPI EMU\n");
  80. puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  81. break;
  82. case 3:
  83. puts("boot from QSPI EMU\n");
  84. puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  85. break;
  86. case 4:
  87. puts("boot from QSPI DEV#0\n");
  88. puts("QSPI_CSA_1 mapped to QSPI EMU\n");
  89. break;
  90. default:
  91. printf("invalid setting of SW%u\n", sw);
  92. break;
  93. }
  94. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  95. #endif
  96. puts("SERDES1 Reference : ");
  97. printf("Clock1 = 100MHz ");
  98. printf("Clock2 = 161.13MHz");
  99. #else
  100. #ifdef CONFIG_FSL_QIXIS
  101. sw = QIXIS_READ(arch);
  102. printf("Board Arch: V%d, ", sw >> 4);
  103. printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  104. sw = QIXIS_READ(brdcfg[0]);
  105. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  106. if (sw < 0x8)
  107. printf("vBank: %d\n", sw);
  108. else if (sw == 0x9)
  109. puts("NAND\n");
  110. else
  111. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  112. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  113. #endif
  114. puts("SERDES1 Reference : ");
  115. printf("Clock1 = 156.25MHz ");
  116. printf("Clock2 = 156.25MHz");
  117. #endif
  118. puts("\nSERDES2 Reference : ");
  119. printf("Clock1 = 100MHz ");
  120. printf("Clock2 = 100MHz\n");
  121. return 0;
  122. }
  123. unsigned long get_board_sys_clk(void)
  124. {
  125. #ifdef CONFIG_FSL_QIXIS
  126. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  127. switch (sysclk_conf & 0x0F) {
  128. case QIXIS_SYSCLK_83:
  129. return 83333333;
  130. case QIXIS_SYSCLK_100:
  131. return 100000000;
  132. case QIXIS_SYSCLK_125:
  133. return 125000000;
  134. case QIXIS_SYSCLK_133:
  135. return 133333333;
  136. case QIXIS_SYSCLK_150:
  137. return 150000000;
  138. case QIXIS_SYSCLK_160:
  139. return 160000000;
  140. case QIXIS_SYSCLK_166:
  141. return 166666666;
  142. }
  143. #endif
  144. return 100000000;
  145. }
  146. int select_i2c_ch_pca9547(u8 ch)
  147. {
  148. int ret;
  149. #if !CONFIG_IS_ENABLED(DM_I2C)
  150. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  151. #else
  152. struct udevice *dev;
  153. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  154. if (!ret)
  155. ret = dm_i2c_write(dev, 0, &ch, 1);
  156. #endif
  157. if (ret) {
  158. puts("PCA: failed to select proper channel\n");
  159. return ret;
  160. }
  161. return 0;
  162. }
  163. int i2c_multiplexer_select_vid_channel(u8 channel)
  164. {
  165. return select_i2c_ch_pca9547(channel);
  166. }
  167. int config_board_mux(int ctrl_type)
  168. {
  169. #ifdef CONFIG_FSL_QIXIS
  170. u8 reg5;
  171. reg5 = QIXIS_READ(brdcfg[5]);
  172. switch (ctrl_type) {
  173. case MUX_TYPE_SDHC:
  174. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
  175. break;
  176. case MUX_TYPE_DSPI:
  177. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
  178. break;
  179. default:
  180. printf("Wrong mux interface type\n");
  181. return -1;
  182. }
  183. QIXIS_WRITE(brdcfg[5], reg5);
  184. #endif
  185. return 0;
  186. }
  187. int board_init(void)
  188. {
  189. #ifdef CONFIG_FSL_MC_ENET
  190. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  191. #endif
  192. init_final_memctl_regs();
  193. #ifdef CONFIG_ENV_IS_NOWHERE
  194. gd->env_addr = (ulong)&default_environment[0];
  195. #endif
  196. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  197. #ifdef CONFIG_FSL_QIXIS
  198. QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
  199. #endif
  200. #ifdef CONFIG_FSL_CAAM
  201. sec_init();
  202. #endif
  203. #ifdef CONFIG_FSL_LS_PPA
  204. ppa_init();
  205. #endif
  206. #ifdef CONFIG_FSL_MC_ENET
  207. /* invert AQR405 IRQ pins polarity */
  208. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
  209. #endif
  210. #ifdef CONFIG_FSL_CAAM
  211. sec_init();
  212. #endif
  213. #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
  214. pci_init();
  215. #endif
  216. return 0;
  217. }
  218. int board_early_init_f(void)
  219. {
  220. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  221. i2c_early_init_f();
  222. #endif
  223. fsl_lsch3_early_init_f();
  224. return 0;
  225. }
  226. int misc_init_r(void)
  227. {
  228. char *env_hwconfig;
  229. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  230. u32 val;
  231. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  232. u32 svr = gur_in32(&gur->svr);
  233. val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
  234. env_hwconfig = env_get("hwconfig");
  235. if (hwconfig_f("dspi", env_hwconfig) &&
  236. DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
  237. config_board_mux(MUX_TYPE_DSPI);
  238. else
  239. config_board_mux(MUX_TYPE_SDHC);
  240. /*
  241. * LS2081ARDB RevF board has smart voltage translator
  242. * which needs to be programmed to enable high speed SD interface
  243. * by setting GPIO4_10 output to zero
  244. */
  245. #ifdef CONFIG_TARGET_LS2081ARDB
  246. out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
  247. in_le32(GPIO4_GPDIR_ADDR)));
  248. out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
  249. in_le32(GPIO4_GPDAT_ADDR)));
  250. #endif
  251. if (hwconfig("sdhc"))
  252. config_board_mux(MUX_TYPE_SDHC);
  253. if (adjust_vdd(0))
  254. printf("Warning: Adjusting core voltage failed.\n");
  255. /*
  256. * Default value of board env is based on filename which is
  257. * ls2080ardb. Modify board env for other supported SoCs
  258. */
  259. if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
  260. (SVR_SOC_VER(svr) == SVR_LS2048A))
  261. env_set("board", "ls2088ardb");
  262. else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
  263. (SVR_SOC_VER(svr) == SVR_LS2041A))
  264. env_set("board", "ls2081ardb");
  265. return 0;
  266. }
  267. void detail_board_ddr_info(void)
  268. {
  269. puts("\nDDR ");
  270. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  271. print_ddr_info(0);
  272. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  273. if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
  274. puts("\nDP-DDR ");
  275. print_size(gd->bd->bi_dram[2].size, "");
  276. print_ddr_info(CONFIG_DP_DDR_CTRL);
  277. }
  278. #endif
  279. }
  280. #ifdef CONFIG_FSL_MC_ENET
  281. void fdt_fixup_board_enet(void *fdt)
  282. {
  283. int offset;
  284. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  285. if (offset < 0)
  286. offset = fdt_path_offset(fdt, "/fsl-mc");
  287. if (offset < 0) {
  288. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  289. __func__, offset);
  290. return;
  291. }
  292. if (get_mc_boot_status() == 0 &&
  293. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  294. fdt_status_okay(fdt, offset);
  295. else
  296. fdt_status_fail(fdt, offset);
  297. }
  298. void board_quiesce_devices(void)
  299. {
  300. fsl_mc_ldpaa_exit(gd->bd);
  301. }
  302. #endif
  303. #ifdef CONFIG_OF_BOARD_SETUP
  304. void fsl_fdt_fixup_flash(void *fdt)
  305. {
  306. int offset;
  307. #ifdef CONFIG_TFABOOT
  308. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  309. u32 val;
  310. #endif
  311. /*
  312. * IFC and QSPI are muxed on board.
  313. * So disable IFC node in dts if QSPI is enabled or
  314. * disable QSPI node in dts in case QSPI is not enabled.
  315. */
  316. #ifdef CONFIG_TFABOOT
  317. enum boot_src src = get_boot_src();
  318. bool disable_ifc = false;
  319. switch (src) {
  320. case BOOT_SOURCE_IFC_NOR:
  321. disable_ifc = false;
  322. break;
  323. case BOOT_SOURCE_QSPI_NOR:
  324. disable_ifc = true;
  325. break;
  326. default:
  327. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  328. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  329. disable_ifc = true;
  330. break;
  331. }
  332. if (disable_ifc) {
  333. offset = fdt_path_offset(fdt, "/soc/ifc");
  334. if (offset < 0)
  335. offset = fdt_path_offset(fdt, "/ifc");
  336. } else {
  337. offset = fdt_path_offset(fdt, "/soc/quadspi");
  338. if (offset < 0)
  339. offset = fdt_path_offset(fdt, "/quadspi");
  340. }
  341. #else
  342. #ifdef CONFIG_FSL_QSPI
  343. offset = fdt_path_offset(fdt, "/soc/ifc");
  344. if (offset < 0)
  345. offset = fdt_path_offset(fdt, "/ifc");
  346. #else
  347. offset = fdt_path_offset(fdt, "/soc/quadspi");
  348. if (offset < 0)
  349. offset = fdt_path_offset(fdt, "/quadspi");
  350. #endif
  351. #endif
  352. if (offset < 0)
  353. return;
  354. fdt_status_disabled(fdt, offset);
  355. }
  356. int ft_board_setup(void *blob, struct bd_info *bd)
  357. {
  358. int i;
  359. u16 mc_memory_bank = 0;
  360. u64 *base;
  361. u64 *size;
  362. u64 mc_memory_base = 0;
  363. u64 mc_memory_size = 0;
  364. u16 total_memory_banks;
  365. ft_cpu_setup(blob, bd);
  366. fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
  367. if (mc_memory_base != 0)
  368. mc_memory_bank++;
  369. total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
  370. base = calloc(total_memory_banks, sizeof(u64));
  371. size = calloc(total_memory_banks, sizeof(u64));
  372. /* fixup DT for the two GPP DDR banks */
  373. base[0] = gd->bd->bi_dram[0].start;
  374. size[0] = gd->bd->bi_dram[0].size;
  375. base[1] = gd->bd->bi_dram[1].start;
  376. size[1] = gd->bd->bi_dram[1].size;
  377. #ifdef CONFIG_RESV_RAM
  378. /* reduce size if reserved memory is within this bank */
  379. if (gd->arch.resv_ram >= base[0] &&
  380. gd->arch.resv_ram < base[0] + size[0])
  381. size[0] = gd->arch.resv_ram - base[0];
  382. else if (gd->arch.resv_ram >= base[1] &&
  383. gd->arch.resv_ram < base[1] + size[1])
  384. size[1] = gd->arch.resv_ram - base[1];
  385. #endif
  386. if (mc_memory_base != 0) {
  387. for (i = 0; i <= total_memory_banks; i++) {
  388. if (base[i] == 0 && size[i] == 0) {
  389. base[i] = mc_memory_base;
  390. size[i] = mc_memory_size;
  391. break;
  392. }
  393. }
  394. }
  395. fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
  396. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  397. fsl_fdt_fixup_dr_usb(blob, bd);
  398. fsl_fdt_fixup_flash(blob);
  399. #ifdef CONFIG_FSL_MC_ENET
  400. fdt_fixup_board_enet(blob);
  401. #endif
  402. fdt_fixup_icid(blob);
  403. return 0;
  404. }
  405. #endif
  406. void qixis_dump_switch(void)
  407. {
  408. #ifdef CONFIG_FSL_QIXIS
  409. int i, nr_of_cfgsw;
  410. QIXIS_WRITE(cms[0], 0x00);
  411. nr_of_cfgsw = QIXIS_READ(cms[1]);
  412. puts("DIP switch settings dump:\n");
  413. for (i = 1; i <= nr_of_cfgsw; i++) {
  414. QIXIS_WRITE(cms[0], i);
  415. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  416. }
  417. #endif
  418. }
  419. /*
  420. * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
  421. * Both slots has 0x54, resulting 2nd slot unusable.
  422. */
  423. void update_spd_address(unsigned int ctrl_num,
  424. unsigned int slot,
  425. unsigned int *addr)
  426. {
  427. #ifndef CONFIG_TARGET_LS2081ARDB
  428. #ifdef CONFIG_FSL_QIXIS
  429. u8 sw;
  430. sw = QIXIS_READ(arch);
  431. if ((sw & 0xf) < 0x3) {
  432. if (ctrl_num == 1 && slot == 0)
  433. *addr = SPD_EEPROM_ADDRESS4;
  434. else if (ctrl_num == 1 && slot == 1)
  435. *addr = SPD_EEPROM_ADDRESS3;
  436. }
  437. #endif
  438. #endif
  439. }