eth.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <log.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/fsl_serdes.h>
  12. #include <hwconfig.h>
  13. #include <fsl_mdio.h>
  14. #include <malloc.h>
  15. #include <fm_eth.h>
  16. #include <i2c.h>
  17. #include <miiphy.h>
  18. #include <fsl-mc/fsl_mc.h>
  19. #include <fsl-mc/ldpaa_wriop.h>
  20. #include <linux/delay.h>
  21. #include "../common/qixis.h"
  22. #include "ls2080aqds_qixis.h"
  23. #define MC_BOOT_ENV_VAR "mcinitcmd"
  24. #ifndef CONFIG_DM_ETH
  25. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  26. /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  27. * Bank 1 -> Lanes A, B, C, D, E, F, G, H
  28. * Bank 2 -> Lanes A,B, C, D, E, F, G, H
  29. */
  30. /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
  31. * means that the mapping must be determined dynamically, or that the lane
  32. * maps to something other than a board slot.
  33. */
  34. static u8 lane_to_slot_fsm1[] = {
  35. 0, 0, 0, 0, 0, 0, 0, 0
  36. };
  37. static u8 lane_to_slot_fsm2[] = {
  38. 0, 0, 0, 0, 0, 0, 0, 0
  39. };
  40. /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  41. * housed.
  42. */
  43. static int xqsgii_riser_phy_addr[] = {
  44. XQSGMII_CARD_PHY1_PORT0_ADDR,
  45. XQSGMII_CARD_PHY2_PORT0_ADDR,
  46. XQSGMII_CARD_PHY3_PORT0_ADDR,
  47. XQSGMII_CARD_PHY4_PORT0_ADDR,
  48. XQSGMII_CARD_PHY3_PORT2_ADDR,
  49. XQSGMII_CARD_PHY1_PORT2_ADDR,
  50. XQSGMII_CARD_PHY4_PORT2_ADDR,
  51. XQSGMII_CARD_PHY2_PORT2_ADDR,
  52. };
  53. static int sgmii_riser_phy_addr[] = {
  54. SGMII_CARD_PORT1_PHY_ADDR,
  55. SGMII_CARD_PORT2_PHY_ADDR,
  56. SGMII_CARD_PORT3_PHY_ADDR,
  57. SGMII_CARD_PORT4_PHY_ADDR,
  58. };
  59. /* Slot2 does not have EMI connections */
  60. #define EMI_NONE 0xFF
  61. #define EMI1_SLOT1 0
  62. #define EMI1_SLOT2 1
  63. #define EMI1_SLOT3 2
  64. #define EMI1_SLOT4 3
  65. #define EMI1_SLOT5 4
  66. #define EMI1_SLOT6 5
  67. #define EMI2 6
  68. #define SFP_TX 0
  69. static const char * const mdio_names[] = {
  70. "LS2080A_QDS_MDIO0",
  71. "LS2080A_QDS_MDIO1",
  72. "LS2080A_QDS_MDIO2",
  73. "LS2080A_QDS_MDIO3",
  74. "LS2080A_QDS_MDIO4",
  75. "LS2080A_QDS_MDIO5",
  76. DEFAULT_WRIOP_MDIO2_NAME,
  77. };
  78. struct ls2080a_qds_mdio {
  79. u8 muxval;
  80. struct mii_dev *realbus;
  81. };
  82. struct reg_pair {
  83. uint addr;
  84. u8 *val;
  85. };
  86. static void sgmii_configure_repeater(int serdes_port)
  87. {
  88. struct mii_dev *bus;
  89. uint8_t a = 0xf;
  90. int i, j, k, ret;
  91. int dpmac_id = 0, dpmac, mii_bus = 0;
  92. unsigned short value;
  93. char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
  94. uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
  95. uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  96. uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  97. uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  98. uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  99. u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
  100. struct reg_pair reg_pair[10] = {
  101. {6, &reg_val[0]}, {4, &reg_val[1]},
  102. {8, &reg_val[2]}, {0xf, NULL},
  103. {0x11, NULL}, {0x16, NULL},
  104. {0x18, NULL}, {0x23, &reg_val[3]},
  105. {0x2d, &reg_val[4]}, {4, &reg_val[5]},
  106. };
  107. int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
  108. #if CONFIG_IS_ENABLED(DM_I2C)
  109. struct udevice *udev;
  110. #endif
  111. /* Set I2c to Slot 1 */
  112. #if !CONFIG_IS_ENABLED(DM_I2C)
  113. ret = i2c_write(0x77, 0, 0, &a, 1);
  114. #else
  115. ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
  116. if (!ret)
  117. ret = dm_i2c_write(udev, 0, &a, 1);
  118. #endif
  119. if (ret)
  120. goto error;
  121. for (dpmac = 0; dpmac < 8; dpmac++) {
  122. /* Check the PHY status */
  123. switch (serdes_port) {
  124. case 1:
  125. mii_bus = 0;
  126. dpmac_id = dpmac + 1;
  127. break;
  128. case 2:
  129. mii_bus = 1;
  130. dpmac_id = dpmac + 9;
  131. a = 0xb;
  132. #if !CONFIG_IS_ENABLED(DM_I2C)
  133. ret = i2c_write(0x76, 0, 0, &a, 1);
  134. #else
  135. ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
  136. if (!ret)
  137. ret = dm_i2c_write(udev, 0, &a, 1);
  138. #endif
  139. if (ret)
  140. goto error;
  141. break;
  142. }
  143. ret = miiphy_set_current_dev(dev[mii_bus]);
  144. if (ret > 0)
  145. goto error;
  146. bus = mdio_get_current_dev();
  147. debug("Reading from bus %s\n", bus->name);
  148. ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
  149. 3);
  150. if (ret > 0)
  151. goto error;
  152. mdelay(10);
  153. ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
  154. &value);
  155. if (ret > 0)
  156. goto error;
  157. mdelay(10);
  158. if ((value & 0xfff) == 0x401) {
  159. printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
  160. miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
  161. 0x1f, 0);
  162. continue;
  163. }
  164. for (i = 0; i < 4; i++) {
  165. for (j = 0; j < 4; j++) {
  166. reg_pair[3].val = &ch_a_eq[i];
  167. reg_pair[4].val = &ch_a_ctl2[j];
  168. reg_pair[5].val = &ch_b_eq[i];
  169. reg_pair[6].val = &ch_b_ctl2[j];
  170. for (k = 0; k < 10; k++) {
  171. #if !CONFIG_IS_ENABLED(DM_I2C)
  172. ret = i2c_write(i2c_addr[dpmac],
  173. reg_pair[k].addr,
  174. 1, reg_pair[k].val, 1);
  175. #else
  176. ret = i2c_get_chip_for_busnum(0,
  177. i2c_addr[dpmac],
  178. 1, &udev);
  179. if (!ret)
  180. ret = dm_i2c_write(udev,
  181. reg_pair[k].addr,
  182. reg_pair[k].val, 1);
  183. #endif
  184. if (ret)
  185. goto error;
  186. }
  187. mdelay(100);
  188. ret = miiphy_read(dev[mii_bus],
  189. riser_phy_addr[dpmac],
  190. 0x11, &value);
  191. if (ret > 0)
  192. goto error;
  193. mdelay(100);
  194. ret = miiphy_read(dev[mii_bus],
  195. riser_phy_addr[dpmac],
  196. 0x11, &value);
  197. if (ret > 0)
  198. goto error;
  199. if ((value & 0xfff) == 0x401) {
  200. printf("DPMAC %d :PHY is configured ",
  201. dpmac_id);
  202. printf("after setting repeater 0x%x\n",
  203. value);
  204. i = 5;
  205. j = 5;
  206. } else {
  207. printf("DPMAC %d :PHY is failed to ",
  208. dpmac_id);
  209. printf("configure the repeater 0x%x\n",
  210. value);
  211. }
  212. }
  213. }
  214. miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
  215. }
  216. error:
  217. if (ret)
  218. printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
  219. return;
  220. }
  221. static void qsgmii_configure_repeater(int dpmac)
  222. {
  223. uint8_t a = 0xf;
  224. int i, j, k;
  225. int i2c_phy_addr = 0;
  226. int phy_addr = 0;
  227. int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
  228. uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  229. uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  230. uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  231. uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  232. u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
  233. struct reg_pair reg_pair[10] = {
  234. {6, &reg_val[0]}, {4, &reg_val[1]},
  235. {8, &reg_val[2]}, {0xf, NULL},
  236. {0x11, NULL}, {0x16, NULL},
  237. {0x18, NULL}, {0x23, &reg_val[3]},
  238. {0x2d, &reg_val[4]}, {4, &reg_val[5]},
  239. };
  240. const char *dev = "LS2080A_QDS_MDIO0";
  241. int ret = 0;
  242. unsigned short value;
  243. #if CONFIG_IS_ENABLED(DM_I2C)
  244. struct udevice *udev;
  245. #endif
  246. /* Set I2c to Slot 1 */
  247. #if !CONFIG_IS_ENABLED(DM_I2C)
  248. ret = i2c_write(0x77, 0, 0, &a, 1);
  249. #else
  250. ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
  251. if (!ret)
  252. ret = dm_i2c_write(udev, 0, &a, 1);
  253. #endif
  254. if (ret)
  255. goto error;
  256. switch (dpmac) {
  257. case 1:
  258. case 2:
  259. case 3:
  260. case 4:
  261. i2c_phy_addr = i2c_addr[0];
  262. phy_addr = 0;
  263. break;
  264. case 5:
  265. case 6:
  266. case 7:
  267. case 8:
  268. i2c_phy_addr = i2c_addr[1];
  269. phy_addr = 4;
  270. break;
  271. case 9:
  272. case 10:
  273. case 11:
  274. case 12:
  275. i2c_phy_addr = i2c_addr[2];
  276. phy_addr = 8;
  277. break;
  278. case 13:
  279. case 14:
  280. case 15:
  281. case 16:
  282. i2c_phy_addr = i2c_addr[3];
  283. phy_addr = 0xc;
  284. break;
  285. }
  286. /* Check the PHY status */
  287. ret = miiphy_set_current_dev(dev);
  288. ret = miiphy_write(dev, phy_addr, 0x1f, 3);
  289. mdelay(10);
  290. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  291. mdelay(10);
  292. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  293. mdelay(10);
  294. if ((value & 0xf) == 0xf) {
  295. printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
  296. return;
  297. }
  298. for (i = 0; i < 4; i++) {
  299. for (j = 0; j < 4; j++) {
  300. reg_pair[3].val = &ch_a_eq[i];
  301. reg_pair[4].val = &ch_a_ctl2[j];
  302. reg_pair[5].val = &ch_b_eq[i];
  303. reg_pair[6].val = &ch_b_ctl2[j];
  304. for (k = 0; k < 10; k++) {
  305. #if !CONFIG_IS_ENABLED(DM_I2C)
  306. ret = i2c_write(i2c_phy_addr,
  307. reg_pair[k].addr,
  308. 1, reg_pair[k].val, 1);
  309. #else
  310. ret = i2c_get_chip_for_busnum(0,
  311. i2c_phy_addr,
  312. 1, &udev);
  313. if (!ret)
  314. ret = dm_i2c_write(udev,
  315. reg_pair[k].addr,
  316. reg_pair[k].val, 1);
  317. #endif
  318. if (ret)
  319. goto error;
  320. }
  321. mdelay(100);
  322. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  323. if (ret > 0)
  324. goto error;
  325. mdelay(1);
  326. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  327. if (ret > 0)
  328. goto error;
  329. mdelay(10);
  330. if ((value & 0xf) == 0xf) {
  331. printf("DPMAC %d :PHY is ..... Configured\n",
  332. dpmac);
  333. return;
  334. }
  335. }
  336. }
  337. error:
  338. printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
  339. return;
  340. }
  341. static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
  342. {
  343. return mdio_names[muxval];
  344. }
  345. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  346. {
  347. struct mii_dev *bus;
  348. const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
  349. if (!name) {
  350. printf("No bus for muxval %x\n", muxval);
  351. return NULL;
  352. }
  353. bus = miiphy_get_dev_by_name(name);
  354. if (!bus) {
  355. printf("No bus by name %s\n", name);
  356. return NULL;
  357. }
  358. return bus;
  359. }
  360. static void ls2080a_qds_enable_SFP_TX(u8 muxval)
  361. {
  362. u8 brdcfg9;
  363. brdcfg9 = QIXIS_READ(brdcfg[9]);
  364. brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
  365. brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
  366. QIXIS_WRITE(brdcfg[9], brdcfg9);
  367. }
  368. static void ls2080a_qds_mux_mdio(u8 muxval)
  369. {
  370. u8 brdcfg4;
  371. if (muxval <= 5) {
  372. brdcfg4 = QIXIS_READ(brdcfg[4]);
  373. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  374. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  375. QIXIS_WRITE(brdcfg[4], brdcfg4);
  376. }
  377. }
  378. static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
  379. int devad, int regnum)
  380. {
  381. struct ls2080a_qds_mdio *priv = bus->priv;
  382. ls2080a_qds_mux_mdio(priv->muxval);
  383. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  384. }
  385. static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  386. int regnum, u16 value)
  387. {
  388. struct ls2080a_qds_mdio *priv = bus->priv;
  389. ls2080a_qds_mux_mdio(priv->muxval);
  390. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  391. }
  392. static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
  393. {
  394. struct ls2080a_qds_mdio *priv = bus->priv;
  395. return priv->realbus->reset(priv->realbus);
  396. }
  397. static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
  398. {
  399. struct ls2080a_qds_mdio *pmdio;
  400. struct mii_dev *bus = mdio_alloc();
  401. if (!bus) {
  402. printf("Failed to allocate ls2080a_qds MDIO bus\n");
  403. return -1;
  404. }
  405. pmdio = malloc(sizeof(*pmdio));
  406. if (!pmdio) {
  407. printf("Failed to allocate ls2080a_qds private data\n");
  408. free(bus);
  409. return -1;
  410. }
  411. bus->read = ls2080a_qds_mdio_read;
  412. bus->write = ls2080a_qds_mdio_write;
  413. bus->reset = ls2080a_qds_mdio_reset;
  414. strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
  415. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  416. if (!pmdio->realbus) {
  417. printf("No bus with name %s\n", realbusname);
  418. free(bus);
  419. free(pmdio);
  420. return -1;
  421. }
  422. pmdio->muxval = muxval;
  423. bus->priv = pmdio;
  424. return mdio_register(bus);
  425. }
  426. /*
  427. * Initialize the dpmac_info array.
  428. *
  429. */
  430. static void initialize_dpmac_to_slot(void)
  431. {
  432. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  433. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  434. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  435. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  436. int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
  437. FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
  438. >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  439. char *env_hwconfig;
  440. env_hwconfig = env_get("hwconfig");
  441. switch (serdes1_prtcl) {
  442. case 0x07:
  443. case 0x09:
  444. case 0x33:
  445. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  446. serdes1_prtcl);
  447. lane_to_slot_fsm1[0] = EMI1_SLOT1;
  448. lane_to_slot_fsm1[1] = EMI1_SLOT1;
  449. lane_to_slot_fsm1[2] = EMI1_SLOT1;
  450. lane_to_slot_fsm1[3] = EMI1_SLOT1;
  451. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  452. lane_to_slot_fsm1[4] = EMI1_SLOT1;
  453. lane_to_slot_fsm1[5] = EMI1_SLOT1;
  454. lane_to_slot_fsm1[6] = EMI1_SLOT1;
  455. lane_to_slot_fsm1[7] = EMI1_SLOT1;
  456. } else {
  457. lane_to_slot_fsm1[4] = EMI1_SLOT2;
  458. lane_to_slot_fsm1[5] = EMI1_SLOT2;
  459. lane_to_slot_fsm1[6] = EMI1_SLOT2;
  460. lane_to_slot_fsm1[7] = EMI1_SLOT2;
  461. }
  462. break;
  463. case 0x39:
  464. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  465. serdes1_prtcl);
  466. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  467. lane_to_slot_fsm1[0] = EMI1_SLOT3;
  468. lane_to_slot_fsm1[1] = EMI1_SLOT3;
  469. lane_to_slot_fsm1[2] = EMI1_SLOT3;
  470. lane_to_slot_fsm1[3] = EMI_NONE;
  471. } else {
  472. lane_to_slot_fsm1[0] = EMI_NONE;
  473. lane_to_slot_fsm1[1] = EMI_NONE;
  474. lane_to_slot_fsm1[2] = EMI_NONE;
  475. lane_to_slot_fsm1[3] = EMI_NONE;
  476. }
  477. lane_to_slot_fsm1[4] = EMI1_SLOT3;
  478. lane_to_slot_fsm1[5] = EMI1_SLOT3;
  479. lane_to_slot_fsm1[6] = EMI1_SLOT3;
  480. lane_to_slot_fsm1[7] = EMI_NONE;
  481. break;
  482. case 0x4D:
  483. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  484. serdes1_prtcl);
  485. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  486. lane_to_slot_fsm1[0] = EMI1_SLOT3;
  487. lane_to_slot_fsm1[1] = EMI1_SLOT3;
  488. lane_to_slot_fsm1[2] = EMI_NONE;
  489. lane_to_slot_fsm1[3] = EMI_NONE;
  490. } else {
  491. lane_to_slot_fsm1[0] = EMI_NONE;
  492. lane_to_slot_fsm1[1] = EMI_NONE;
  493. lane_to_slot_fsm1[2] = EMI_NONE;
  494. lane_to_slot_fsm1[3] = EMI_NONE;
  495. }
  496. lane_to_slot_fsm1[4] = EMI1_SLOT3;
  497. lane_to_slot_fsm1[5] = EMI1_SLOT3;
  498. lane_to_slot_fsm1[6] = EMI_NONE;
  499. lane_to_slot_fsm1[7] = EMI_NONE;
  500. break;
  501. case 0x2A:
  502. case 0x4B:
  503. case 0x4C:
  504. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  505. serdes1_prtcl);
  506. break;
  507. default:
  508. printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  509. __func__, serdes1_prtcl);
  510. break;
  511. }
  512. switch (serdes2_prtcl) {
  513. case 0x07:
  514. case 0x08:
  515. case 0x09:
  516. case 0x49:
  517. printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
  518. serdes2_prtcl);
  519. lane_to_slot_fsm2[0] = EMI1_SLOT4;
  520. lane_to_slot_fsm2[1] = EMI1_SLOT4;
  521. lane_to_slot_fsm2[2] = EMI1_SLOT4;
  522. lane_to_slot_fsm2[3] = EMI1_SLOT4;
  523. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  524. lane_to_slot_fsm2[4] = EMI1_SLOT4;
  525. lane_to_slot_fsm2[5] = EMI1_SLOT4;
  526. lane_to_slot_fsm2[6] = EMI1_SLOT4;
  527. lane_to_slot_fsm2[7] = EMI1_SLOT4;
  528. } else {
  529. /* No MDIO physical connection */
  530. lane_to_slot_fsm2[4] = EMI1_SLOT6;
  531. lane_to_slot_fsm2[5] = EMI1_SLOT6;
  532. lane_to_slot_fsm2[6] = EMI1_SLOT6;
  533. lane_to_slot_fsm2[7] = EMI1_SLOT6;
  534. }
  535. break;
  536. case 0x47:
  537. printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
  538. serdes2_prtcl);
  539. lane_to_slot_fsm2[0] = EMI_NONE;
  540. lane_to_slot_fsm2[1] = EMI1_SLOT5;
  541. lane_to_slot_fsm2[2] = EMI1_SLOT5;
  542. lane_to_slot_fsm2[3] = EMI1_SLOT5;
  543. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  544. lane_to_slot_fsm2[4] = EMI_NONE;
  545. lane_to_slot_fsm2[5] = EMI1_SLOT5;
  546. lane_to_slot_fsm2[6] = EMI1_SLOT5;
  547. lane_to_slot_fsm2[7] = EMI1_SLOT5;
  548. }
  549. break;
  550. case 0x57:
  551. printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
  552. serdes2_prtcl);
  553. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  554. lane_to_slot_fsm2[0] = EMI_NONE;
  555. lane_to_slot_fsm2[1] = EMI_NONE;
  556. lane_to_slot_fsm2[2] = EMI_NONE;
  557. lane_to_slot_fsm2[3] = EMI_NONE;
  558. }
  559. lane_to_slot_fsm2[4] = EMI_NONE;
  560. lane_to_slot_fsm2[5] = EMI_NONE;
  561. lane_to_slot_fsm2[6] = EMI1_SLOT5;
  562. lane_to_slot_fsm2[7] = EMI1_SLOT5;
  563. break;
  564. default:
  565. printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
  566. __func__ , serdes2_prtcl);
  567. break;
  568. }
  569. }
  570. void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
  571. {
  572. int lane, slot;
  573. struct mii_dev *bus;
  574. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  575. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  576. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  577. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  578. int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
  579. FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
  580. >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  581. int *riser_phy_addr;
  582. char *env_hwconfig = env_get("hwconfig");
  583. if (hwconfig_f("xqsgmii", env_hwconfig))
  584. riser_phy_addr = &xqsgii_riser_phy_addr[0];
  585. else
  586. riser_phy_addr = &sgmii_riser_phy_addr[0];
  587. if (dpmac_id > WRIOP1_DPMAC9)
  588. goto serdes2;
  589. switch (serdes1_prtcl) {
  590. case 0x07:
  591. case 0x39:
  592. case 0x4D:
  593. lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
  594. slot = lane_to_slot_fsm1[lane];
  595. switch (++slot) {
  596. case 1:
  597. /* Slot housing a SGMII riser card? */
  598. wriop_set_phy_address(dpmac_id, 0,
  599. riser_phy_addr[dpmac_id - 1]);
  600. dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  601. bus = mii_dev_for_muxval(EMI1_SLOT1);
  602. wriop_set_mdio(dpmac_id, bus);
  603. break;
  604. case 2:
  605. /* Slot housing a SGMII riser card? */
  606. wriop_set_phy_address(dpmac_id, 0,
  607. riser_phy_addr[dpmac_id - 1]);
  608. dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
  609. bus = mii_dev_for_muxval(EMI1_SLOT2);
  610. wriop_set_mdio(dpmac_id, bus);
  611. break;
  612. case 3:
  613. if (slot == EMI_NONE)
  614. return;
  615. if (serdes1_prtcl == 0x39) {
  616. wriop_set_phy_address(dpmac_id, 0,
  617. riser_phy_addr[dpmac_id - 2]);
  618. if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
  619. env_hwconfig))
  620. wriop_set_phy_address(dpmac_id, 0,
  621. riser_phy_addr[dpmac_id - 3]);
  622. } else {
  623. wriop_set_phy_address(dpmac_id, 0,
  624. riser_phy_addr[dpmac_id - 2]);
  625. if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
  626. env_hwconfig))
  627. wriop_set_phy_address(dpmac_id, 0,
  628. riser_phy_addr[dpmac_id - 3]);
  629. }
  630. dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
  631. bus = mii_dev_for_muxval(EMI1_SLOT3);
  632. wriop_set_mdio(dpmac_id, bus);
  633. break;
  634. case 4:
  635. break;
  636. case 5:
  637. break;
  638. case 6:
  639. break;
  640. }
  641. break;
  642. default:
  643. printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  644. __func__ , serdes1_prtcl);
  645. break;
  646. }
  647. serdes2:
  648. switch (serdes2_prtcl) {
  649. case 0x07:
  650. case 0x08:
  651. case 0x49:
  652. case 0x47:
  653. case 0x57:
  654. lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
  655. (dpmac_id - 9));
  656. slot = lane_to_slot_fsm2[lane];
  657. switch (++slot) {
  658. case 1:
  659. break;
  660. case 3:
  661. break;
  662. case 4:
  663. /* Slot housing a SGMII riser card? */
  664. wriop_set_phy_address(dpmac_id, 0,
  665. riser_phy_addr[dpmac_id - 9]);
  666. dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
  667. bus = mii_dev_for_muxval(EMI1_SLOT4);
  668. wriop_set_mdio(dpmac_id, bus);
  669. break;
  670. case 5:
  671. if (slot == EMI_NONE)
  672. return;
  673. if (serdes2_prtcl == 0x47) {
  674. wriop_set_phy_address(dpmac_id, 0,
  675. riser_phy_addr[dpmac_id - 10]);
  676. if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
  677. env_hwconfig))
  678. wriop_set_phy_address(dpmac_id, 0,
  679. riser_phy_addr[dpmac_id - 11]);
  680. } else {
  681. wriop_set_phy_address(dpmac_id, 0,
  682. riser_phy_addr[dpmac_id - 11]);
  683. }
  684. dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
  685. bus = mii_dev_for_muxval(EMI1_SLOT5);
  686. wriop_set_mdio(dpmac_id, bus);
  687. break;
  688. case 6:
  689. /* Slot housing a SGMII riser card? */
  690. wriop_set_phy_address(dpmac_id, 0,
  691. riser_phy_addr[dpmac_id - 13]);
  692. dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
  693. bus = mii_dev_for_muxval(EMI1_SLOT6);
  694. wriop_set_mdio(dpmac_id, bus);
  695. break;
  696. }
  697. break;
  698. default:
  699. printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
  700. __func__, serdes2_prtcl);
  701. break;
  702. }
  703. }
  704. void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
  705. {
  706. int lane = 0, slot;
  707. struct mii_dev *bus;
  708. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  709. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  710. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  711. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  712. switch (serdes1_prtcl) {
  713. case 0x33:
  714. switch (dpmac_id) {
  715. case 1:
  716. case 2:
  717. case 3:
  718. case 4:
  719. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
  720. break;
  721. case 5:
  722. case 6:
  723. case 7:
  724. case 8:
  725. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
  726. break;
  727. case 9:
  728. case 10:
  729. case 11:
  730. case 12:
  731. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
  732. break;
  733. case 13:
  734. case 14:
  735. case 15:
  736. case 16:
  737. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
  738. break;
  739. }
  740. slot = lane_to_slot_fsm1[lane];
  741. switch (++slot) {
  742. case 1:
  743. /* Slot housing a QSGMII riser card? */
  744. wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
  745. dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  746. bus = mii_dev_for_muxval(EMI1_SLOT1);
  747. wriop_set_mdio(dpmac_id, bus);
  748. break;
  749. case 3:
  750. break;
  751. case 4:
  752. break;
  753. case 5:
  754. break;
  755. case 6:
  756. break;
  757. }
  758. break;
  759. default:
  760. printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  761. serdes1_prtcl);
  762. break;
  763. }
  764. qsgmii_configure_repeater(dpmac_id);
  765. }
  766. void ls2080a_handle_phy_interface_xsgmii(int i)
  767. {
  768. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  769. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  770. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  771. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  772. switch (serdes1_prtcl) {
  773. case 0x2A:
  774. case 0x4B:
  775. case 0x4C:
  776. /*
  777. * XFI does not need a PHY to work, but to avoid U-Boot use
  778. * default PHY address which is zero to a MAC when it found
  779. * a MAC has no PHY address, we give a PHY address to XFI
  780. * MAC, and should not use a real XAUI PHY address, since
  781. * MDIO can access it successfully, and then MDIO thinks
  782. * the XAUI card is used for the XFI MAC, which will cause
  783. * error.
  784. */
  785. wriop_set_phy_address(i, 0, i + 4);
  786. ls2080a_qds_enable_SFP_TX(SFP_TX);
  787. break;
  788. default:
  789. printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  790. serdes1_prtcl);
  791. break;
  792. }
  793. }
  794. #endif
  795. #endif // !CONFIG_DM_ETH
  796. int board_eth_init(struct bd_info *bis)
  797. {
  798. #ifndef CONFIG_DM_ETH
  799. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  800. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  801. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  802. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  803. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  804. int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
  805. FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
  806. >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  807. struct memac_mdio_info *memac_mdio0_info;
  808. struct memac_mdio_info *memac_mdio1_info;
  809. unsigned int i;
  810. char *env_hwconfig;
  811. int error;
  812. env_hwconfig = env_get("hwconfig");
  813. initialize_dpmac_to_slot();
  814. memac_mdio0_info = (struct memac_mdio_info *)malloc(
  815. sizeof(struct memac_mdio_info));
  816. memac_mdio0_info->regs =
  817. (struct memac_mdio_controller *)
  818. CONFIG_SYS_FSL_WRIOP1_MDIO1;
  819. memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
  820. /* Register the real MDIO1 bus */
  821. fm_memac_mdio_init(bis, memac_mdio0_info);
  822. memac_mdio1_info = (struct memac_mdio_info *)malloc(
  823. sizeof(struct memac_mdio_info));
  824. memac_mdio1_info->regs =
  825. (struct memac_mdio_controller *)
  826. CONFIG_SYS_FSL_WRIOP1_MDIO2;
  827. memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
  828. /* Register the real MDIO2 bus */
  829. fm_memac_mdio_init(bis, memac_mdio1_info);
  830. /* Register the muxing front-ends to the MDIO buses */
  831. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
  832. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
  833. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
  834. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
  835. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
  836. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
  837. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
  838. for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  839. switch (wriop_get_enet_if(i)) {
  840. case PHY_INTERFACE_MODE_QSGMII:
  841. ls2080a_handle_phy_interface_qsgmii(i);
  842. break;
  843. case PHY_INTERFACE_MODE_SGMII:
  844. ls2080a_handle_phy_interface_sgmii(i);
  845. break;
  846. case PHY_INTERFACE_MODE_XGMII:
  847. ls2080a_handle_phy_interface_xsgmii(i);
  848. break;
  849. default:
  850. break;
  851. if (i == 16)
  852. i = NUM_WRIOP_PORTS;
  853. }
  854. }
  855. error = cpu_eth_init(bis);
  856. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  857. if (serdes1_prtcl == 0x7)
  858. sgmii_configure_repeater(1);
  859. if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
  860. serdes2_prtcl == 0x49)
  861. sgmii_configure_repeater(2);
  862. }
  863. #endif
  864. #endif // !CONFIG_DM_ETH
  865. #ifdef CONFIG_DM_ETH
  866. return 0;
  867. #else
  868. return pci_eth_init(bis);
  869. #endif
  870. }
  871. #if defined(CONFIG_RESET_PHY_R)
  872. void reset_phy(void)
  873. {
  874. mc_env_boot();
  875. }
  876. #endif /* CONFIG_RESET_PHY_R */
  877. #if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
  878. /* Structure to hold SERDES protocols supported in case of
  879. * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
  880. *
  881. * @serdes_block: the index of the SERDES block
  882. * @serdes_protocol: the decimal value of the protocol supported
  883. * @dts_needed: DTS notes describing the current configuration are needed
  884. *
  885. * When dts_needed is true, the board_fit_config_name_match() function
  886. * will try to exactly match the current configuration of the block with a DTS
  887. * name provided.
  888. */
  889. static struct serdes_configuration {
  890. u8 serdes_block;
  891. u32 serdes_protocol;
  892. bool dts_needed;
  893. } supported_protocols[] = {
  894. /* Serdes block #1 */
  895. {1, 42, true},
  896. /* Serdes block #2 */
  897. {2, 65, false},
  898. };
  899. #define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
  900. static bool protocol_supported(u8 serdes_block, u32 protocol)
  901. {
  902. struct serdes_configuration serdes_conf;
  903. int i;
  904. for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
  905. serdes_conf = supported_protocols[i];
  906. if (serdes_conf.serdes_block == serdes_block &&
  907. serdes_conf.serdes_protocol == protocol)
  908. return true;
  909. }
  910. return false;
  911. }
  912. static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
  913. {
  914. struct serdes_configuration serdes_conf;
  915. int i;
  916. for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
  917. serdes_conf = supported_protocols[i];
  918. if (serdes_conf.serdes_block == serdes_block &&
  919. serdes_conf.serdes_protocol == protocol) {
  920. if (serdes_conf.dts_needed == true)
  921. sprintf(str, "%u", protocol);
  922. else
  923. sprintf(str, "x");
  924. return;
  925. }
  926. }
  927. }
  928. int board_fit_config_name_match(const char *name)
  929. {
  930. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  931. u32 rcw_status = in_le32(&gur->rcwsr[28]);
  932. char srds_s1_str[2], srds_s2_str[2];
  933. u32 srds_s1, srds_s2;
  934. char expected_dts[100];
  935. srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  936. srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  937. srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
  938. srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  939. /* Check for supported protocols. The default DTS will be used
  940. * in this case
  941. */
  942. if (!protocol_supported(1, srds_s1) ||
  943. !protocol_supported(2, srds_s2))
  944. return -1;
  945. get_str_protocol(1, srds_s1, srds_s1_str);
  946. get_str_protocol(2, srds_s2, srds_s2_str);
  947. printf("expected_dts %s\n", expected_dts);
  948. sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s",
  949. srds_s1_str, srds_s2_str);
  950. if (!strcmp(name, expected_dts))
  951. return 0;
  952. printf("this is not!\n");
  953. return -1;
  954. }
  955. #endif