ls1088a.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <i2c.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <errno.h>
  12. #include <netdev.h>
  13. #include <fsl_ifc.h>
  14. #include <fsl_ddr.h>
  15. #include <fsl_sec.h>
  16. #include <asm/global_data.h>
  17. #include <asm/io.h>
  18. #include <fdt_support.h>
  19. #include <linux/delay.h>
  20. #include <linux/libfdt.h>
  21. #include <fsl-mc/fsl_mc.h>
  22. #include <env_internal.h>
  23. #include <asm/arch-fsl-layerscape/soc.h>
  24. #include <asm/arch/ppa.h>
  25. #include <hwconfig.h>
  26. #include <asm/arch/fsl_serdes.h>
  27. #include <asm/arch/soc.h>
  28. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  29. #include "../common/qixis.h"
  30. #include "ls1088a_qixis.h"
  31. #include "../common/vid.h"
  32. #include <fsl_immap.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #ifdef CONFIG_TARGET_LS1088AQDS
  35. #ifdef CONFIG_TFABOOT
  36. struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  37. {
  38. "nor0",
  39. CONFIG_SYS_NOR0_CSPR_EARLY,
  40. CONFIG_SYS_NOR0_CSPR_EXT,
  41. CONFIG_SYS_NOR_AMASK,
  42. CONFIG_SYS_NOR_CSOR,
  43. {
  44. CONFIG_SYS_NOR_FTIM0,
  45. CONFIG_SYS_NOR_FTIM1,
  46. CONFIG_SYS_NOR_FTIM2,
  47. CONFIG_SYS_NOR_FTIM3
  48. },
  49. 0,
  50. CONFIG_SYS_NOR0_CSPR,
  51. 0,
  52. },
  53. {
  54. "nor1",
  55. CONFIG_SYS_NOR1_CSPR_EARLY,
  56. CONFIG_SYS_NOR0_CSPR_EXT,
  57. CONFIG_SYS_NOR_AMASK_EARLY,
  58. CONFIG_SYS_NOR_CSOR,
  59. {
  60. CONFIG_SYS_NOR_FTIM0,
  61. CONFIG_SYS_NOR_FTIM1,
  62. CONFIG_SYS_NOR_FTIM2,
  63. CONFIG_SYS_NOR_FTIM3
  64. },
  65. 0,
  66. CONFIG_SYS_NOR1_CSPR,
  67. CONFIG_SYS_NOR_AMASK,
  68. },
  69. {
  70. "nand",
  71. CONFIG_SYS_NAND_CSPR,
  72. CONFIG_SYS_NAND_CSPR_EXT,
  73. CONFIG_SYS_NAND_AMASK,
  74. CONFIG_SYS_NAND_CSOR,
  75. {
  76. CONFIG_SYS_NAND_FTIM0,
  77. CONFIG_SYS_NAND_FTIM1,
  78. CONFIG_SYS_NAND_FTIM2,
  79. CONFIG_SYS_NAND_FTIM3
  80. },
  81. },
  82. {
  83. "fpga",
  84. CONFIG_SYS_FPGA_CSPR,
  85. CONFIG_SYS_FPGA_CSPR_EXT,
  86. SYS_FPGA_AMASK,
  87. CONFIG_SYS_FPGA_CSOR,
  88. {
  89. SYS_FPGA_CS_FTIM0,
  90. SYS_FPGA_CS_FTIM1,
  91. SYS_FPGA_CS_FTIM2,
  92. SYS_FPGA_CS_FTIM3
  93. },
  94. 0,
  95. SYS_FPGA_CSPR_FINAL,
  96. 0,
  97. }
  98. };
  99. struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  100. {
  101. "nand",
  102. CONFIG_SYS_NAND_CSPR,
  103. CONFIG_SYS_NAND_CSPR_EXT,
  104. CONFIG_SYS_NAND_AMASK,
  105. CONFIG_SYS_NAND_CSOR,
  106. {
  107. CONFIG_SYS_NAND_FTIM0,
  108. CONFIG_SYS_NAND_FTIM1,
  109. CONFIG_SYS_NAND_FTIM2,
  110. CONFIG_SYS_NAND_FTIM3
  111. },
  112. },
  113. {
  114. "reserved",
  115. },
  116. {
  117. "fpga",
  118. CONFIG_SYS_FPGA_CSPR,
  119. CONFIG_SYS_FPGA_CSPR_EXT,
  120. SYS_FPGA_AMASK,
  121. CONFIG_SYS_FPGA_CSOR,
  122. {
  123. SYS_FPGA_CS_FTIM0,
  124. SYS_FPGA_CS_FTIM1,
  125. SYS_FPGA_CS_FTIM2,
  126. SYS_FPGA_CS_FTIM3
  127. },
  128. 0,
  129. SYS_FPGA_CSPR_FINAL,
  130. 0,
  131. }
  132. };
  133. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  134. {
  135. enum boot_src src = get_boot_src();
  136. if (src == BOOT_SOURCE_QSPI_NOR)
  137. regs_info->regs = ifc_cfg_qspi_nor_boot;
  138. else
  139. regs_info->regs = ifc_cfg_ifc_nor_boot;
  140. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  141. }
  142. #endif /* CONFIG_TFABOOT */
  143. #endif /* CONFIG_TARGET_LS1088AQDS */
  144. int board_early_init_f(void)
  145. {
  146. #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
  147. i2c_early_init_f();
  148. #endif
  149. fsl_lsch3_early_init_f();
  150. return 0;
  151. }
  152. #ifdef CONFIG_FSL_QIXIS
  153. unsigned long long get_qixis_addr(void)
  154. {
  155. unsigned long long addr;
  156. if (gd->flags & GD_FLG_RELOC)
  157. addr = QIXIS_BASE_PHYS;
  158. else
  159. addr = QIXIS_BASE_PHYS_EARLY;
  160. /*
  161. * IFC address under 256MB is mapped to 0x30000000, any address above
  162. * is mapped to 0x5_10000000 up to 4GB.
  163. */
  164. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  165. return addr;
  166. }
  167. #endif
  168. #if defined(CONFIG_VID)
  169. int init_func_vid(void)
  170. {
  171. if (adjust_vdd(0) < 0)
  172. printf("core voltage not adjusted\n");
  173. return 0;
  174. }
  175. #endif
  176. int is_pb_board(void)
  177. {
  178. u8 board_id;
  179. board_id = QIXIS_READ(id);
  180. if (board_id == LS1088ARDB_PB_BOARD)
  181. return 1;
  182. else
  183. return 0;
  184. }
  185. int fixup_ls1088ardb_pb_banner(void *fdt)
  186. {
  187. fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
  188. return 0;
  189. }
  190. #if !defined(CONFIG_SPL_BUILD)
  191. int checkboard(void)
  192. {
  193. #ifdef CONFIG_TFABOOT
  194. enum boot_src src = get_boot_src();
  195. #endif
  196. char buf[64];
  197. u8 sw;
  198. static const char *const freq[] = {"100", "125", "156.25",
  199. "100 separate SSCG"};
  200. int clock;
  201. #ifdef CONFIG_TARGET_LS1088AQDS
  202. printf("Board: LS1088A-QDS, ");
  203. #else
  204. if (is_pb_board())
  205. printf("Board: LS1088ARDB-PB, ");
  206. else
  207. printf("Board: LS1088A-RDB, ");
  208. #endif
  209. sw = QIXIS_READ(arch);
  210. printf("Board Arch: V%d, ", sw >> 4);
  211. #ifdef CONFIG_TARGET_LS1088AQDS
  212. printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  213. #else
  214. printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  215. #endif
  216. memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  217. sw = QIXIS_READ(brdcfg[0]);
  218. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  219. #ifdef CONFIG_TFABOOT
  220. if (src == BOOT_SOURCE_SD_MMC)
  221. puts("SD card\n");
  222. #else
  223. #ifdef CONFIG_SD_BOOT
  224. puts("SD card\n");
  225. #endif
  226. #endif /* CONFIG_TFABOOT */
  227. switch (sw) {
  228. #ifdef CONFIG_TARGET_LS1088AQDS
  229. case 0:
  230. case 1:
  231. case 2:
  232. case 3:
  233. case 4:
  234. case 5:
  235. case 6:
  236. case 7:
  237. printf("vBank: %d\n", sw);
  238. break;
  239. case 8:
  240. puts("PromJet\n");
  241. break;
  242. case 15:
  243. puts("IFCCard\n");
  244. break;
  245. case 14:
  246. #else
  247. case 0:
  248. #endif
  249. puts("QSPI:");
  250. sw = QIXIS_READ(brdcfg[0]);
  251. sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
  252. if (sw == 0 || sw == 4)
  253. puts("0\n");
  254. else if (sw == 1)
  255. puts("1\n");
  256. else
  257. puts("EMU\n");
  258. break;
  259. default:
  260. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  261. break;
  262. }
  263. #ifdef CONFIG_TARGET_LS1088AQDS
  264. printf("FPGA: v%d (%s), build %d",
  265. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  266. (int)qixis_read_minor());
  267. /* the timestamp string contains "\n" at the end */
  268. printf(" on %s", qixis_read_time(buf));
  269. #else
  270. printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  271. #endif
  272. /*
  273. * Display the actual SERDES reference clocks as configured by the
  274. * dip switches on the board. Note that the SWx registers could
  275. * technically be set to force the reference clocks to match the
  276. * values that the SERDES expects (or vice versa). For now, however,
  277. * we just display both values and hope the user notices when they
  278. * don't match.
  279. */
  280. puts("SERDES1 Reference : ");
  281. sw = QIXIS_READ(brdcfg[2]);
  282. clock = (sw >> 6) & 3;
  283. printf("Clock1 = %sMHz ", freq[clock]);
  284. clock = (sw >> 4) & 3;
  285. printf("Clock2 = %sMHz", freq[clock]);
  286. puts("\nSERDES2 Reference : ");
  287. clock = (sw >> 2) & 3;
  288. printf("Clock1 = %sMHz ", freq[clock]);
  289. clock = (sw >> 0) & 3;
  290. printf("Clock2 = %sMHz\n", freq[clock]);
  291. return 0;
  292. }
  293. #endif
  294. bool if_board_diff_clk(void)
  295. {
  296. #ifdef CONFIG_TARGET_LS1088AQDS
  297. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  298. return diff_conf & 0x40;
  299. #else
  300. u8 diff_conf = QIXIS_READ(dutcfg[11]);
  301. return diff_conf & 0x80;
  302. #endif
  303. }
  304. unsigned long get_board_sys_clk(void)
  305. {
  306. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  307. switch (sysclk_conf & 0x0f) {
  308. case QIXIS_SYSCLK_83:
  309. return 83333333;
  310. case QIXIS_SYSCLK_100:
  311. return 100000000;
  312. case QIXIS_SYSCLK_125:
  313. return 125000000;
  314. case QIXIS_SYSCLK_133:
  315. return 133333333;
  316. case QIXIS_SYSCLK_150:
  317. return 150000000;
  318. case QIXIS_SYSCLK_160:
  319. return 160000000;
  320. case QIXIS_SYSCLK_166:
  321. return 166666666;
  322. }
  323. return 66666666;
  324. }
  325. unsigned long get_board_ddr_clk(void)
  326. {
  327. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  328. if (if_board_diff_clk())
  329. return get_board_sys_clk();
  330. switch ((ddrclk_conf & 0x30) >> 4) {
  331. case QIXIS_DDRCLK_100:
  332. return 100000000;
  333. case QIXIS_DDRCLK_125:
  334. return 125000000;
  335. case QIXIS_DDRCLK_133:
  336. return 133333333;
  337. }
  338. return 66666666;
  339. }
  340. int select_i2c_ch_pca9547(u8 ch)
  341. {
  342. int ret;
  343. #if !CONFIG_IS_ENABLED(DM_I2C)
  344. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  345. #else
  346. struct udevice *dev;
  347. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  348. if (!ret)
  349. ret = dm_i2c_write(dev, 0, &ch, 1);
  350. #endif
  351. if (ret) {
  352. puts("PCA: failed to select proper channel\n");
  353. return ret;
  354. }
  355. return 0;
  356. }
  357. #if !defined(CONFIG_SPL_BUILD)
  358. void board_retimer_init(void)
  359. {
  360. u8 reg;
  361. /* Retimer is connected to I2C1_CH5 */
  362. select_i2c_ch_pca9547(I2C_MUX_CH5);
  363. /* Access to Control/Shared register */
  364. reg = 0x0;
  365. #if !CONFIG_IS_ENABLED(DM_I2C)
  366. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  367. #else
  368. struct udevice *dev;
  369. i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
  370. dm_i2c_write(dev, 0xff, &reg, 1);
  371. #endif
  372. /* Read device revision and ID */
  373. #if !CONFIG_IS_ENABLED(DM_I2C)
  374. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  375. #else
  376. dm_i2c_read(dev, 1, &reg, 1);
  377. #endif
  378. debug("Retimer version id = 0x%x\n", reg);
  379. /* Enable Broadcast. All writes target all channel register sets */
  380. reg = 0x0c;
  381. #if !CONFIG_IS_ENABLED(DM_I2C)
  382. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  383. #else
  384. dm_i2c_write(dev, 0xff, &reg, 1);
  385. #endif
  386. /* Reset Channel Registers */
  387. #if !CONFIG_IS_ENABLED(DM_I2C)
  388. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  389. #else
  390. dm_i2c_read(dev, 0, &reg, 1);
  391. #endif
  392. reg |= 0x4;
  393. #if !CONFIG_IS_ENABLED(DM_I2C)
  394. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  395. #else
  396. dm_i2c_write(dev, 0, &reg, 1);
  397. #endif
  398. /* Set data rate as 10.3125 Gbps */
  399. reg = 0x90;
  400. #if !CONFIG_IS_ENABLED(DM_I2C)
  401. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  402. #else
  403. dm_i2c_write(dev, 0x60, &reg, 1);
  404. #endif
  405. reg = 0xb3;
  406. #if !CONFIG_IS_ENABLED(DM_I2C)
  407. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  408. #else
  409. dm_i2c_write(dev, 0x61, &reg, 1);
  410. #endif
  411. reg = 0x90;
  412. #if !CONFIG_IS_ENABLED(DM_I2C)
  413. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  414. #else
  415. dm_i2c_write(dev, 0x62, &reg, 1);
  416. #endif
  417. reg = 0xb3;
  418. #if !CONFIG_IS_ENABLED(DM_I2C)
  419. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  420. #else
  421. dm_i2c_write(dev, 0x63, &reg, 1);
  422. #endif
  423. reg = 0xcd;
  424. #if !CONFIG_IS_ENABLED(DM_I2C)
  425. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  426. #else
  427. dm_i2c_write(dev, 0x64, &reg, 1);
  428. #endif
  429. /* Select VCO Divider to full rate (000) */
  430. #if !CONFIG_IS_ENABLED(DM_I2C)
  431. i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
  432. #else
  433. dm_i2c_read(dev, 0x2F, &reg, 1);
  434. #endif
  435. reg &= 0x0f;
  436. reg |= 0x70;
  437. #if !CONFIG_IS_ENABLED(DM_I2C)
  438. i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
  439. #else
  440. dm_i2c_write(dev, 0x2F, &reg, 1);
  441. #endif
  442. #ifdef CONFIG_TARGET_LS1088AQDS
  443. /* Retimer is connected to I2C1_CH5 */
  444. select_i2c_ch_pca9547(I2C_MUX_CH5);
  445. /* Access to Control/Shared register */
  446. reg = 0x0;
  447. #if !CONFIG_IS_ENABLED(DM_I2C)
  448. i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
  449. #else
  450. i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
  451. dm_i2c_write(dev, 0xff, &reg, 1);
  452. #endif
  453. /* Read device revision and ID */
  454. #if !CONFIG_IS_ENABLED(DM_I2C)
  455. i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
  456. #else
  457. dm_i2c_read(dev, 1, &reg, 1);
  458. #endif
  459. debug("Retimer version id = 0x%x\n", reg);
  460. /* Enable Broadcast. All writes target all channel register sets */
  461. reg = 0x0c;
  462. #if !CONFIG_IS_ENABLED(DM_I2C)
  463. i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
  464. #else
  465. dm_i2c_write(dev, 0xff, &reg, 1);
  466. #endif
  467. /* Reset Channel Registers */
  468. #if !CONFIG_IS_ENABLED(DM_I2C)
  469. i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
  470. #else
  471. dm_i2c_read(dev, 0, &reg, 1);
  472. #endif
  473. reg |= 0x4;
  474. #if !CONFIG_IS_ENABLED(DM_I2C)
  475. i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
  476. #else
  477. dm_i2c_write(dev, 0, &reg, 1);
  478. #endif
  479. /* Set data rate as 10.3125 Gbps */
  480. reg = 0x90;
  481. #if !CONFIG_IS_ENABLED(DM_I2C)
  482. i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
  483. #else
  484. dm_i2c_write(dev, 0x60, &reg, 1);
  485. #endif
  486. reg = 0xb3;
  487. #if !CONFIG_IS_ENABLED(DM_I2C)
  488. i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
  489. #else
  490. dm_i2c_write(dev, 0x61, &reg, 1);
  491. #endif
  492. reg = 0x90;
  493. #if !CONFIG_IS_ENABLED(DM_I2C)
  494. i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
  495. #else
  496. dm_i2c_write(dev, 0x62, &reg, 1);
  497. #endif
  498. reg = 0xb3;
  499. #if !CONFIG_IS_ENABLED(DM_I2C)
  500. i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
  501. #else
  502. dm_i2c_write(dev, 0x63, &reg, 1);
  503. #endif
  504. reg = 0xcd;
  505. #if !CONFIG_IS_ENABLED(DM_I2C)
  506. i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
  507. #else
  508. dm_i2c_write(dev, 0x64, &reg, 1);
  509. #endif
  510. /* Select VCO Divider to full rate (000) */
  511. #if !CONFIG_IS_ENABLED(DM_I2C)
  512. i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
  513. #else
  514. dm_i2c_read(dev, 0x2F, &reg, 1);
  515. #endif
  516. reg &= 0x0f;
  517. reg |= 0x70;
  518. #if !CONFIG_IS_ENABLED(DM_I2C)
  519. i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
  520. #else
  521. dm_i2c_write(dev, 0x2F, &reg, 1);
  522. #endif
  523. #endif
  524. /*return the default channel*/
  525. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  526. }
  527. #ifdef CONFIG_MISC_INIT_R
  528. int misc_init_r(void)
  529. {
  530. #ifdef CONFIG_TARGET_LS1088ARDB
  531. u8 brdcfg5;
  532. if (hwconfig("esdhc-force-sd")) {
  533. brdcfg5 = QIXIS_READ(brdcfg[5]);
  534. brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
  535. brdcfg5 |= BRDCFG5_FORCE_SD;
  536. QIXIS_WRITE(brdcfg[5], brdcfg5);
  537. }
  538. #endif
  539. #ifdef CONFIG_TARGET_LS1088AQDS
  540. u8 brdcfg4, brdcfg5;
  541. if (hwconfig("dspi-on-board")) {
  542. brdcfg4 = QIXIS_READ(brdcfg[4]);
  543. brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
  544. brdcfg4 |= BRDCFG4_SPI;
  545. QIXIS_WRITE(brdcfg[4], brdcfg4);
  546. brdcfg5 = QIXIS_READ(brdcfg[5]);
  547. brdcfg5 &= ~BRDCFG5_SPR_MASK;
  548. brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
  549. QIXIS_WRITE(brdcfg[5], brdcfg5);
  550. } else if (hwconfig("dspi-off-board")) {
  551. brdcfg4 = QIXIS_READ(brdcfg[4]);
  552. brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
  553. brdcfg4 |= BRDCFG4_SPI;
  554. QIXIS_WRITE(brdcfg[4], brdcfg4);
  555. brdcfg5 = QIXIS_READ(brdcfg[5]);
  556. brdcfg5 &= ~BRDCFG5_SPR_MASK;
  557. brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
  558. QIXIS_WRITE(brdcfg[5], brdcfg5);
  559. }
  560. #endif
  561. return 0;
  562. }
  563. #endif
  564. #endif
  565. int i2c_multiplexer_select_vid_channel(u8 channel)
  566. {
  567. return select_i2c_ch_pca9547(channel);
  568. }
  569. #ifdef CONFIG_TARGET_LS1088AQDS
  570. /* read the current value(SVDD) of the LTM Regulator Voltage */
  571. int get_serdes_volt(void)
  572. {
  573. int ret, vcode = 0;
  574. u8 chan = PWM_CHANNEL0;
  575. /* Select the PAGE 0 using PMBus commands PAGE for VDD */
  576. #if !CONFIG_IS_ENABLED(DM_I2C)
  577. ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
  578. PMBUS_CMD_PAGE, 1, &chan, 1);
  579. #else
  580. struct udevice *dev;
  581. ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
  582. if (!ret)
  583. ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
  584. &chan, 1);
  585. #endif
  586. if (ret) {
  587. printf("VID: failed to select VDD Page 0\n");
  588. return ret;
  589. }
  590. /* Read the output voltage using PMBus command READ_VOUT */
  591. #if !CONFIG_IS_ENABLED(DM_I2C)
  592. ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
  593. PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
  594. #else
  595. dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
  596. #endif
  597. if (ret) {
  598. printf("VID: failed to read the volatge\n");
  599. return ret;
  600. }
  601. return vcode;
  602. }
  603. int set_serdes_volt(int svdd)
  604. {
  605. int ret, vdd_last;
  606. u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
  607. svdd & 0xFF, (svdd & 0xFF00) >> 8};
  608. /* Write the desired voltage code to the SVDD regulator */
  609. #if !CONFIG_IS_ENABLED(DM_I2C)
  610. ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
  611. PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
  612. #else
  613. struct udevice *dev;
  614. ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
  615. if (!ret)
  616. ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
  617. (void *)&buff, 5);
  618. #endif
  619. if (ret) {
  620. printf("VID: I2C failed to write to the volatge regulator\n");
  621. return -1;
  622. }
  623. /* Wait for the volatge to get to the desired value */
  624. do {
  625. vdd_last = get_serdes_volt();
  626. if (vdd_last < 0) {
  627. printf("VID: Couldn't read sensor abort VID adjust\n");
  628. return -1;
  629. }
  630. } while (vdd_last != svdd);
  631. return 1;
  632. }
  633. #else
  634. int get_serdes_volt(void)
  635. {
  636. return 0;
  637. }
  638. int set_serdes_volt(int svdd)
  639. {
  640. int ret;
  641. u8 brdcfg4;
  642. printf("SVDD changing of RDB\n");
  643. /* Read the BRDCFG54 via CLPD */
  644. #if !CONFIG_IS_ENABLED(DM_I2C)
  645. ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
  646. QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
  647. #else
  648. struct udevice *dev;
  649. ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
  650. if (!ret)
  651. ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
  652. (void *)&brdcfg4, 1);
  653. #endif
  654. if (ret) {
  655. printf("VID: I2C failed to read the CPLD BRDCFG4\n");
  656. return -1;
  657. }
  658. brdcfg4 = brdcfg4 | 0x08;
  659. /* Write to the BRDCFG4 */
  660. #if !CONFIG_IS_ENABLED(DM_I2C)
  661. ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
  662. QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
  663. #else
  664. ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
  665. (void *)&brdcfg4, 1);
  666. #endif
  667. if (ret) {
  668. debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
  669. return -1;
  670. }
  671. /* Wait for the volatge to get to the desired value */
  672. udelay(10000);
  673. return 1;
  674. }
  675. #endif
  676. /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
  677. int board_adjust_vdd(int vdd)
  678. {
  679. int ret = 0;
  680. debug("%s: vdd = %d\n", __func__, vdd);
  681. /* Special settings to be performed when voltage is 900mV */
  682. if (vdd == 900) {
  683. ret = setup_serdes_volt(vdd);
  684. if (ret < 0) {
  685. ret = -1;
  686. goto exit;
  687. }
  688. }
  689. exit:
  690. return ret;
  691. }
  692. #if !defined(CONFIG_SPL_BUILD)
  693. int board_init(void)
  694. {
  695. init_final_memctl_regs();
  696. #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
  697. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  698. #endif
  699. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  700. board_retimer_init();
  701. #ifdef CONFIG_ENV_IS_NOWHERE
  702. gd->env_addr = (ulong)&default_environment[0];
  703. #endif
  704. #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
  705. /* invert AQR105 IRQ pins polarity */
  706. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
  707. #endif
  708. #ifdef CONFIG_FSL_CAAM
  709. sec_init();
  710. #endif
  711. #ifdef CONFIG_FSL_LS_PPA
  712. ppa_init();
  713. #endif
  714. #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
  715. pci_init();
  716. #endif
  717. return 0;
  718. }
  719. void detail_board_ddr_info(void)
  720. {
  721. puts("\nDDR ");
  722. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  723. print_ddr_info(0);
  724. }
  725. #ifdef CONFIG_FSL_MC_ENET
  726. void board_quiesce_devices(void)
  727. {
  728. fsl_mc_ldpaa_exit(gd->bd);
  729. }
  730. void fdt_fixup_board_enet(void *fdt)
  731. {
  732. int offset;
  733. offset = fdt_path_offset(fdt, "/fsl-mc");
  734. if (offset < 0)
  735. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  736. if (offset < 0) {
  737. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  738. __func__, offset);
  739. return;
  740. }
  741. if (get_mc_boot_status() == 0 &&
  742. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  743. fdt_status_okay(fdt, offset);
  744. else
  745. fdt_status_fail(fdt, offset);
  746. }
  747. #endif
  748. #ifdef CONFIG_OF_BOARD_SETUP
  749. void fsl_fdt_fixup_flash(void *fdt)
  750. {
  751. int offset;
  752. #ifdef CONFIG_TFABOOT
  753. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  754. u32 val;
  755. #endif
  756. /*
  757. * IFC-NOR and QSPI are muxed on SoC.
  758. * So disable IFC node in dts if QSPI is enabled or
  759. * disable QSPI node in dts in case QSPI is not enabled.
  760. */
  761. #ifdef CONFIG_TFABOOT
  762. enum boot_src src = get_boot_src();
  763. bool disable_ifc = false;
  764. switch (src) {
  765. case BOOT_SOURCE_IFC_NOR:
  766. disable_ifc = false;
  767. break;
  768. case BOOT_SOURCE_QSPI_NOR:
  769. disable_ifc = true;
  770. break;
  771. default:
  772. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  773. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  774. disable_ifc = true;
  775. break;
  776. }
  777. if (disable_ifc) {
  778. offset = fdt_path_offset(fdt, "/soc/ifc/nor");
  779. if (offset < 0)
  780. offset = fdt_path_offset(fdt, "/ifc/nor");
  781. } else {
  782. offset = fdt_path_offset(fdt, "/soc/quadspi");
  783. if (offset < 0)
  784. offset = fdt_path_offset(fdt, "/quadspi");
  785. }
  786. #else
  787. #ifdef CONFIG_FSL_QSPI
  788. offset = fdt_path_offset(fdt, "/soc/ifc/nor");
  789. if (offset < 0)
  790. offset = fdt_path_offset(fdt, "/ifc/nor");
  791. #else
  792. offset = fdt_path_offset(fdt, "/soc/quadspi");
  793. if (offset < 0)
  794. offset = fdt_path_offset(fdt, "/quadspi");
  795. #endif
  796. #endif
  797. if (offset < 0)
  798. return;
  799. fdt_status_disabled(fdt, offset);
  800. }
  801. int ft_board_setup(void *blob, struct bd_info *bd)
  802. {
  803. int i;
  804. u16 mc_memory_bank = 0;
  805. u64 *base;
  806. u64 *size;
  807. u64 mc_memory_base = 0;
  808. u64 mc_memory_size = 0;
  809. u16 total_memory_banks;
  810. ft_cpu_setup(blob, bd);
  811. fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
  812. if (mc_memory_base != 0)
  813. mc_memory_bank++;
  814. total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
  815. base = calloc(total_memory_banks, sizeof(u64));
  816. size = calloc(total_memory_banks, sizeof(u64));
  817. /* fixup DT for the two GPP DDR banks */
  818. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  819. base[i] = gd->bd->bi_dram[i].start;
  820. size[i] = gd->bd->bi_dram[i].size;
  821. }
  822. #ifdef CONFIG_RESV_RAM
  823. /* reduce size if reserved memory is within this bank */
  824. if (gd->arch.resv_ram >= base[0] &&
  825. gd->arch.resv_ram < base[0] + size[0])
  826. size[0] = gd->arch.resv_ram - base[0];
  827. else if (gd->arch.resv_ram >= base[1] &&
  828. gd->arch.resv_ram < base[1] + size[1])
  829. size[1] = gd->arch.resv_ram - base[1];
  830. #endif
  831. if (mc_memory_base != 0) {
  832. for (i = 0; i <= total_memory_banks; i++) {
  833. if (base[i] == 0 && size[i] == 0) {
  834. base[i] = mc_memory_base;
  835. size[i] = mc_memory_size;
  836. break;
  837. }
  838. }
  839. }
  840. fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
  841. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  842. fsl_fdt_fixup_flash(blob);
  843. #ifdef CONFIG_FSL_MC_ENET
  844. fdt_fixup_board_enet(blob);
  845. #endif
  846. fdt_fixup_icid(blob);
  847. if (is_pb_board())
  848. fixup_ls1088ardb_pb_banner(blob);
  849. return 0;
  850. }
  851. #endif
  852. #endif /* defined(CONFIG_SPL_BUILD) */
  853. #ifdef CONFIG_TFABOOT
  854. #ifdef CONFIG_MTD_NOR_FLASH
  855. int is_flash_available(void)
  856. {
  857. char *env_hwconfig = env_get("hwconfig");
  858. enum boot_src src = get_boot_src();
  859. int is_nor_flash_available = 1;
  860. switch (src) {
  861. case BOOT_SOURCE_IFC_NOR:
  862. is_nor_flash_available = 1;
  863. break;
  864. case BOOT_SOURCE_QSPI_NOR:
  865. is_nor_flash_available = 0;
  866. break;
  867. /*
  868. * In Case of SD boot,if qspi is defined in env_hwconfig
  869. * disable nor flash probe.
  870. */
  871. default:
  872. if (hwconfig_f("qspi", env_hwconfig))
  873. is_nor_flash_available = 0;
  874. break;
  875. }
  876. return is_nor_flash_available;
  877. }
  878. #endif
  879. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  880. void *env_sf_get_env_addr(void)
  881. {
  882. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  883. }
  884. #endif
  885. #endif