eth_ls1088aqds.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <log.h>
  9. #include <net.h>
  10. #include <netdev.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/fsl_serdes.h>
  13. #include <hwconfig.h>
  14. #include <fsl_mdio.h>
  15. #include <malloc.h>
  16. #include <phy.h>
  17. #include <fm_eth.h>
  18. #include <i2c.h>
  19. #include <miiphy.h>
  20. #include <fsl-mc/fsl_mc.h>
  21. #include <fsl-mc/ldpaa_wriop.h>
  22. #include <linux/delay.h>
  23. #include "../common/qixis.h"
  24. #include "ls1088a_qixis.h"
  25. #ifndef CONFIG_DM_ETH
  26. #ifdef CONFIG_FSL_MC_ENET
  27. #define SFP_TX 0
  28. /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  29. * Bank 1 -> Lanes A, B, C, D,
  30. * Bank 2 -> Lanes A,B, C, D,
  31. */
  32. /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
  33. * means that the mapping must be determined dynamically, or that the lane
  34. * maps to something other than a board slot.
  35. */
  36. static u8 lane_to_slot_fsm1[] = {
  37. 0, 0, 0, 0, 0, 0, 0, 0
  38. };
  39. /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  40. * housed.
  41. */
  42. static int xqsgii_riser_phy_addr[] = {
  43. XQSGMII_CARD_PHY1_PORT0_ADDR,
  44. XQSGMII_CARD_PHY2_PORT0_ADDR,
  45. XQSGMII_CARD_PHY3_PORT0_ADDR,
  46. XQSGMII_CARD_PHY4_PORT0_ADDR,
  47. XQSGMII_CARD_PHY3_PORT2_ADDR,
  48. XQSGMII_CARD_PHY1_PORT2_ADDR,
  49. XQSGMII_CARD_PHY4_PORT2_ADDR,
  50. XQSGMII_CARD_PHY2_PORT2_ADDR,
  51. };
  52. static int sgmii_riser_phy_addr[] = {
  53. SGMII_CARD_PORT1_PHY_ADDR,
  54. SGMII_CARD_PORT2_PHY_ADDR,
  55. SGMII_CARD_PORT3_PHY_ADDR,
  56. SGMII_CARD_PORT4_PHY_ADDR,
  57. };
  58. /* Slot2 does not have EMI connections */
  59. #define EMI_NONE 0xFF
  60. #define EMI1_RGMII1 0
  61. #define EMI1_RGMII2 1
  62. #define EMI1_SLOT1 2
  63. static const char * const mdio_names[] = {
  64. "LS1088A_QDS_MDIO0",
  65. "LS1088A_QDS_MDIO1",
  66. "LS1088A_QDS_MDIO2",
  67. DEFAULT_WRIOP_MDIO2_NAME,
  68. };
  69. struct ls1088a_qds_mdio {
  70. u8 muxval;
  71. struct mii_dev *realbus;
  72. };
  73. struct reg_pair {
  74. uint addr;
  75. u8 *val;
  76. };
  77. static void sgmii_configure_repeater(int dpmac)
  78. {
  79. struct mii_dev *bus;
  80. uint8_t a = 0xf;
  81. int i, j, k, ret;
  82. unsigned short value;
  83. const char *dev = "LS1088A_QDS_MDIO2";
  84. int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
  85. int i2c_phy_addr = 0;
  86. int phy_addr = 0;
  87. uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  88. uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  89. uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  90. uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  91. u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
  92. struct reg_pair reg_pair[10] = {
  93. {6, &reg_val[0]}, {4, &reg_val[1]},
  94. {8, &reg_val[2]}, {0xf, NULL},
  95. {0x11, NULL}, {0x16, NULL},
  96. {0x18, NULL}, {0x23, &reg_val[3]},
  97. {0x2d, &reg_val[4]}, {4, &reg_val[5]},
  98. };
  99. #if CONFIG_IS_ENABLED(DM_I2C)
  100. struct udevice *udev;
  101. #endif
  102. /* Set I2c to Slot 1 */
  103. #if !CONFIG_IS_ENABLED(DM_I2C)
  104. ret = i2c_write(0x77, 0, 0, &a, 1);
  105. #else
  106. ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
  107. if (!ret)
  108. ret = dm_i2c_write(udev, 0, &a, 1);
  109. #endif
  110. if (ret)
  111. goto error;
  112. switch (dpmac) {
  113. case 1:
  114. i2c_phy_addr = i2c_addr[1];
  115. phy_addr = 4;
  116. break;
  117. case 2:
  118. i2c_phy_addr = i2c_addr[0];
  119. phy_addr = 0;
  120. break;
  121. case 3:
  122. i2c_phy_addr = i2c_addr[3];
  123. phy_addr = 0xc;
  124. break;
  125. case 7:
  126. i2c_phy_addr = i2c_addr[2];
  127. phy_addr = 8;
  128. break;
  129. }
  130. /* Check the PHY status */
  131. ret = miiphy_set_current_dev(dev);
  132. if (ret > 0)
  133. goto error;
  134. bus = mdio_get_current_dev();
  135. debug("Reading from bus %s\n", bus->name);
  136. ret = miiphy_write(dev, phy_addr, 0x1f, 3);
  137. if (ret > 0)
  138. goto error;
  139. mdelay(10);
  140. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  141. if (ret > 0)
  142. goto error;
  143. mdelay(10);
  144. if ((value & 0xfff) == 0x401) {
  145. miiphy_write(dev, phy_addr, 0x1f, 0);
  146. printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
  147. return;
  148. }
  149. #if CONFIG_IS_ENABLED(DM_I2C)
  150. i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
  151. #endif
  152. for (i = 0; i < 4; i++) {
  153. for (j = 0; j < 4; j++) {
  154. reg_pair[3].val = &ch_a_eq[i];
  155. reg_pair[4].val = &ch_a_ctl2[j];
  156. reg_pair[5].val = &ch_b_eq[i];
  157. reg_pair[6].val = &ch_b_ctl2[j];
  158. for (k = 0; k < 10; k++) {
  159. #if !CONFIG_IS_ENABLED(DM_I2C)
  160. ret = i2c_write(i2c_phy_addr,
  161. reg_pair[k].addr,
  162. 1, reg_pair[k].val, 1);
  163. #else
  164. ret = i2c_get_chip_for_busnum(0,
  165. i2c_phy_addr,
  166. 1, &udev);
  167. if (!ret)
  168. ret = dm_i2c_write(udev,
  169. reg_pair[k].addr,
  170. reg_pair[k].val, 1);
  171. #endif
  172. if (ret)
  173. goto error;
  174. }
  175. mdelay(100);
  176. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  177. if (ret > 0)
  178. goto error;
  179. mdelay(100);
  180. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  181. if (ret > 0)
  182. goto error;
  183. if ((value & 0xfff) == 0x401) {
  184. printf("DPMAC %d :PHY is configured ",
  185. dpmac);
  186. printf("after setting repeater 0x%x\n",
  187. value);
  188. i = 5;
  189. j = 5;
  190. } else {
  191. printf("DPMAC %d :PHY is failed to ",
  192. dpmac);
  193. printf("configure the repeater 0x%x\n", value);
  194. }
  195. }
  196. }
  197. miiphy_write(dev, phy_addr, 0x1f, 0);
  198. error:
  199. if (ret)
  200. printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
  201. return;
  202. }
  203. static void qsgmii_configure_repeater(int dpmac)
  204. {
  205. uint8_t a = 0xf;
  206. int i, j, k;
  207. int i2c_phy_addr = 0;
  208. int phy_addr = 0;
  209. int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
  210. uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  211. uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  212. uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  213. uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  214. u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
  215. struct reg_pair reg_pair[10] = {
  216. {6, &reg_val[0]}, {4, &reg_val[1]},
  217. {8, &reg_val[2]}, {0xf, NULL},
  218. {0x11, NULL}, {0x16, NULL},
  219. {0x18, NULL}, {0x23, &reg_val[3]},
  220. {0x2d, &reg_val[4]}, {4, &reg_val[5]},
  221. };
  222. const char *dev = mdio_names[EMI1_SLOT1];
  223. int ret = 0;
  224. unsigned short value;
  225. #if CONFIG_IS_ENABLED(DM_I2C)
  226. struct udevice *udev;
  227. #endif
  228. /* Set I2c to Slot 1 */
  229. #if !CONFIG_IS_ENABLED(DM_I2C)
  230. ret = i2c_write(0x77, 0, 0, &a, 1);
  231. #else
  232. ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
  233. if (!ret)
  234. ret = dm_i2c_write(udev, 0, &a, 1);
  235. #endif
  236. if (ret)
  237. goto error;
  238. switch (dpmac) {
  239. case 7:
  240. case 8:
  241. case 9:
  242. case 10:
  243. i2c_phy_addr = i2c_addr[2];
  244. phy_addr = 8;
  245. break;
  246. case 3:
  247. case 4:
  248. case 5:
  249. case 6:
  250. i2c_phy_addr = i2c_addr[3];
  251. phy_addr = 0xc;
  252. break;
  253. }
  254. /* Check the PHY status */
  255. ret = miiphy_set_current_dev(dev);
  256. ret = miiphy_write(dev, phy_addr, 0x1f, 3);
  257. mdelay(10);
  258. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  259. mdelay(10);
  260. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  261. mdelay(10);
  262. if ((value & 0xf) == 0xf) {
  263. miiphy_write(dev, phy_addr, 0x1f, 0);
  264. printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
  265. return;
  266. }
  267. #if CONFIG_IS_ENABLED(DM_I2C)
  268. i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
  269. #endif
  270. for (i = 0; i < 4; i++) {
  271. for (j = 0; j < 4; j++) {
  272. reg_pair[3].val = &ch_a_eq[i];
  273. reg_pair[4].val = &ch_a_ctl2[j];
  274. reg_pair[5].val = &ch_b_eq[i];
  275. reg_pair[6].val = &ch_b_ctl2[j];
  276. for (k = 0; k < 10; k++) {
  277. #if !CONFIG_IS_ENABLED(DM_I2C)
  278. ret = i2c_write(i2c_phy_addr,
  279. reg_pair[k].addr,
  280. 1, reg_pair[k].val, 1);
  281. #else
  282. ret = i2c_get_chip_for_busnum(0,
  283. i2c_addr[dpmac],
  284. 1, &udev);
  285. if (!ret)
  286. ret = dm_i2c_write(udev,
  287. reg_pair[k].addr,
  288. reg_pair[k].val, 1);
  289. #endif
  290. if (ret)
  291. goto error;
  292. }
  293. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  294. if (ret > 0)
  295. goto error;
  296. mdelay(1);
  297. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  298. if (ret > 0)
  299. goto error;
  300. mdelay(10);
  301. if ((value & 0xf) == 0xf) {
  302. miiphy_write(dev, phy_addr, 0x1f, 0);
  303. printf("DPMAC %d :PHY is ..... Configured\n",
  304. dpmac);
  305. return;
  306. }
  307. }
  308. }
  309. error:
  310. printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
  311. return;
  312. }
  313. static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
  314. {
  315. return mdio_names[muxval];
  316. }
  317. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  318. {
  319. struct mii_dev *bus;
  320. const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
  321. if (!name) {
  322. printf("No bus for muxval %x\n", muxval);
  323. return NULL;
  324. }
  325. bus = miiphy_get_dev_by_name(name);
  326. if (!bus) {
  327. printf("No bus by name %s\n", name);
  328. return NULL;
  329. }
  330. return bus;
  331. }
  332. static void ls1088a_qds_enable_SFP_TX(u8 muxval)
  333. {
  334. u8 brdcfg9;
  335. brdcfg9 = QIXIS_READ(brdcfg[9]);
  336. brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
  337. brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
  338. QIXIS_WRITE(brdcfg[9], brdcfg9);
  339. }
  340. static void ls1088a_qds_mux_mdio(u8 muxval)
  341. {
  342. u8 brdcfg4;
  343. if (muxval <= 5) {
  344. brdcfg4 = QIXIS_READ(brdcfg[4]);
  345. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  346. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  347. QIXIS_WRITE(brdcfg[4], brdcfg4);
  348. }
  349. }
  350. static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
  351. int devad, int regnum)
  352. {
  353. struct ls1088a_qds_mdio *priv = bus->priv;
  354. ls1088a_qds_mux_mdio(priv->muxval);
  355. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  356. }
  357. static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  358. int regnum, u16 value)
  359. {
  360. struct ls1088a_qds_mdio *priv = bus->priv;
  361. ls1088a_qds_mux_mdio(priv->muxval);
  362. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  363. }
  364. static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
  365. {
  366. struct ls1088a_qds_mdio *priv = bus->priv;
  367. return priv->realbus->reset(priv->realbus);
  368. }
  369. static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
  370. {
  371. struct ls1088a_qds_mdio *pmdio;
  372. struct mii_dev *bus = mdio_alloc();
  373. if (!bus) {
  374. printf("Failed to allocate ls1088a_qds MDIO bus\n");
  375. return -1;
  376. }
  377. pmdio = malloc(sizeof(*pmdio));
  378. if (!pmdio) {
  379. printf("Failed to allocate ls1088a_qds private data\n");
  380. free(bus);
  381. return -1;
  382. }
  383. bus->read = ls1088a_qds_mdio_read;
  384. bus->write = ls1088a_qds_mdio_write;
  385. bus->reset = ls1088a_qds_mdio_reset;
  386. sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
  387. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  388. if (!pmdio->realbus) {
  389. printf("No bus with name %s\n", realbusname);
  390. free(bus);
  391. free(pmdio);
  392. return -1;
  393. }
  394. pmdio->muxval = muxval;
  395. bus->priv = pmdio;
  396. return mdio_register(bus);
  397. }
  398. /*
  399. * Initialize the dpmac_info array.
  400. *
  401. */
  402. static void initialize_dpmac_to_slot(void)
  403. {
  404. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  405. u32 serdes1_prtcl, cfg;
  406. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  407. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  408. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  409. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  410. switch (serdes1_prtcl) {
  411. case 0x12:
  412. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  413. serdes1_prtcl);
  414. lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  415. lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
  416. lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
  417. lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
  418. break;
  419. case 0x15:
  420. case 0x1D:
  421. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  422. serdes1_prtcl);
  423. lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  424. lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
  425. lane_to_slot_fsm1[2] = EMI_NONE;
  426. lane_to_slot_fsm1[3] = EMI_NONE;
  427. break;
  428. case 0x1E:
  429. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  430. serdes1_prtcl);
  431. lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  432. lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
  433. lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
  434. lane_to_slot_fsm1[3] = EMI_NONE;
  435. break;
  436. case 0x3A:
  437. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  438. serdes1_prtcl);
  439. lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  440. lane_to_slot_fsm1[1] = EMI_NONE;
  441. lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
  442. lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
  443. break;
  444. default:
  445. printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  446. __func__, serdes1_prtcl);
  447. break;
  448. }
  449. }
  450. void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
  451. {
  452. struct mii_dev *bus;
  453. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  454. u32 serdes1_prtcl, cfg;
  455. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  456. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  457. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  458. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  459. int *riser_phy_addr;
  460. char *env_hwconfig = env_get("hwconfig");
  461. if (hwconfig_f("xqsgmii", env_hwconfig))
  462. riser_phy_addr = &xqsgii_riser_phy_addr[0];
  463. else
  464. riser_phy_addr = &sgmii_riser_phy_addr[0];
  465. switch (serdes1_prtcl) {
  466. case 0x12:
  467. case 0x15:
  468. case 0x1E:
  469. case 0x3A:
  470. switch (dpmac_id) {
  471. case 1:
  472. wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]);
  473. break;
  474. case 2:
  475. wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]);
  476. break;
  477. case 3:
  478. wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]);
  479. break;
  480. case 7:
  481. wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]);
  482. break;
  483. default:
  484. printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
  485. break;
  486. }
  487. break;
  488. default:
  489. printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  490. __func__, serdes1_prtcl);
  491. return;
  492. }
  493. dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  494. bus = mii_dev_for_muxval(EMI1_SLOT1);
  495. wriop_set_mdio(dpmac_id, bus);
  496. }
  497. void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
  498. {
  499. struct mii_dev *bus;
  500. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  501. u32 serdes1_prtcl, cfg;
  502. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  503. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  504. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  505. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  506. switch (serdes1_prtcl) {
  507. case 0x1D:
  508. case 0x1E:
  509. switch (dpmac_id) {
  510. case 3:
  511. case 4:
  512. case 5:
  513. case 6:
  514. wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9);
  515. break;
  516. case 7:
  517. case 8:
  518. case 9:
  519. case 10:
  520. wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1);
  521. break;
  522. }
  523. dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  524. bus = mii_dev_for_muxval(EMI1_SLOT1);
  525. wriop_set_mdio(dpmac_id, bus);
  526. break;
  527. default:
  528. printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  529. serdes1_prtcl);
  530. break;
  531. }
  532. }
  533. void ls1088a_handle_phy_interface_xsgmii(int i)
  534. {
  535. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  536. u32 serdes1_prtcl, cfg;
  537. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  538. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  539. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  540. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  541. switch (serdes1_prtcl) {
  542. case 0x15:
  543. case 0x1D:
  544. case 0x1E:
  545. wriop_set_phy_address(i, 0, i + 26);
  546. ls1088a_qds_enable_SFP_TX(SFP_TX);
  547. break;
  548. default:
  549. printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  550. serdes1_prtcl);
  551. break;
  552. }
  553. }
  554. static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
  555. {
  556. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  557. u32 serdes1_prtcl, cfg;
  558. struct mii_dev *bus;
  559. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  560. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  561. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  562. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  563. switch (dpmac_id) {
  564. case 4:
  565. wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR);
  566. dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
  567. bus = mii_dev_for_muxval(EMI1_RGMII1);
  568. wriop_set_mdio(dpmac_id, bus);
  569. break;
  570. case 5:
  571. wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR);
  572. dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
  573. bus = mii_dev_for_muxval(EMI1_RGMII2);
  574. wriop_set_mdio(dpmac_id, bus);
  575. break;
  576. default:
  577. printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
  578. serdes1_prtcl);
  579. break;
  580. }
  581. }
  582. #endif
  583. int board_eth_init(struct bd_info *bis)
  584. {
  585. int error = 0, i;
  586. #ifdef CONFIG_FSL_MC_ENET
  587. struct memac_mdio_info *memac_mdio0_info;
  588. char *env_hwconfig = env_get("hwconfig");
  589. initialize_dpmac_to_slot();
  590. memac_mdio0_info = (struct memac_mdio_info *)malloc(
  591. sizeof(struct memac_mdio_info));
  592. memac_mdio0_info->regs =
  593. (struct memac_mdio_controller *)
  594. CONFIG_SYS_FSL_WRIOP1_MDIO1;
  595. memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
  596. /* Register the real MDIO1 bus */
  597. fm_memac_mdio_init(bis, memac_mdio0_info);
  598. /* Register the muxing front-ends to the MDIO buses */
  599. ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
  600. ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
  601. ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
  602. for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  603. switch (wriop_get_enet_if(i)) {
  604. case PHY_INTERFACE_MODE_RGMII:
  605. case PHY_INTERFACE_MODE_RGMII_ID:
  606. ls1088a_handle_phy_interface_rgmii(i);
  607. break;
  608. case PHY_INTERFACE_MODE_QSGMII:
  609. ls1088a_handle_phy_interface_qsgmii(i);
  610. break;
  611. case PHY_INTERFACE_MODE_SGMII:
  612. ls1088a_handle_phy_interface_sgmii(i);
  613. break;
  614. case PHY_INTERFACE_MODE_XGMII:
  615. ls1088a_handle_phy_interface_xsgmii(i);
  616. break;
  617. default:
  618. break;
  619. if (i == 16)
  620. i = NUM_WRIOP_PORTS;
  621. }
  622. }
  623. error = cpu_eth_init(bis);
  624. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  625. for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  626. switch (wriop_get_enet_if(i)) {
  627. case PHY_INTERFACE_MODE_QSGMII:
  628. qsgmii_configure_repeater(i);
  629. break;
  630. case PHY_INTERFACE_MODE_SGMII:
  631. sgmii_configure_repeater(i);
  632. break;
  633. default:
  634. break;
  635. }
  636. if (i == 16)
  637. i = NUM_WRIOP_PORTS;
  638. }
  639. }
  640. #endif
  641. error = pci_eth_init(bis);
  642. return error;
  643. }
  644. #endif // !CONFIG_DM_ETH
  645. #if defined(CONFIG_RESET_PHY_R)
  646. void reset_phy(void)
  647. {
  648. mc_env_boot();
  649. }
  650. #endif /* CONFIG_RESET_PHY_R */
  651. #if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
  652. /* Structure to hold SERDES protocols supported in case of
  653. * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
  654. *
  655. * @serdes_block: the index of the SERDES block
  656. * @serdes_protocol: the decimal value of the protocol supported
  657. * @dts_needed: DTS notes describing the current configuration are needed
  658. *
  659. * When dts_needed is true, the board_fit_config_name_match() function
  660. * will try to exactly match the current configuration of the block with a DTS
  661. * name provided.
  662. */
  663. static struct serdes_configuration {
  664. u8 serdes_block;
  665. u32 serdes_protocol;
  666. bool dts_needed;
  667. } supported_protocols[] = {
  668. /* Serdes block #1 */
  669. {1, 21, true},
  670. {1, 29, true},
  671. };
  672. #define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
  673. static bool protocol_supported(u8 serdes_block, u32 protocol)
  674. {
  675. struct serdes_configuration serdes_conf;
  676. int i;
  677. for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
  678. serdes_conf = supported_protocols[i];
  679. if (serdes_conf.serdes_block == serdes_block &&
  680. serdes_conf.serdes_protocol == protocol)
  681. return true;
  682. }
  683. return false;
  684. }
  685. static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
  686. {
  687. struct serdes_configuration serdes_conf;
  688. int i;
  689. for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
  690. serdes_conf = supported_protocols[i];
  691. if (serdes_conf.serdes_block == serdes_block &&
  692. serdes_conf.serdes_protocol == protocol) {
  693. if (serdes_conf.dts_needed == true)
  694. sprintf(str, "%u", protocol);
  695. else
  696. sprintf(str, "x");
  697. return;
  698. }
  699. }
  700. }
  701. int board_fit_config_name_match(const char *name)
  702. {
  703. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  704. char expected_dts[100];
  705. char srds_s1_str[2];
  706. u32 srds_s1, cfg;
  707. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  708. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  709. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  710. srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
  711. /* Check for supported protocols. The default DTS will be used
  712. * in this case
  713. */
  714. if (!protocol_supported(1, srds_s1))
  715. return -1;
  716. get_str_protocol(1, srds_s1, srds_s1_str);
  717. sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str);
  718. if (!strcmp(name, expected_dts))
  719. return 0;
  720. return -1;
  721. }
  722. #endif