ls1046aqds.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2019-2020 NXP
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <fdt_support.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <init.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/fsl_serdes.h>
  15. #include <asm/arch/ppa.h>
  16. #include <asm/arch/fdt.h>
  17. #include <asm/arch/mmu.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/soc.h>
  20. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  21. #include <ahci.h>
  22. #include <hwconfig.h>
  23. #include <mmc.h>
  24. #include <scsi.h>
  25. #include <fm_eth.h>
  26. #include <fsl_csu.h>
  27. #include <fsl_esdhc.h>
  28. #include <fsl_ifc.h>
  29. #include <fsl_sec.h>
  30. #include <spl.h>
  31. #include "../common/vid.h"
  32. #include "../common/qixis.h"
  33. #include "ls1046aqds_qixis.h"
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  36. void i2c_early_init_f(void);
  37. #endif
  38. #ifdef CONFIG_TFABOOT
  39. struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  40. {
  41. "nor0",
  42. CONFIG_SYS_NOR0_CSPR,
  43. CONFIG_SYS_NOR0_CSPR_EXT,
  44. CONFIG_SYS_NOR_AMASK,
  45. CONFIG_SYS_NOR_CSOR,
  46. {
  47. CONFIG_SYS_NOR_FTIM0,
  48. CONFIG_SYS_NOR_FTIM1,
  49. CONFIG_SYS_NOR_FTIM2,
  50. CONFIG_SYS_NOR_FTIM3
  51. },
  52. },
  53. {
  54. "nor1",
  55. CONFIG_SYS_NOR1_CSPR,
  56. CONFIG_SYS_NOR1_CSPR_EXT,
  57. CONFIG_SYS_NOR_AMASK,
  58. CONFIG_SYS_NOR_CSOR,
  59. {
  60. CONFIG_SYS_NOR_FTIM0,
  61. CONFIG_SYS_NOR_FTIM1,
  62. CONFIG_SYS_NOR_FTIM2,
  63. CONFIG_SYS_NOR_FTIM3
  64. },
  65. },
  66. {
  67. "nand",
  68. CONFIG_SYS_NAND_CSPR,
  69. CONFIG_SYS_NAND_CSPR_EXT,
  70. CONFIG_SYS_NAND_AMASK,
  71. CONFIG_SYS_NAND_CSOR,
  72. {
  73. CONFIG_SYS_NAND_FTIM0,
  74. CONFIG_SYS_NAND_FTIM1,
  75. CONFIG_SYS_NAND_FTIM2,
  76. CONFIG_SYS_NAND_FTIM3
  77. },
  78. },
  79. {
  80. "fpga",
  81. CONFIG_SYS_FPGA_CSPR,
  82. CONFIG_SYS_FPGA_CSPR_EXT,
  83. CONFIG_SYS_FPGA_AMASK,
  84. CONFIG_SYS_FPGA_CSOR,
  85. {
  86. CONFIG_SYS_FPGA_FTIM0,
  87. CONFIG_SYS_FPGA_FTIM1,
  88. CONFIG_SYS_FPGA_FTIM2,
  89. CONFIG_SYS_FPGA_FTIM3
  90. },
  91. }
  92. };
  93. struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  94. {
  95. "nand",
  96. CONFIG_SYS_NAND_CSPR,
  97. CONFIG_SYS_NAND_CSPR_EXT,
  98. CONFIG_SYS_NAND_AMASK,
  99. CONFIG_SYS_NAND_CSOR,
  100. {
  101. CONFIG_SYS_NAND_FTIM0,
  102. CONFIG_SYS_NAND_FTIM1,
  103. CONFIG_SYS_NAND_FTIM2,
  104. CONFIG_SYS_NAND_FTIM3
  105. },
  106. },
  107. {
  108. "nor0",
  109. CONFIG_SYS_NOR0_CSPR,
  110. CONFIG_SYS_NOR0_CSPR_EXT,
  111. CONFIG_SYS_NOR_AMASK,
  112. CONFIG_SYS_NOR_CSOR,
  113. {
  114. CONFIG_SYS_NOR_FTIM0,
  115. CONFIG_SYS_NOR_FTIM1,
  116. CONFIG_SYS_NOR_FTIM2,
  117. CONFIG_SYS_NOR_FTIM3
  118. },
  119. },
  120. {
  121. "nor1",
  122. CONFIG_SYS_NOR1_CSPR,
  123. CONFIG_SYS_NOR1_CSPR_EXT,
  124. CONFIG_SYS_NOR_AMASK,
  125. CONFIG_SYS_NOR_CSOR,
  126. {
  127. CONFIG_SYS_NOR_FTIM0,
  128. CONFIG_SYS_NOR_FTIM1,
  129. CONFIG_SYS_NOR_FTIM2,
  130. CONFIG_SYS_NOR_FTIM3
  131. },
  132. },
  133. {
  134. "fpga",
  135. CONFIG_SYS_FPGA_CSPR,
  136. CONFIG_SYS_FPGA_CSPR_EXT,
  137. CONFIG_SYS_FPGA_AMASK,
  138. CONFIG_SYS_FPGA_CSOR,
  139. {
  140. CONFIG_SYS_FPGA_FTIM0,
  141. CONFIG_SYS_FPGA_FTIM1,
  142. CONFIG_SYS_FPGA_FTIM2,
  143. CONFIG_SYS_FPGA_FTIM3
  144. },
  145. }
  146. };
  147. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  148. {
  149. enum boot_src src = get_boot_src();
  150. if (src == BOOT_SOURCE_IFC_NAND)
  151. regs_info->regs = ifc_cfg_nand_boot;
  152. else
  153. regs_info->regs = ifc_cfg_nor_boot;
  154. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  155. }
  156. #endif
  157. enum {
  158. MUX_TYPE_GPIO,
  159. };
  160. int checkboard(void)
  161. {
  162. #ifdef CONFIG_TFABOOT
  163. enum boot_src src = get_boot_src();
  164. #endif
  165. char buf[64];
  166. #ifndef CONFIG_SD_BOOT
  167. u8 sw;
  168. #endif
  169. puts("Board: LS1046AQDS, boot from ");
  170. #ifdef CONFIG_TFABOOT
  171. if (src == BOOT_SOURCE_SD_MMC)
  172. puts("SD\n");
  173. else {
  174. #endif
  175. #ifdef CONFIG_SD_BOOT
  176. puts("SD\n");
  177. #else
  178. sw = QIXIS_READ(brdcfg[0]);
  179. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  180. if (sw < 0x8)
  181. printf("vBank: %d\n", sw);
  182. else if (sw == 0x8)
  183. puts("PromJet\n");
  184. else if (sw == 0x9)
  185. puts("NAND\n");
  186. else if (sw == 0xF)
  187. printf("QSPI\n");
  188. else
  189. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  190. #endif
  191. #ifdef CONFIG_TFABOOT
  192. }
  193. #endif
  194. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  195. QIXIS_READ(id), QIXIS_READ(arch));
  196. printf("FPGA: v%d (%s), build %d\n",
  197. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  198. (int)qixis_read_minor());
  199. return 0;
  200. }
  201. bool if_board_diff_clk(void)
  202. {
  203. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  204. return diff_conf & 0x40;
  205. }
  206. unsigned long get_board_sys_clk(void)
  207. {
  208. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  209. switch (sysclk_conf & 0x0f) {
  210. case QIXIS_SYSCLK_64:
  211. return 64000000;
  212. case QIXIS_SYSCLK_83:
  213. return 83333333;
  214. case QIXIS_SYSCLK_100:
  215. return 100000000;
  216. case QIXIS_SYSCLK_125:
  217. return 125000000;
  218. case QIXIS_SYSCLK_133:
  219. return 133333333;
  220. case QIXIS_SYSCLK_150:
  221. return 150000000;
  222. case QIXIS_SYSCLK_160:
  223. return 160000000;
  224. case QIXIS_SYSCLK_166:
  225. return 166666666;
  226. }
  227. return 66666666;
  228. }
  229. unsigned long get_board_ddr_clk(void)
  230. {
  231. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  232. if (if_board_diff_clk())
  233. return get_board_sys_clk();
  234. switch ((ddrclk_conf & 0x30) >> 4) {
  235. case QIXIS_DDRCLK_100:
  236. return 100000000;
  237. case QIXIS_DDRCLK_125:
  238. return 125000000;
  239. case QIXIS_DDRCLK_133:
  240. return 133333333;
  241. }
  242. return 66666666;
  243. }
  244. #ifdef CONFIG_LPUART
  245. u32 get_lpuart_clk(void)
  246. {
  247. return gd->bus_clk;
  248. }
  249. #endif
  250. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  251. {
  252. int ret;
  253. #if CONFIG_IS_ENABLED(DM_I2C)
  254. struct udevice *dev;
  255. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  256. 1, &dev);
  257. if (ret) {
  258. printf("%s: Cannot find udev for a bus %d\n", __func__,
  259. bus_num);
  260. return ret;
  261. }
  262. ret = dm_i2c_write(dev, 0, &ch, 1);
  263. #else
  264. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  265. #endif
  266. if (ret) {
  267. puts("PCA: failed to select proper channel\n");
  268. return ret;
  269. }
  270. return 0;
  271. }
  272. int dram_init(void)
  273. {
  274. /*
  275. * When resuming from deep sleep, the I2C channel may not be
  276. * in the default channel. So, switch to the default channel
  277. * before accessing DDR SPD.
  278. *
  279. * PCA9547 mount on I2C1 bus
  280. */
  281. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  282. fsl_initdram();
  283. #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
  284. defined(CONFIG_SPL_BUILD)
  285. /* This will break-before-make MMU for DDR */
  286. update_early_mmu_table();
  287. #endif
  288. return 0;
  289. }
  290. int i2c_multiplexer_select_vid_channel(u8 channel)
  291. {
  292. return select_i2c_ch_pca9547(channel, 0);
  293. }
  294. int board_early_init_f(void)
  295. {
  296. u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
  297. #ifdef CONFIG_HAS_FSL_XHCI_USB
  298. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  299. u32 usb_pwrfault;
  300. #endif
  301. #ifdef CONFIG_LPUART
  302. u8 uart;
  303. #endif
  304. /*
  305. * Enable secure system counter for timer
  306. */
  307. out_le32(cntcr, 0x1);
  308. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  309. i2c_early_init_f();
  310. #endif
  311. fsl_lsch2_early_init_f();
  312. #ifdef CONFIG_HAS_FSL_XHCI_USB
  313. out_be32(&scfg->rcwpmuxcr0, 0x3333);
  314. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  315. usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
  316. SCFG_USBPWRFAULT_USB3_SHIFT) |
  317. (SCFG_USBPWRFAULT_DEDICATED <<
  318. SCFG_USBPWRFAULT_USB2_SHIFT) |
  319. (SCFG_USBPWRFAULT_SHARED <<
  320. SCFG_USBPWRFAULT_USB1_SHIFT);
  321. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  322. #endif
  323. #ifdef CONFIG_LPUART
  324. /* We use lpuart0 as system console */
  325. uart = QIXIS_READ(brdcfg[14]);
  326. uart &= ~CFG_UART_MUX_MASK;
  327. uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
  328. QIXIS_WRITE(brdcfg[14], uart);
  329. #endif
  330. return 0;
  331. }
  332. #ifdef CONFIG_FSL_DEEP_SLEEP
  333. /* determine if it is a warm boot */
  334. bool is_warm_boot(void)
  335. {
  336. #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
  337. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  338. if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
  339. return 1;
  340. return 0;
  341. }
  342. #endif
  343. int config_board_mux(int ctrl_type)
  344. {
  345. u8 reg14;
  346. reg14 = QIXIS_READ(brdcfg[14]);
  347. switch (ctrl_type) {
  348. case MUX_TYPE_GPIO:
  349. reg14 = (reg14 & (~0x6)) | 0x2;
  350. break;
  351. default:
  352. puts("Unsupported mux interface type\n");
  353. return -1;
  354. }
  355. QIXIS_WRITE(brdcfg[14], reg14);
  356. return 0;
  357. }
  358. int config_serdes_mux(void)
  359. {
  360. return 0;
  361. }
  362. #ifdef CONFIG_MISC_INIT_R
  363. int misc_init_r(void)
  364. {
  365. if (hwconfig("gpio"))
  366. config_board_mux(MUX_TYPE_GPIO);
  367. return 0;
  368. }
  369. #endif
  370. int board_init(void)
  371. {
  372. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  373. #ifdef CONFIG_SYS_FSL_SERDES
  374. config_serdes_mux();
  375. #endif
  376. if (adjust_vdd(0))
  377. printf("Warning: Adjusting core voltage failed.\n");
  378. #ifdef CONFIG_FSL_LS_PPA
  379. ppa_init();
  380. #endif
  381. #ifdef CONFIG_NXP_ESBC
  382. /*
  383. * In case of Secure Boot, the IBR configures the SMMU
  384. * to allow only Secure transactions.
  385. * SMMU must be reset in bypass mode.
  386. * Set the ClientPD bit and Clear the USFCFG Bit
  387. */
  388. u32 val;
  389. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  390. out_le32(SMMU_SCR0, val);
  391. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  392. out_le32(SMMU_NSCR0, val);
  393. #endif
  394. #ifdef CONFIG_FSL_CAAM
  395. sec_init();
  396. #endif
  397. return 0;
  398. }
  399. #ifdef CONFIG_OF_BOARD_SETUP
  400. int ft_board_setup(void *blob, struct bd_info *bd)
  401. {
  402. u64 base[CONFIG_NR_DRAM_BANKS];
  403. u64 size[CONFIG_NR_DRAM_BANKS];
  404. u8 reg;
  405. /* fixup DT for the two DDR banks */
  406. base[0] = gd->bd->bi_dram[0].start;
  407. size[0] = gd->bd->bi_dram[0].size;
  408. base[1] = gd->bd->bi_dram[1].start;
  409. size[1] = gd->bd->bi_dram[1].size;
  410. fdt_fixup_memory_banks(blob, base, size, 2);
  411. ft_cpu_setup(blob, bd);
  412. #ifdef CONFIG_SYS_DPAA_FMAN
  413. #ifndef CONFIG_DM_ETH
  414. fdt_fixup_fman_ethernet(blob);
  415. #endif
  416. fdt_fixup_board_enet(blob);
  417. #endif
  418. fdt_fixup_icid(blob);
  419. reg = QIXIS_READ(brdcfg[0]);
  420. reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  421. /* Disable IFC if QSPI is enabled */
  422. if (reg == 0xF)
  423. do_fixup_by_compat(blob, "fsl,ifc",
  424. "status", "disabled", 8 + 1, 1);
  425. return 0;
  426. }
  427. #endif
  428. u8 flash_read8(void *addr)
  429. {
  430. return __raw_readb(addr + 1);
  431. }
  432. void flash_write16(u16 val, void *addr)
  433. {
  434. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  435. __raw_writew(shftval, addr);
  436. }
  437. u16 flash_read16(void *addr)
  438. {
  439. u16 val = __raw_readw(addr);
  440. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  441. }
  442. #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  443. void *env_sf_get_env_addr(void)
  444. {
  445. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  446. }
  447. #endif