ls1043aqds.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. * Copyright 2019-2020 NXP
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <fdt_support.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #include <asm/arch/ppa.h>
  17. #include <asm/arch/fdt.h>
  18. #include <asm/arch/mmu.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/soc.h>
  21. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  22. #include <ahci.h>
  23. #include <hwconfig.h>
  24. #include <mmc.h>
  25. #include <scsi.h>
  26. #include <fm_eth.h>
  27. #include <fsl_esdhc.h>
  28. #include <fsl_ifc.h>
  29. #include <spl.h>
  30. #include "../common/qixis.h"
  31. #include "ls1043aqds_qixis.h"
  32. DECLARE_GLOBAL_DATA_PTR;
  33. enum {
  34. MUX_TYPE_GPIO,
  35. };
  36. /* LS1043AQDS serdes mux */
  37. #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
  38. #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
  39. #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
  40. #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
  41. #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
  42. #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
  43. #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
  44. #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
  45. #define CFG_UART_MUX_MASK 0x6
  46. #define CFG_UART_MUX_SHIFT 1
  47. #define CFG_LPUART_EN 0x1
  48. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  49. void i2c_early_init_f(void);
  50. #endif
  51. #ifdef CONFIG_TFABOOT
  52. struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  53. {
  54. "nor0",
  55. CONFIG_SYS_NOR0_CSPR,
  56. CONFIG_SYS_NOR0_CSPR_EXT,
  57. CONFIG_SYS_NOR_AMASK,
  58. CONFIG_SYS_NOR_CSOR,
  59. {
  60. CONFIG_SYS_NOR_FTIM0,
  61. CONFIG_SYS_NOR_FTIM1,
  62. CONFIG_SYS_NOR_FTIM2,
  63. CONFIG_SYS_NOR_FTIM3
  64. },
  65. },
  66. {
  67. "nor1",
  68. CONFIG_SYS_NOR1_CSPR,
  69. CONFIG_SYS_NOR1_CSPR_EXT,
  70. CONFIG_SYS_NOR_AMASK,
  71. CONFIG_SYS_NOR_CSOR,
  72. {
  73. CONFIG_SYS_NOR_FTIM0,
  74. CONFIG_SYS_NOR_FTIM1,
  75. CONFIG_SYS_NOR_FTIM2,
  76. CONFIG_SYS_NOR_FTIM3
  77. },
  78. },
  79. {
  80. "nand",
  81. CONFIG_SYS_NAND_CSPR,
  82. CONFIG_SYS_NAND_CSPR_EXT,
  83. CONFIG_SYS_NAND_AMASK,
  84. CONFIG_SYS_NAND_CSOR,
  85. {
  86. CONFIG_SYS_NAND_FTIM0,
  87. CONFIG_SYS_NAND_FTIM1,
  88. CONFIG_SYS_NAND_FTIM2,
  89. CONFIG_SYS_NAND_FTIM3
  90. },
  91. },
  92. {
  93. "fpga",
  94. CONFIG_SYS_FPGA_CSPR,
  95. CONFIG_SYS_FPGA_CSPR_EXT,
  96. CONFIG_SYS_FPGA_AMASK,
  97. CONFIG_SYS_FPGA_CSOR,
  98. {
  99. CONFIG_SYS_FPGA_FTIM0,
  100. CONFIG_SYS_FPGA_FTIM1,
  101. CONFIG_SYS_FPGA_FTIM2,
  102. CONFIG_SYS_FPGA_FTIM3
  103. },
  104. }
  105. };
  106. struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  107. {
  108. "nand",
  109. CONFIG_SYS_NAND_CSPR,
  110. CONFIG_SYS_NAND_CSPR_EXT,
  111. CONFIG_SYS_NAND_AMASK,
  112. CONFIG_SYS_NAND_CSOR,
  113. {
  114. CONFIG_SYS_NAND_FTIM0,
  115. CONFIG_SYS_NAND_FTIM1,
  116. CONFIG_SYS_NAND_FTIM2,
  117. CONFIG_SYS_NAND_FTIM3
  118. },
  119. },
  120. {
  121. "nor0",
  122. CONFIG_SYS_NOR0_CSPR,
  123. CONFIG_SYS_NOR0_CSPR_EXT,
  124. CONFIG_SYS_NOR_AMASK,
  125. CONFIG_SYS_NOR_CSOR,
  126. {
  127. CONFIG_SYS_NOR_FTIM0,
  128. CONFIG_SYS_NOR_FTIM1,
  129. CONFIG_SYS_NOR_FTIM2,
  130. CONFIG_SYS_NOR_FTIM3
  131. },
  132. },
  133. {
  134. "nor1",
  135. CONFIG_SYS_NOR1_CSPR,
  136. CONFIG_SYS_NOR1_CSPR_EXT,
  137. CONFIG_SYS_NOR_AMASK,
  138. CONFIG_SYS_NOR_CSOR,
  139. {
  140. CONFIG_SYS_NOR_FTIM0,
  141. CONFIG_SYS_NOR_FTIM1,
  142. CONFIG_SYS_NOR_FTIM2,
  143. CONFIG_SYS_NOR_FTIM3
  144. },
  145. },
  146. {
  147. "fpga",
  148. CONFIG_SYS_FPGA_CSPR,
  149. CONFIG_SYS_FPGA_CSPR_EXT,
  150. CONFIG_SYS_FPGA_AMASK,
  151. CONFIG_SYS_FPGA_CSOR,
  152. {
  153. CONFIG_SYS_FPGA_FTIM0,
  154. CONFIG_SYS_FPGA_FTIM1,
  155. CONFIG_SYS_FPGA_FTIM2,
  156. CONFIG_SYS_FPGA_FTIM3
  157. },
  158. }
  159. };
  160. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  161. {
  162. enum boot_src src = get_boot_src();
  163. if (src == BOOT_SOURCE_IFC_NAND)
  164. regs_info->regs = ifc_cfg_nand_boot;
  165. else
  166. regs_info->regs = ifc_cfg_nor_boot;
  167. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  168. }
  169. #endif
  170. int checkboard(void)
  171. {
  172. #ifdef CONFIG_TFABOOT
  173. enum boot_src src = get_boot_src();
  174. #endif
  175. char buf[64];
  176. #ifndef CONFIG_SD_BOOT
  177. u8 sw;
  178. #endif
  179. puts("Board: LS1043AQDS, boot from ");
  180. #ifdef CONFIG_TFABOOT
  181. if (src == BOOT_SOURCE_SD_MMC)
  182. puts("SD\n");
  183. else {
  184. #endif
  185. #ifdef CONFIG_SD_BOOT
  186. puts("SD\n");
  187. #else
  188. sw = QIXIS_READ(brdcfg[0]);
  189. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  190. if (sw < 0x8)
  191. printf("vBank: %d\n", sw);
  192. else if (sw == 0x8)
  193. puts("PromJet\n");
  194. else if (sw == 0x9)
  195. puts("NAND\n");
  196. else if (sw == 0xF)
  197. printf("QSPI\n");
  198. else
  199. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  200. #endif
  201. #ifdef CONFIG_TFABOOT
  202. }
  203. #endif
  204. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  205. QIXIS_READ(id), QIXIS_READ(arch));
  206. printf("FPGA: v%d (%s), build %d\n",
  207. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  208. (int)qixis_read_minor());
  209. return 0;
  210. }
  211. bool if_board_diff_clk(void)
  212. {
  213. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  214. return diff_conf & 0x40;
  215. }
  216. unsigned long get_board_sys_clk(void)
  217. {
  218. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  219. switch (sysclk_conf & 0x0f) {
  220. case QIXIS_SYSCLK_64:
  221. return 64000000;
  222. case QIXIS_SYSCLK_83:
  223. return 83333333;
  224. case QIXIS_SYSCLK_100:
  225. return 100000000;
  226. case QIXIS_SYSCLK_125:
  227. return 125000000;
  228. case QIXIS_SYSCLK_133:
  229. return 133333333;
  230. case QIXIS_SYSCLK_150:
  231. return 150000000;
  232. case QIXIS_SYSCLK_160:
  233. return 160000000;
  234. case QIXIS_SYSCLK_166:
  235. return 166666666;
  236. }
  237. return 66666666;
  238. }
  239. unsigned long get_board_ddr_clk(void)
  240. {
  241. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  242. if (if_board_diff_clk())
  243. return get_board_sys_clk();
  244. switch ((ddrclk_conf & 0x30) >> 4) {
  245. case QIXIS_DDRCLK_100:
  246. return 100000000;
  247. case QIXIS_DDRCLK_125:
  248. return 125000000;
  249. case QIXIS_DDRCLK_133:
  250. return 133333333;
  251. }
  252. return 66666666;
  253. }
  254. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  255. {
  256. int ret;
  257. #if CONFIG_IS_ENABLED(DM_I2C)
  258. struct udevice *dev;
  259. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  260. 1, &dev);
  261. if (ret) {
  262. printf("%s: Cannot find udev for a bus %d\n", __func__,
  263. bus_num);
  264. return ret;
  265. }
  266. ret = dm_i2c_write(dev, 0, &ch, 1);
  267. #else
  268. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  269. #endif
  270. if (ret) {
  271. puts("PCA: failed to select proper channel\n");
  272. return ret;
  273. }
  274. return 0;
  275. }
  276. int dram_init(void)
  277. {
  278. /*
  279. * When resuming from deep sleep, the I2C channel may not be
  280. * in the default channel. So, switch to the default channel
  281. * before accessing DDR SPD.
  282. *
  283. * PCA9547 mount on I2C1 bus
  284. */
  285. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  286. fsl_initdram();
  287. #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
  288. defined(CONFIG_SPL_BUILD)
  289. /* This will break-before-make MMU for DDR */
  290. update_early_mmu_table();
  291. #endif
  292. return 0;
  293. }
  294. int i2c_multiplexer_select_vid_channel(u8 channel)
  295. {
  296. return select_i2c_ch_pca9547(channel, 0);
  297. }
  298. void board_retimer_init(void)
  299. {
  300. u8 reg;
  301. int bus_num = 0;
  302. /* Retimer is connected to I2C1_CH7_CH5 */
  303. select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
  304. reg = I2C_MUX_CH5;
  305. #if CONFIG_IS_ENABLED(DM_I2C)
  306. struct udevice *dev;
  307. int ret;
  308. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
  309. 1, &dev);
  310. if (ret) {
  311. printf("%s: Cannot find udev for a bus %d\n", __func__,
  312. bus_num);
  313. return;
  314. }
  315. dm_i2c_write(dev, 0, &reg, 1);
  316. /* Access to Control/Shared register */
  317. ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
  318. 1, &dev);
  319. if (ret) {
  320. printf("%s: Cannot find udev for a bus %d\n", __func__,
  321. bus_num);
  322. return;
  323. }
  324. reg = 0x0;
  325. dm_i2c_write(dev, 0xff, &reg, 1);
  326. /* Read device revision and ID */
  327. dm_i2c_read(dev, 1, &reg, 1);
  328. debug("Retimer version id = 0x%x\n", reg);
  329. /* Enable Broadcast. All writes target all channel register sets */
  330. reg = 0x0c;
  331. dm_i2c_write(dev, 0xff, &reg, 1);
  332. /* Reset Channel Registers */
  333. dm_i2c_read(dev, 0, &reg, 1);
  334. reg |= 0x4;
  335. dm_i2c_write(dev, 0, &reg, 1);
  336. /* Enable override divider select and Enable Override Output Mux */
  337. dm_i2c_read(dev, 9, &reg, 1);
  338. reg |= 0x24;
  339. dm_i2c_write(dev, 9, &reg, 1);
  340. /* Select VCO Divider to full rate (000) */
  341. dm_i2c_read(dev, 0x18, &reg, 1);
  342. reg &= 0x8f;
  343. dm_i2c_write(dev, 0x18, &reg, 1);
  344. /* Selects active PFD MUX Input as Re-timed Data (001) */
  345. dm_i2c_read(dev, 0x1e, &reg, 1);
  346. reg &= 0x3f;
  347. reg |= 0x20;
  348. dm_i2c_write(dev, 0x1e, &reg, 1);
  349. /* Set data rate as 10.3125 Gbps */
  350. reg = 0x0;
  351. dm_i2c_write(dev, 0x60, &reg, 1);
  352. reg = 0xb2;
  353. dm_i2c_write(dev, 0x61, &reg, 1);
  354. reg = 0x90;
  355. dm_i2c_write(dev, 0x62, &reg, 1);
  356. reg = 0xb3;
  357. dm_i2c_write(dev, 0x63, &reg, 1);
  358. reg = 0xcd;
  359. dm_i2c_write(dev, 0x64, &reg, 1);
  360. #else
  361. i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
  362. /* Access to Control/Shared register */
  363. reg = 0x0;
  364. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  365. /* Read device revision and ID */
  366. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  367. debug("Retimer version id = 0x%x\n", reg);
  368. /* Enable Broadcast. All writes target all channel register sets */
  369. reg = 0x0c;
  370. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  371. /* Reset Channel Registers */
  372. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  373. reg |= 0x4;
  374. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  375. /* Enable override divider select and Enable Override Output Mux */
  376. i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  377. reg |= 0x24;
  378. i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  379. /* Select VCO Divider to full rate (000) */
  380. i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  381. reg &= 0x8f;
  382. i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  383. /* Selects active PFD MUX Input as Re-timed Data (001) */
  384. i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  385. reg &= 0x3f;
  386. reg |= 0x20;
  387. i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  388. /* Set data rate as 10.3125 Gbps */
  389. reg = 0x0;
  390. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  391. reg = 0xb2;
  392. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  393. reg = 0x90;
  394. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  395. reg = 0xb3;
  396. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  397. reg = 0xcd;
  398. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  399. #endif
  400. /* Return the default channel */
  401. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
  402. }
  403. int board_early_init_f(void)
  404. {
  405. u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
  406. #ifdef CONFIG_HAS_FSL_XHCI_USB
  407. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  408. u32 usb_pwrfault;
  409. #endif
  410. #ifdef CONFIG_LPUART
  411. u8 uart;
  412. #endif
  413. /*
  414. * Enable secure system counter for timer
  415. */
  416. out_le32(cntcr, 0x1);
  417. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  418. i2c_early_init_f();
  419. #endif
  420. fsl_lsch2_early_init_f();
  421. #ifdef CONFIG_HAS_FSL_XHCI_USB
  422. out_be32(&scfg->rcwpmuxcr0, 0x3333);
  423. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  424. usb_pwrfault =
  425. (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
  426. (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
  427. (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
  428. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  429. #endif
  430. #ifdef CONFIG_LPUART
  431. /* We use lpuart0 as system console */
  432. uart = QIXIS_READ(brdcfg[14]);
  433. uart &= ~CFG_UART_MUX_MASK;
  434. uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
  435. QIXIS_WRITE(brdcfg[14], uart);
  436. #endif
  437. return 0;
  438. }
  439. #ifdef CONFIG_FSL_DEEP_SLEEP
  440. /* determine if it is a warm boot */
  441. bool is_warm_boot(void)
  442. {
  443. #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
  444. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  445. if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
  446. return 1;
  447. return 0;
  448. }
  449. #endif
  450. int config_board_mux(int ctrl_type)
  451. {
  452. u8 reg14;
  453. reg14 = QIXIS_READ(brdcfg[14]);
  454. switch (ctrl_type) {
  455. case MUX_TYPE_GPIO:
  456. reg14 = (reg14 & (~0x30)) | 0x20;
  457. break;
  458. default:
  459. puts("Unsupported mux interface type\n");
  460. return -1;
  461. }
  462. QIXIS_WRITE(brdcfg[14], reg14);
  463. return 0;
  464. }
  465. int config_serdes_mux(void)
  466. {
  467. return 0;
  468. }
  469. #ifdef CONFIG_MISC_INIT_R
  470. int misc_init_r(void)
  471. {
  472. if (hwconfig("gpio"))
  473. config_board_mux(MUX_TYPE_GPIO);
  474. return 0;
  475. }
  476. #endif
  477. int board_init(void)
  478. {
  479. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  480. erratum_a010315();
  481. #endif
  482. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  483. board_retimer_init();
  484. #ifdef CONFIG_SYS_FSL_SERDES
  485. config_serdes_mux();
  486. #endif
  487. #ifdef CONFIG_FSL_LS_PPA
  488. ppa_init();
  489. #endif
  490. return 0;
  491. }
  492. #ifdef CONFIG_OF_BOARD_SETUP
  493. int ft_board_setup(void *blob, struct bd_info *bd)
  494. {
  495. u64 base[CONFIG_NR_DRAM_BANKS];
  496. u64 size[CONFIG_NR_DRAM_BANKS];
  497. u8 reg;
  498. /* fixup DT for the two DDR banks */
  499. base[0] = gd->bd->bi_dram[0].start;
  500. size[0] = gd->bd->bi_dram[0].size;
  501. base[1] = gd->bd->bi_dram[1].start;
  502. size[1] = gd->bd->bi_dram[1].size;
  503. fdt_fixup_memory_banks(blob, base, size, 2);
  504. ft_cpu_setup(blob, bd);
  505. #ifdef CONFIG_SYS_DPAA_FMAN
  506. #ifndef CONFIG_DM_ETH
  507. fdt_fixup_fman_ethernet(blob);
  508. #endif
  509. fdt_fixup_board_enet(blob);
  510. #endif
  511. fdt_fixup_icid(blob);
  512. reg = QIXIS_READ(brdcfg[0]);
  513. reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  514. /* Disable IFC if QSPI is enabled */
  515. if (reg == 0xF)
  516. do_fixup_by_compat(blob, "fsl,ifc",
  517. "status", "disabled", 8 + 1, 1);
  518. return 0;
  519. }
  520. #endif
  521. u8 flash_read8(void *addr)
  522. {
  523. return __raw_readb(addr + 1);
  524. }
  525. void flash_write16(u16 val, void *addr)
  526. {
  527. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  528. __raw_writew(shftval, addr);
  529. }
  530. u16 flash_read16(void *addr)
  531. {
  532. u16 val = __raw_readw(addr);
  533. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  534. }
  535. #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  536. void *env_sf_get_env_addr(void)
  537. {
  538. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  539. }
  540. #endif