ls1028a.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <malloc.h>
  8. #include <errno.h>
  9. #include <fsl_ddr.h>
  10. #include <net.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <hwconfig.h>
  14. #include <fdt_support.h>
  15. #include <linux/libfdt.h>
  16. #include <env_internal.h>
  17. #include <asm/arch-fsl-layerscape/soc.h>
  18. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  19. #include <i2c.h>
  20. #include <asm/arch/soc.h>
  21. #ifdef CONFIG_FSL_LS_PPA
  22. #include <asm/arch/ppa.h>
  23. #endif
  24. #include <fsl_immap.h>
  25. #include <netdev.h>
  26. #include <fdtdec.h>
  27. #include <miiphy.h>
  28. #include "../common/qixis.h"
  29. #include "../drivers/net/fsl_enetc.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. int config_board_mux(void)
  32. {
  33. #ifndef CONFIG_LPUART
  34. #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  35. u8 reg;
  36. reg = QIXIS_READ(brdcfg[13]);
  37. /* Field| Function
  38. * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
  39. * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  40. * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
  41. * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  42. */
  43. reg &= ~(0xf0);
  44. reg |= 0xb0;
  45. QIXIS_WRITE(brdcfg[13], reg);
  46. reg = QIXIS_READ(brdcfg[15]);
  47. /* Field| Function
  48. * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  49. * CAN1 | 0= CAN #1 transceiver enabled
  50. * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  51. * CAN2 | 0= CAN #2 transceiver enabled
  52. */
  53. reg &= ~(0xc0);
  54. QIXIS_WRITE(brdcfg[15], reg);
  55. #endif
  56. #endif
  57. return 0;
  58. }
  59. #ifdef CONFIG_LPUART
  60. u32 get_lpuart_clk(void)
  61. {
  62. return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
  63. }
  64. #endif
  65. int board_init(void)
  66. {
  67. #ifdef CONFIG_ENV_IS_NOWHERE
  68. gd->env_addr = (ulong)&default_environment[0];
  69. #endif
  70. #ifdef CONFIG_FSL_CAAM
  71. sec_init();
  72. #endif
  73. #ifdef CONFIG_FSL_LS_PPA
  74. ppa_init();
  75. #endif
  76. #ifndef CONFIG_SYS_EARLY_PCI_INIT
  77. pci_init();
  78. #endif
  79. #if defined(CONFIG_TARGET_LS1028ARDB)
  80. u8 val = I2C_MUX_CH_DEFAULT;
  81. #if !CONFIG_IS_ENABLED(DM_I2C)
  82. i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  83. #else
  84. struct udevice *dev;
  85. if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  86. dm_i2c_write(dev, 0x0b, &val, 1);
  87. #endif
  88. #endif
  89. #if defined(CONFIG_TARGET_LS1028ARDB)
  90. u8 reg;
  91. reg = QIXIS_READ(brdcfg[4]);
  92. /*
  93. * Field | Function
  94. * 3 | DisplayPort Power Enable (net DP_PWR_EN):
  95. * DPPWR | 0= DP_PWR is enabled.
  96. */
  97. reg &= ~(DP_PWD_EN_DEFAULT_MASK);
  98. QIXIS_WRITE(brdcfg[4], reg);
  99. #endif
  100. return 0;
  101. }
  102. int board_eth_init(struct bd_info *bis)
  103. {
  104. return pci_eth_init(bis);
  105. }
  106. #ifdef CONFIG_MISC_INIT_R
  107. int misc_init_r(void)
  108. {
  109. config_board_mux();
  110. return 0;
  111. }
  112. #endif
  113. int board_early_init_f(void)
  114. {
  115. #ifdef CONFIG_LPUART
  116. u8 uart;
  117. #endif
  118. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  119. i2c_early_init_f();
  120. #endif
  121. fsl_lsch3_early_init_f();
  122. #ifdef CONFIG_LPUART
  123. /*
  124. * Field| Function
  125. * --------------------------------------------------------------
  126. * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
  127. * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
  128. * --------------------------------------------------------------
  129. * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
  130. * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
  131. */
  132. /* use lpuart0 as system console */
  133. uart = QIXIS_READ(brdcfg[13]);
  134. uart &= ~CFG_LPUART_MUX_MASK;
  135. uart |= CFG_LPUART_EN;
  136. QIXIS_WRITE(brdcfg[13], uart);
  137. #endif
  138. return 0;
  139. }
  140. void detail_board_ddr_info(void)
  141. {
  142. puts("\nDDR ");
  143. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  144. print_ddr_info(0);
  145. }
  146. int esdhc_status_fixup(void *blob, const char *compat)
  147. {
  148. void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
  149. char esdhc1_path[] = "/soc/mmc@2140000";
  150. char esdhc2_path[] = "/soc/mmc@2150000";
  151. char dspi1_path[] = "/soc/spi@2100000";
  152. char dspi2_path[] = "/soc/spi@2110000";
  153. u32 mux_sdhc1, mux_sdhc2;
  154. u32 io = 0;
  155. /*
  156. * The PMUX IO-expander for mux select is used to control
  157. * the muxing of various onboard interfaces.
  158. */
  159. io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
  160. mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
  161. /* Disable esdhc1/dspi1 if not selected. */
  162. if (mux_sdhc1 != 0)
  163. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  164. sizeof("disabled"), 1);
  165. if (mux_sdhc1 != 2)
  166. do_fixup_by_path(blob, dspi1_path, "status", "disabled",
  167. sizeof("disabled"), 1);
  168. io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
  169. mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
  170. /* Disable esdhc2/dspi2 if not selected. */
  171. if (mux_sdhc2 != 0)
  172. do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
  173. sizeof("disabled"), 1);
  174. if (mux_sdhc2 != 2)
  175. do_fixup_by_path(blob, dspi2_path, "status", "disabled",
  176. sizeof("disabled"), 1);
  177. return 0;
  178. }
  179. #ifdef CONFIG_OF_BOARD_SETUP
  180. int ft_board_setup(void *blob, struct bd_info *bd)
  181. {
  182. u64 base[CONFIG_NR_DRAM_BANKS];
  183. u64 size[CONFIG_NR_DRAM_BANKS];
  184. ft_cpu_setup(blob, bd);
  185. /* fixup DT for the two GPP DDR banks */
  186. base[0] = gd->bd->bi_dram[0].start;
  187. size[0] = gd->bd->bi_dram[0].size;
  188. base[1] = gd->bd->bi_dram[1].start;
  189. size[1] = gd->bd->bi_dram[1].size;
  190. #ifdef CONFIG_RESV_RAM
  191. /* reduce size if reserved memory is within this bank */
  192. if (gd->arch.resv_ram >= base[0] &&
  193. gd->arch.resv_ram < base[0] + size[0])
  194. size[0] = gd->arch.resv_ram - base[0];
  195. else if (gd->arch.resv_ram >= base[1] &&
  196. gd->arch.resv_ram < base[1] + size[1])
  197. size[1] = gd->arch.resv_ram - base[1];
  198. #endif
  199. fdt_fixup_memory_banks(blob, base, size, 2);
  200. fdt_fixup_icid(blob);
  201. #ifdef CONFIG_FSL_ENETC
  202. fdt_fixup_enetc_mac(blob);
  203. #endif
  204. return 0;
  205. }
  206. #endif
  207. #ifdef CONFIG_FSL_QIXIS
  208. int checkboard(void)
  209. {
  210. #ifdef CONFIG_TFABOOT
  211. enum boot_src src = get_boot_src();
  212. #endif
  213. u8 sw;
  214. int clock;
  215. char *board;
  216. char buf[64] = {0};
  217. static const char *freq[6] = {"100.00", "125.00", "156.25",
  218. "161.13", "322.26", "100.00 SS"};
  219. cpu_name(buf);
  220. /* find the board details */
  221. sw = QIXIS_READ(id);
  222. switch (sw) {
  223. case 0x46:
  224. board = "QDS";
  225. break;
  226. case 0x47:
  227. board = "RDB";
  228. break;
  229. case 0x49:
  230. board = "HSSI";
  231. break;
  232. default:
  233. board = "unknown";
  234. break;
  235. }
  236. sw = QIXIS_READ(arch);
  237. printf("Board: %s-%s, Version: %c, boot from ",
  238. buf, board, (sw & 0xf) + 'A' - 1);
  239. sw = QIXIS_READ(brdcfg[0]);
  240. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  241. #ifdef CONFIG_TFABOOT
  242. if (src == BOOT_SOURCE_SD_MMC) {
  243. puts("SD\n");
  244. } else if (src == BOOT_SOURCE_SD_MMC2) {
  245. puts("eMMC\n");
  246. } else {
  247. #endif
  248. #ifdef CONFIG_SD_BOOT
  249. puts("SD\n");
  250. #elif defined(CONFIG_EMMC_BOOT)
  251. puts("eMMC\n");
  252. #else
  253. switch (sw) {
  254. case 0:
  255. case 4:
  256. printf("NOR\n");
  257. break;
  258. case 1:
  259. printf("NAND\n");
  260. break;
  261. default:
  262. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  263. break;
  264. }
  265. #endif
  266. #ifdef CONFIG_TFABOOT
  267. }
  268. #endif
  269. printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
  270. puts("SERDES1 Reference : ");
  271. sw = QIXIS_READ(brdcfg[2]);
  272. #ifdef CONFIG_TARGET_LS1028ARDB
  273. clock = (sw >> 6) & 3;
  274. #else
  275. clock = (sw >> 4) & 0xf;
  276. #endif
  277. printf("Clock1 = %sMHz ", freq[clock]);
  278. #ifdef CONFIG_TARGET_LS1028ARDB
  279. clock = (sw >> 4) & 3;
  280. #else
  281. clock = sw & 0xf;
  282. #endif
  283. printf("Clock2 = %sMHz\n", freq[clock]);
  284. return 0;
  285. }
  286. #endif