ls1021atwr.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <clock_legacy.h>
  8. #include <command.h>
  9. #include <fdt_support.h>
  10. #include <i2c.h>
  11. #include <init.h>
  12. #include <net.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/immap_ls102xa.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/fsl_serdes.h>
  18. #include <asm/arch/ls102xa_devdis.h>
  19. #include <asm/arch/ls102xa_soc.h>
  20. #include <hwconfig.h>
  21. #include <mmc.h>
  22. #include <fsl_csu.h>
  23. #include <fsl_ifc.h>
  24. #include <fsl_immap.h>
  25. #include <netdev.h>
  26. #include <fsl_mdio.h>
  27. #include <tsec.h>
  28. #include <fsl_sec.h>
  29. #include <fsl_devdis.h>
  30. #include <spl.h>
  31. #include <linux/delay.h>
  32. #include "../common/sleep.h"
  33. #ifdef CONFIG_U_QE
  34. #include <fsl_qe.h>
  35. #endif
  36. #include <fsl_validate.h>
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define VERSION_MASK 0x00FF
  39. #define BANK_MASK 0x0001
  40. #define CONFIG_RESET 0x1
  41. #define INIT_RESET 0x1
  42. #define CPLD_SET_MUX_SERDES 0x20
  43. #define CPLD_SET_BOOT_BANK 0x40
  44. #define BOOT_FROM_UPPER_BANK 0x0
  45. #define BOOT_FROM_LOWER_BANK 0x1
  46. #define LANEB_SATA (0x01)
  47. #define LANEB_SGMII1 (0x02)
  48. #define LANEC_SGMII1 (0x04)
  49. #define LANEC_PCIEX1 (0x08)
  50. #define LANED_PCIEX2 (0x10)
  51. #define LANED_SGMII2 (0x20)
  52. #define MASK_LANE_B 0x1
  53. #define MASK_LANE_C 0x2
  54. #define MASK_LANE_D 0x4
  55. #define MASK_SGMII 0x8
  56. #define KEEP_STATUS 0x0
  57. #define NEED_RESET 0x1
  58. #define SOFT_MUX_ON_I2C3_IFC 0x2
  59. #define SOFT_MUX_ON_CAN3_USB2 0x8
  60. #define SOFT_MUX_ON_QE_LCD 0x10
  61. #define PIN_I2C3_IFC_MUX_I2C3 0x0
  62. #define PIN_I2C3_IFC_MUX_IFC 0x1
  63. #define PIN_CAN3_USB2_MUX_USB2 0x0
  64. #define PIN_CAN3_USB2_MUX_CAN3 0x1
  65. #define PIN_QE_LCD_MUX_LCD 0x0
  66. #define PIN_QE_LCD_MUX_QE 0x1
  67. struct cpld_data {
  68. u8 cpld_ver; /* cpld revision */
  69. u8 cpld_ver_sub; /* cpld sub revision */
  70. u8 pcba_ver; /* pcb revision number */
  71. u8 system_rst; /* reset system by cpld */
  72. u8 soft_mux_on; /* CPLD override physical switches Enable */
  73. u8 cfg_rcw_src1; /* Reset config word 1 */
  74. u8 cfg_rcw_src2; /* Reset config word 2 */
  75. u8 vbank; /* Flash bank selection Control */
  76. u8 gpio; /* GPIO for TWR-ELEV */
  77. u8 i2c3_ifc_mux;
  78. u8 mux_spi2;
  79. u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
  80. u8 qe_lcd_mux; /* QE and LCD Selection */
  81. u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
  82. u8 global_rst; /* reset with init CPLD reg to default */
  83. u8 rev1; /* Reserved */
  84. u8 rev2; /* Reserved */
  85. };
  86. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  87. static void cpld_show(void)
  88. {
  89. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  90. printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
  91. in_8(&cpld_data->cpld_ver) & VERSION_MASK,
  92. in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
  93. in_8(&cpld_data->pcba_ver) & VERSION_MASK,
  94. in_8(&cpld_data->vbank) & BANK_MASK);
  95. #ifdef CONFIG_DEBUG
  96. printf("soft_mux_on =%x\n",
  97. in_8(&cpld_data->soft_mux_on));
  98. printf("cfg_rcw_src1 =%x\n",
  99. in_8(&cpld_data->cfg_rcw_src1));
  100. printf("cfg_rcw_src2 =%x\n",
  101. in_8(&cpld_data->cfg_rcw_src2));
  102. printf("vbank =%x\n",
  103. in_8(&cpld_data->vbank));
  104. printf("gpio =%x\n",
  105. in_8(&cpld_data->gpio));
  106. printf("i2c3_ifc_mux =%x\n",
  107. in_8(&cpld_data->i2c3_ifc_mux));
  108. printf("mux_spi2 =%x\n",
  109. in_8(&cpld_data->mux_spi2));
  110. printf("can3_usb2_mux =%x\n",
  111. in_8(&cpld_data->can3_usb2_mux));
  112. printf("qe_lcd_mux =%x\n",
  113. in_8(&cpld_data->qe_lcd_mux));
  114. printf("serdes_mux =%x\n",
  115. in_8(&cpld_data->serdes_mux));
  116. #endif
  117. }
  118. #endif
  119. int checkboard(void)
  120. {
  121. puts("Board: LS1021ATWR\n");
  122. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  123. cpld_show();
  124. #endif
  125. return 0;
  126. }
  127. void ddrmc_init(void)
  128. {
  129. struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  130. u32 temp_sdram_cfg, tmp;
  131. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  132. out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  133. out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  134. out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  135. out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  136. out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  137. out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  138. out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  139. out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  140. #ifdef CONFIG_DEEP_SLEEP
  141. if (is_warm_boot()) {
  142. out_be32(&ddr->sdram_cfg_2,
  143. DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  144. out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  145. out_be32(&ddr->init_ext_addr, (1 << 31));
  146. /* DRAM VRef will not be trained */
  147. out_be32(&ddr->ddr_cdr2,
  148. DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  149. } else
  150. #endif
  151. {
  152. out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  153. out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  154. }
  155. out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  156. out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  157. out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  158. out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  159. out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  160. out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  161. out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  162. out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  163. out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  164. out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  165. /* DDR erratum A-009942 */
  166. tmp = in_be32(&ddr->debug[28]);
  167. out_be32(&ddr->debug[28], tmp | 0x0070006f);
  168. udelay(1);
  169. #ifdef CONFIG_DEEP_SLEEP
  170. if (is_warm_boot()) {
  171. /* enter self-refresh */
  172. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  173. temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  174. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  175. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  176. } else
  177. #endif
  178. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  179. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  180. #ifdef CONFIG_DEEP_SLEEP
  181. if (is_warm_boot()) {
  182. /* exit self-refresh */
  183. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  184. temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  185. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  186. }
  187. #endif
  188. }
  189. int dram_init(void)
  190. {
  191. #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  192. ddrmc_init();
  193. #endif
  194. erratum_a008850_post();
  195. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  196. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  197. fsl_dp_resume();
  198. #endif
  199. return 0;
  200. }
  201. int board_eth_init(struct bd_info *bis)
  202. {
  203. return pci_eth_init(bis);
  204. }
  205. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  206. static void convert_serdes_mux(int type, int need_reset)
  207. {
  208. char current_serdes;
  209. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  210. current_serdes = cpld_data->serdes_mux;
  211. switch (type) {
  212. case LANEB_SATA:
  213. current_serdes &= ~MASK_LANE_B;
  214. break;
  215. case LANEB_SGMII1:
  216. current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
  217. break;
  218. case LANEC_SGMII1:
  219. current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
  220. break;
  221. case LANED_SGMII2:
  222. current_serdes |= MASK_LANE_D;
  223. break;
  224. case LANEC_PCIEX1:
  225. current_serdes |= MASK_LANE_C;
  226. break;
  227. case (LANED_PCIEX2 | LANEC_PCIEX1):
  228. current_serdes |= MASK_LANE_C;
  229. current_serdes &= ~MASK_LANE_D;
  230. break;
  231. default:
  232. printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
  233. return;
  234. }
  235. cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
  236. cpld_data->serdes_mux = current_serdes;
  237. if (need_reset == 1) {
  238. printf("Reset board to enable configuration\n");
  239. cpld_data->system_rst = CONFIG_RESET;
  240. }
  241. }
  242. int config_serdes_mux(void)
  243. {
  244. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  245. u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
  246. protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
  247. switch (protocol) {
  248. case 0x10:
  249. convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
  250. convert_serdes_mux(LANED_PCIEX2 |
  251. LANEC_PCIEX1, KEEP_STATUS);
  252. break;
  253. case 0x20:
  254. convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
  255. convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
  256. convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
  257. break;
  258. case 0x30:
  259. convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
  260. convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
  261. convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
  262. break;
  263. case 0x70:
  264. convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
  265. convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
  266. convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
  267. break;
  268. }
  269. return 0;
  270. }
  271. #endif
  272. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  273. int config_board_mux(void)
  274. {
  275. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  276. int conflict_flag;
  277. conflict_flag = 0;
  278. if (hwconfig("i2c3")) {
  279. conflict_flag++;
  280. cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
  281. cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
  282. }
  283. if (hwconfig("ifc")) {
  284. conflict_flag++;
  285. /* some signals can not enable simultaneous*/
  286. if (conflict_flag > 1)
  287. goto conflict;
  288. cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
  289. cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
  290. }
  291. conflict_flag = 0;
  292. if (hwconfig("usb2")) {
  293. conflict_flag++;
  294. cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
  295. cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
  296. }
  297. if (hwconfig("can3")) {
  298. conflict_flag++;
  299. /* some signals can not enable simultaneous*/
  300. if (conflict_flag > 1)
  301. goto conflict;
  302. cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
  303. cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
  304. }
  305. conflict_flag = 0;
  306. if (hwconfig("lcd")) {
  307. conflict_flag++;
  308. cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
  309. cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
  310. }
  311. if (hwconfig("qe")) {
  312. conflict_flag++;
  313. /* some signals can not enable simultaneous*/
  314. if (conflict_flag > 1)
  315. goto conflict;
  316. cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
  317. cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
  318. }
  319. return 0;
  320. conflict:
  321. printf("WARNING: pin conflict! MUX setting may failed!\n");
  322. return 0;
  323. }
  324. #endif
  325. int board_early_init_f(void)
  326. {
  327. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  328. #ifdef CONFIG_TSEC_ENET
  329. /* clear BD & FR bits for BE BD's and frame data */
  330. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  331. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  332. #endif
  333. #ifdef CONFIG_FSL_IFC
  334. init_early_memctl_regs();
  335. #endif
  336. arch_soc_init();
  337. #if defined(CONFIG_DEEP_SLEEP)
  338. if (is_warm_boot()) {
  339. timer_init();
  340. dram_init();
  341. }
  342. #endif
  343. return 0;
  344. }
  345. #ifdef CONFIG_SPL_BUILD
  346. void board_init_f(ulong dummy)
  347. {
  348. void (*second_uboot)(void);
  349. /* Clear the BSS */
  350. memset(__bss_start, 0, __bss_end - __bss_start);
  351. get_clocks();
  352. #if defined(CONFIG_DEEP_SLEEP)
  353. if (is_warm_boot())
  354. fsl_dp_disable_console();
  355. #endif
  356. preloader_console_init();
  357. timer_init();
  358. dram_init();
  359. /* Allow OCRAM access permission as R/W */
  360. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  361. enable_layerscape_ns_access();
  362. #endif
  363. /*
  364. * if it is woken up from deep sleep, then jump to second
  365. * stage uboot and continue executing without recopying
  366. * it from SD since it has already been reserved in memeory
  367. * in last boot.
  368. */
  369. if (is_warm_boot()) {
  370. second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
  371. second_uboot();
  372. }
  373. board_init_r(NULL, 0);
  374. }
  375. #endif
  376. #ifdef CONFIG_DEEP_SLEEP
  377. /* program the regulator (MC34VR500) to support deep sleep */
  378. void ls1twr_program_regulator(void)
  379. {
  380. u8 i2c_device_id;
  381. #define LS1TWR_I2C_BUS_MC34VR500 1
  382. #define MC34VR500_ADDR 0x8
  383. #define MC34VR500_DEVICEID 0x4
  384. #define MC34VR500_DEVICEID_MASK 0x0f
  385. #if CONFIG_IS_ENABLED(DM_I2C)
  386. struct udevice *dev;
  387. int ret;
  388. ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
  389. 1, &dev);
  390. if (ret) {
  391. printf("%s: Cannot find udev for a bus %d\n", __func__,
  392. LS1TWR_I2C_BUS_MC34VR500);
  393. return;
  394. }
  395. i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
  396. MC34VR500_DEVICEID_MASK;
  397. if (i2c_device_id != MC34VR500_DEVICEID) {
  398. printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
  399. return;
  400. }
  401. dm_i2c_reg_write(dev, 0x31, 0x4);
  402. dm_i2c_reg_write(dev, 0x4d, 0x4);
  403. dm_i2c_reg_write(dev, 0x6d, 0x38);
  404. dm_i2c_reg_write(dev, 0x6f, 0x37);
  405. dm_i2c_reg_write(dev, 0x71, 0x30);
  406. #else
  407. unsigned int i2c_bus;
  408. i2c_bus = i2c_get_bus_num();
  409. i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
  410. i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
  411. MC34VR500_DEVICEID_MASK;
  412. if (i2c_device_id != MC34VR500_DEVICEID) {
  413. printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
  414. return;
  415. }
  416. i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
  417. i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
  418. i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
  419. i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
  420. i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
  421. i2c_set_bus_num(i2c_bus);
  422. #endif
  423. }
  424. #endif
  425. int board_init(void)
  426. {
  427. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  428. erratum_a010315();
  429. #endif
  430. #ifndef CONFIG_SYS_FSL_NO_SERDES
  431. fsl_serdes_init();
  432. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  433. config_serdes_mux();
  434. #endif
  435. #endif
  436. ls102xa_smmu_stream_id_init();
  437. #ifdef CONFIG_U_QE
  438. u_qe_init();
  439. #endif
  440. #ifdef CONFIG_DEEP_SLEEP
  441. ls1twr_program_regulator();
  442. #endif
  443. return 0;
  444. }
  445. #if defined(CONFIG_SPL_BUILD)
  446. void spl_board_init(void)
  447. {
  448. ls102xa_smmu_stream_id_init();
  449. }
  450. #endif
  451. #ifdef CONFIG_BOARD_LATE_INIT
  452. int board_late_init(void)
  453. {
  454. #ifdef CONFIG_CHAIN_OF_TRUST
  455. fsl_setenv_chain_of_trust();
  456. #endif
  457. return 0;
  458. }
  459. #endif
  460. #if defined(CONFIG_MISC_INIT_R)
  461. int misc_init_r(void)
  462. {
  463. #ifdef CONFIG_FSL_DEVICE_DISABLE
  464. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  465. #endif
  466. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  467. config_board_mux();
  468. #endif
  469. #ifdef CONFIG_FSL_CAAM
  470. return sec_init();
  471. #endif
  472. }
  473. #endif
  474. #if defined(CONFIG_DEEP_SLEEP)
  475. void board_sleep_prepare(void)
  476. {
  477. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  478. enable_layerscape_ns_access();
  479. #endif
  480. }
  481. #endif
  482. int ft_board_setup(void *blob, struct bd_info *bd)
  483. {
  484. ft_cpu_setup(blob, bd);
  485. #ifdef CONFIG_PCI
  486. ft_pci_setup(blob, bd);
  487. #endif
  488. return 0;
  489. }
  490. u8 flash_read8(void *addr)
  491. {
  492. return __raw_readb(addr + 1);
  493. }
  494. void flash_write16(u16 val, void *addr)
  495. {
  496. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  497. __raw_writew(shftval, addr);
  498. }
  499. u16 flash_read16(void *addr)
  500. {
  501. u16 val = __raw_readw(addr);
  502. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  503. }
  504. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
  505. && !defined(CONFIG_SPL_BUILD)
  506. static void convert_flash_bank(char bank)
  507. {
  508. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  509. printf("Now switch to boot from flash bank %d.\n", bank);
  510. cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
  511. cpld_data->vbank = bank;
  512. printf("Reset board to enable configuration.\n");
  513. cpld_data->system_rst = CONFIG_RESET;
  514. }
  515. static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  516. char *const argv[])
  517. {
  518. if (argc != 2)
  519. return CMD_RET_USAGE;
  520. if (strcmp(argv[1], "0") == 0)
  521. convert_flash_bank(BOOT_FROM_UPPER_BANK);
  522. else if (strcmp(argv[1], "1") == 0)
  523. convert_flash_bank(BOOT_FROM_LOWER_BANK);
  524. else
  525. return CMD_RET_USAGE;
  526. return 0;
  527. }
  528. U_BOOT_CMD(
  529. boot_bank, 2, 0, flash_bank_cmd,
  530. "Flash bank Selection Control",
  531. "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
  532. );
  533. static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  534. char *const argv[])
  535. {
  536. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  537. if (argc > 2)
  538. return CMD_RET_USAGE;
  539. if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
  540. cpld_data->system_rst = CONFIG_RESET;
  541. else if (strcmp(argv[1], "init") == 0)
  542. cpld_data->global_rst = INIT_RESET;
  543. else
  544. return CMD_RET_USAGE;
  545. return 0;
  546. }
  547. U_BOOT_CMD(
  548. cpld_reset, 2, 0, cpld_reset_cmd,
  549. "Reset via CPLD",
  550. "conf\n"
  551. " -reset with current CPLD configuration\n"
  552. "init\n"
  553. " -reset and initial CPLD configuration with default value"
  554. );
  555. static void print_serdes_mux(void)
  556. {
  557. char current_serdes;
  558. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  559. current_serdes = cpld_data->serdes_mux;
  560. printf("Serdes Lane B: ");
  561. if ((current_serdes & MASK_LANE_B) == 0)
  562. printf("SATA,\n");
  563. else
  564. printf("SGMII 1,\n");
  565. printf("Serdes Lane C: ");
  566. if ((current_serdes & MASK_LANE_C) == 0)
  567. printf("SGMII 1,\n");
  568. else
  569. printf("PCIe,\n");
  570. printf("Serdes Lane D: ");
  571. if ((current_serdes & MASK_LANE_D) == 0)
  572. printf("PCIe,\n");
  573. else
  574. printf("SGMII 2,\n");
  575. printf("SGMII 1 is on lane ");
  576. if ((current_serdes & MASK_SGMII) == 0)
  577. printf("C.\n");
  578. else
  579. printf("B.\n");
  580. }
  581. static int serdes_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  582. char *const argv[])
  583. {
  584. if (argc != 2)
  585. return CMD_RET_USAGE;
  586. if (strcmp(argv[1], "sata") == 0) {
  587. printf("Set serdes lane B to SATA.\n");
  588. convert_serdes_mux(LANEB_SATA, NEED_RESET);
  589. } else if (strcmp(argv[1], "sgmii1b") == 0) {
  590. printf("Set serdes lane B to SGMII 1.\n");
  591. convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
  592. } else if (strcmp(argv[1], "sgmii1c") == 0) {
  593. printf("Set serdes lane C to SGMII 1.\n");
  594. convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
  595. } else if (strcmp(argv[1], "sgmii2") == 0) {
  596. printf("Set serdes lane D to SGMII 2.\n");
  597. convert_serdes_mux(LANED_SGMII2, NEED_RESET);
  598. } else if (strcmp(argv[1], "pciex1") == 0) {
  599. printf("Set serdes lane C to PCIe X1.\n");
  600. convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
  601. } else if (strcmp(argv[1], "pciex2") == 0) {
  602. printf("Set serdes lane C & lane D to PCIe X2.\n");
  603. convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
  604. } else if (strcmp(argv[1], "show") == 0) {
  605. print_serdes_mux();
  606. } else {
  607. return CMD_RET_USAGE;
  608. }
  609. return 0;
  610. }
  611. U_BOOT_CMD(
  612. lane_bank, 2, 0, serdes_mux_cmd,
  613. "Multiplexed function setting for SerDes Lanes",
  614. "sata\n"
  615. " -change lane B to sata\n"
  616. "lane_bank sgmii1b\n"
  617. " -change lane B to SGMII1\n"
  618. "lane_bank sgmii1c\n"
  619. " -change lane C to SGMII1\n"
  620. "lane_bank sgmii2\n"
  621. " -change lane D to SGMII2\n"
  622. "lane_bank pciex1\n"
  623. " -change lane C to PCIeX1\n"
  624. "lane_bank pciex2\n"
  625. " -change lane C & lane D to PCIeX2\n"
  626. "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
  627. );
  628. #endif