dcu.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. *
  6. * FSL DCU Framebuffer driver
  7. */
  8. #include <asm/global_data.h>
  9. #include <asm/io.h>
  10. #include <common.h>
  11. #include <fsl_dcu_fb.h>
  12. #include <i2c.h>
  13. #include "div64.h"
  14. #include "../common/diu_ch7301.h"
  15. #include "ls1021aqds_qixis.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. static int select_i2c_ch_pca9547(u8 ch, int bus_num)
  18. {
  19. int ret;
  20. #if CONFIG_IS_ENABLED(DM_I2C)
  21. struct udevice *dev;
  22. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  23. 1, &dev);
  24. if (ret) {
  25. printf("%s: Cannot find udev for a bus %d\n", __func__,
  26. bus_num);
  27. return ret;
  28. }
  29. ret = dm_i2c_write(dev, 0, &ch, 1);
  30. #else
  31. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  32. #endif
  33. if (ret) {
  34. puts("PCA: failed to select proper channel\n");
  35. return ret;
  36. }
  37. return 0;
  38. }
  39. unsigned int dcu_set_pixel_clock(unsigned int pixclock)
  40. {
  41. unsigned long long div;
  42. div = (unsigned long long)(gd->bus_clk / 1000);
  43. div *= (unsigned long long)pixclock;
  44. do_div(div, 1000000000);
  45. return div;
  46. }
  47. int platform_dcu_init(struct fb_info *fbinfo,
  48. unsigned int xres,
  49. unsigned int yres,
  50. const char *port,
  51. struct fb_videomode *dcu_fb_videomode)
  52. {
  53. const char *name;
  54. unsigned int pixel_format;
  55. int ret;
  56. u8 ch;
  57. /* Mux I2C3+I2C4 as HSYNC+VSYNC */
  58. #if CONFIG_IS_ENABLED(DM_I2C)
  59. struct udevice *dev;
  60. /* QIXIS device mount on I2C1 bus*/
  61. ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR,
  62. 1, &dev);
  63. if (ret) {
  64. printf("%s: Cannot find udev for a bus %d\n", __func__,
  65. 0);
  66. return ret;
  67. }
  68. ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
  69. if (ret) {
  70. printf("Error: failed to read I2C @%02x\n",
  71. CONFIG_SYS_I2C_QIXIS_ADDR);
  72. return ret;
  73. }
  74. ch &= 0x1F;
  75. ch |= 0xA0;
  76. ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
  77. #else
  78. ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
  79. 1, &ch, 1);
  80. if (ret) {
  81. printf("Error: failed to read I2C @%02x\n",
  82. CONFIG_SYS_I2C_QIXIS_ADDR);
  83. return ret;
  84. }
  85. ch &= 0x1F;
  86. ch |= 0xA0;
  87. ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
  88. 1, &ch, 1);
  89. #endif
  90. if (ret) {
  91. printf("Error: failed to write I2C @%02x\n",
  92. CONFIG_SYS_I2C_QIXIS_ADDR);
  93. return ret;
  94. }
  95. if (strncmp(port, "hdmi", 4) == 0) {
  96. unsigned long pixval;
  97. name = "HDMI";
  98. pixval = 1000000000 / dcu_fb_videomode->pixclock;
  99. pixval *= 1000;
  100. #if !CONFIG_IS_ENABLED(DM_I2C)
  101. i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
  102. #endif
  103. select_i2c_ch_pca9547(I2C_MUX_CH_CH7301,
  104. CONFIG_SYS_I2C_DVI_BUS_NUM);
  105. diu_set_dvi_encoder(pixval);
  106. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT,
  107. CONFIG_SYS_I2C_DVI_BUS_NUM);
  108. } else {
  109. return 0;
  110. }
  111. printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
  112. pixel_format = 32;
  113. fsl_dcu_init(fbinfo, xres, yres, pixel_format);
  114. return 0;
  115. }