ls1012ardb.c 9.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <fdt_support.h>
  8. #include <hang.h>
  9. #include <i2c.h>
  10. #include <asm/cache.h>
  11. #include <init.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #ifdef CONFIG_FSL_LS_PPA
  17. #include <asm/arch/ppa.h>
  18. #endif
  19. #include <asm/arch/mmu.h>
  20. #include <asm/arch/soc.h>
  21. #include <hwconfig.h>
  22. #include <ahci.h>
  23. #include <mmc.h>
  24. #include <scsi.h>
  25. #include <fsl_esdhc.h>
  26. #include <env_internal.h>
  27. #include <fsl_mmdc.h>
  28. #include <netdev.h>
  29. #include <fsl_sec.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define BOOT_FROM_UPPER_BANK 0x2
  32. #define BOOT_FROM_LOWER_BANK 0x1
  33. int checkboard(void)
  34. {
  35. #ifdef CONFIG_TARGET_LS1012ARDB
  36. u8 in1;
  37. int ret, bus_num = 0;
  38. puts("Board: LS1012ARDB ");
  39. /* Initialize i2c early for Serial flash bank information */
  40. #if CONFIG_IS_ENABLED(DM_I2C)
  41. struct udevice *dev;
  42. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
  43. 1, &dev);
  44. if (ret) {
  45. printf("%s: Cannot find udev for a bus %d\n", __func__,
  46. bus_num);
  47. return -ENXIO;
  48. }
  49. ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
  50. #else /* Non DM I2C support - will be removed */
  51. i2c_set_bus_num(bus_num);
  52. ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
  53. #endif
  54. if (ret < 0) {
  55. printf("Error reading i2c boot information!\n");
  56. return 0; /* Don't want to hang() on this error */
  57. }
  58. puts("Version");
  59. switch (in1 & SW_REV_MASK) {
  60. case SW_REV_A:
  61. puts(": RevA");
  62. break;
  63. case SW_REV_B:
  64. puts(": RevB");
  65. break;
  66. case SW_REV_C:
  67. puts(": RevC");
  68. break;
  69. case SW_REV_C1:
  70. puts(": RevC1");
  71. break;
  72. case SW_REV_C2:
  73. puts(": RevC2");
  74. break;
  75. case SW_REV_D:
  76. puts(": RevD");
  77. break;
  78. case SW_REV_E:
  79. puts(": RevE");
  80. break;
  81. default:
  82. puts(": unknown");
  83. break;
  84. }
  85. printf(", boot from QSPI");
  86. if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
  87. puts(": emu\n");
  88. else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
  89. puts(": bank1\n");
  90. else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
  91. puts(": bank2\n");
  92. else
  93. puts("unknown\n");
  94. #else
  95. puts("Board: LS1012A2G5RDB ");
  96. #endif
  97. return 0;
  98. }
  99. #ifdef CONFIG_TFABOOT
  100. int dram_init(void)
  101. {
  102. gd->ram_size = tfa_get_dram_size();
  103. if (!gd->ram_size)
  104. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  105. return 0;
  106. }
  107. #else
  108. int dram_init(void)
  109. {
  110. #ifndef CONFIG_TFABOOT
  111. static const struct fsl_mmdc_info mparam = {
  112. 0x05180000, /* mdctl */
  113. 0x00030035, /* mdpdc */
  114. 0x12554000, /* mdotc */
  115. 0xbabf7954, /* mdcfg0 */
  116. 0xdb328f64, /* mdcfg1 */
  117. 0x01ff00db, /* mdcfg2 */
  118. 0x00001680, /* mdmisc */
  119. 0x0f3c8000, /* mdref */
  120. 0x00002000, /* mdrwd */
  121. 0x00bf1023, /* mdor */
  122. 0x0000003f, /* mdasp */
  123. 0x0000022a, /* mpodtctrl */
  124. 0xa1390003, /* mpzqhwctrl */
  125. };
  126. mmdc_init(&mparam);
  127. #endif
  128. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  129. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  130. /* This will break-before-make MMU for DDR */
  131. update_early_mmu_table();
  132. #endif
  133. return 0;
  134. }
  135. #endif
  136. int board_early_init_f(void)
  137. {
  138. fsl_lsch2_early_init_f();
  139. return 0;
  140. }
  141. int board_init(void)
  142. {
  143. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  144. CONFIG_SYS_CCI400_OFFSET);
  145. /*
  146. * Set CCI-400 control override register to enable barrier
  147. * transaction
  148. */
  149. if (current_el() == 3)
  150. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  151. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  152. erratum_a010315();
  153. #endif
  154. #ifdef CONFIG_ENV_IS_NOWHERE
  155. gd->env_addr = (ulong)&default_environment[0];
  156. #endif
  157. #ifdef CONFIG_FSL_CAAM
  158. sec_init();
  159. #endif
  160. #ifdef CONFIG_FSL_LS_PPA
  161. ppa_init();
  162. #endif
  163. return 0;
  164. }
  165. #ifdef CONFIG_TARGET_LS1012ARDB
  166. int esdhc_status_fixup(void *blob, const char *compat)
  167. {
  168. char esdhc1_path[] = "/soc/esdhc@1580000";
  169. bool sdhc2_en = false;
  170. u8 mux_sdhc2;
  171. u8 io = 0;
  172. int ret, bus_num = 0;
  173. #if CONFIG_IS_ENABLED(DM_I2C)
  174. struct udevice *dev;
  175. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
  176. 1, &dev);
  177. if (ret) {
  178. printf("%s: Cannot find udev for a bus %d\n", __func__,
  179. bus_num);
  180. return -ENXIO;
  181. }
  182. ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
  183. #else
  184. i2c_set_bus_num(bus_num);
  185. /* IO1[7:3] is the field of board revision info. */
  186. ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
  187. #endif
  188. if (ret < 0) {
  189. printf("Error reading i2c boot information!\n");
  190. return 0;
  191. }
  192. /* hwconfig method is used for RevD and later versions. */
  193. if ((io & SW_REV_MASK) <= SW_REV_D) {
  194. #ifdef CONFIG_HWCONFIG
  195. if (hwconfig("esdhc1"))
  196. sdhc2_en = true;
  197. #endif
  198. } else {
  199. /*
  200. * The I2C IO-expander for mux select is used to control
  201. * the muxing of various onboard interfaces.
  202. *
  203. * IO0[3:2] indicates SDHC2 interface demultiplexer
  204. * select lines.
  205. * 00 - SDIO wifi
  206. * 01 - GPIO (to Arduino)
  207. * 10 - eMMC Memory
  208. * 11 - SPI
  209. */
  210. #if CONFIG_IS_ENABLED(DM_I2C)
  211. ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
  212. #else
  213. ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
  214. #endif
  215. if (ret < 0) {
  216. printf("Error reading i2c boot information!\n");
  217. return 0;
  218. }
  219. mux_sdhc2 = (io & 0x0c) >> 2;
  220. /* Enable SDHC2 only when use SDIO wifi and eMMC */
  221. if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
  222. sdhc2_en = true;
  223. }
  224. if (sdhc2_en)
  225. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  226. sizeof("okay"), 1);
  227. else
  228. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  229. sizeof("disabled"), 1);
  230. return 0;
  231. }
  232. #endif
  233. int ft_board_setup(void *blob, struct bd_info *bd)
  234. {
  235. arch_fixup_fdt(blob);
  236. ft_cpu_setup(blob, bd);
  237. return 0;
  238. }
  239. static int switch_to_bank1(void)
  240. {
  241. u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
  242. int ret, bus_num = 0;
  243. #if CONFIG_IS_ENABLED(DM_I2C)
  244. struct udevice *dev;
  245. ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
  246. 1, &dev);
  247. if (ret) {
  248. printf("%s: Cannot find udev for a bus %d\n", __func__,
  249. bus_num);
  250. return -ENXIO;
  251. }
  252. /*
  253. * --------------------------------------------------------------------
  254. * |bus |I2C address| Device | Notes |
  255. * --------------------------------------------------------------------
  256. * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General |
  257. * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output|
  258. * | | | KW41GPIO) - NXP | (GPIO) expansion for the |
  259. * | | | PCAL9555AHF | I2C bus |
  260. * ----- --------------------------------------------------------------
  261. * - mount three IO expander(PCAL9555AHF) on I2C1
  262. *
  263. * PCAL9555A device address
  264. * slave address
  265. * --------------------------------------
  266. * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
  267. * --------------------------------------
  268. * | fixed | hardware selectable|
  269. *
  270. * Output port 1(Pinter register bits = 0x03)
  271. *
  272. * P1_[7~0] = 0xf4
  273. * P1_0 <---> CFG_MUX_QSPI_S0
  274. * P1_1 <---> CFG_MUX_QSPI_S1
  275. * CFG_MUX_QSPI_S[1:0] = 0b00
  276. *
  277. * QSPI chip-select demultiplexer select
  278. * ---------------------------------------------------------------------
  279. * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values
  280. * ---------------------------------------------------------------------
  281. * 0 | 0 |CS routed to SPI memory bank1(default)
  282. * ---------------------------------------------------------------------
  283. * 0 | 1 |CS routed to SPI memory bank2
  284. * ---------------------------------------------------------------------
  285. *
  286. */
  287. ret = dm_i2c_write(dev, offset_addr, &data, 1);
  288. #else /* Non DM I2C support - will be removed */
  289. i2c_set_bus_num(bus_num);
  290. ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
  291. #endif
  292. if (ret) {
  293. printf("i2c write error to chip : %u, addr : %u, data : %u\n",
  294. chip_addr, offset_addr, data);
  295. }
  296. return ret;
  297. }
  298. static int switch_to_bank2(void)
  299. {
  300. u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
  301. u8 chip_addr = 0x24;
  302. int ret, i, bus_num = 0;
  303. #if CONFIG_IS_ENABLED(DM_I2C)
  304. struct udevice *dev;
  305. ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
  306. 1, &dev);
  307. if (ret) {
  308. printf("%s: Cannot find udev for a bus %d\n", __func__,
  309. bus_num);
  310. return -ENXIO;
  311. }
  312. #else /* Non DM I2C support - will be removed */
  313. i2c_set_bus_num(bus_num);
  314. #endif
  315. /*
  316. * 1th step: config port 1
  317. * - the port 1 pin is enabled as an output
  318. * 2th step: output port 1
  319. * - P1_[7:0] output 0xf5,
  320. * then CFG_MUX_QSPI_S[1:0] equal to 0b01,
  321. * CS routed to SPI memory bank2
  322. */
  323. for (i = 0; i < sizeof(data); i++) {
  324. #if CONFIG_IS_ENABLED(DM_I2C)
  325. ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
  326. #else /* Non DM I2C support - will be removed */
  327. ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
  328. #endif
  329. if (ret) {
  330. printf("i2c write error to chip : %u, addr : %u, data : %u\n",
  331. chip_addr, offset_addr[i], data[i]);
  332. goto err;
  333. }
  334. }
  335. err:
  336. return ret;
  337. }
  338. static int convert_flash_bank(int bank)
  339. {
  340. int ret = 0;
  341. switch (bank) {
  342. case BOOT_FROM_UPPER_BANK:
  343. ret = switch_to_bank2();
  344. break;
  345. case BOOT_FROM_LOWER_BANK:
  346. ret = switch_to_bank1();
  347. break;
  348. default:
  349. ret = CMD_RET_USAGE;
  350. break;
  351. };
  352. return ret;
  353. }
  354. static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  355. char *const argv[])
  356. {
  357. if (argc != 2)
  358. return CMD_RET_USAGE;
  359. if (strcmp(argv[1], "1") == 0)
  360. convert_flash_bank(BOOT_FROM_LOWER_BANK);
  361. else if (strcmp(argv[1], "2") == 0)
  362. convert_flash_bank(BOOT_FROM_UPPER_BANK);
  363. else
  364. return CMD_RET_USAGE;
  365. return 0;
  366. }
  367. U_BOOT_CMD(
  368. boot_bank, 2, 0, flash_bank_cmd,
  369. "Flash bank Selection Control",
  370. "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
  371. );