qixis.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011 Freescale Semiconductor
  4. * Copyright 2020 NXP
  5. * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
  6. *
  7. * This file provides support for the QIXIS of some Freescale reference boards.
  8. */
  9. #include <common.h>
  10. #include <command.h>
  11. #include <asm/io.h>
  12. #include <linux/compiler.h>
  13. #include <linux/time.h>
  14. #include <i2c.h>
  15. #include "qixis.h"
  16. #ifndef QIXIS_LBMAP_BRDCFG_REG
  17. /*
  18. * For consistency with existing platforms
  19. */
  20. #define QIXIS_LBMAP_BRDCFG_REG 0x00
  21. #endif
  22. #ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE
  23. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  24. #endif
  25. #ifndef QIXIS_RCFG_CTL_RECONFIG_START
  26. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  27. #endif
  28. #ifdef CONFIG_SYS_I2C_FPGA_ADDR
  29. u8 qixis_read_i2c(unsigned int reg)
  30. {
  31. #if !CONFIG_IS_ENABLED(DM_I2C)
  32. return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
  33. #else
  34. struct udevice *dev;
  35. if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
  36. return 0xff;
  37. return dm_i2c_reg_read(dev, reg);
  38. #endif
  39. }
  40. void qixis_write_i2c(unsigned int reg, u8 value)
  41. {
  42. u8 val = value;
  43. #if !CONFIG_IS_ENABLED(DM_I2C)
  44. i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
  45. #else
  46. struct udevice *dev;
  47. if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
  48. dm_i2c_reg_write(dev, reg, val);
  49. #endif
  50. }
  51. #endif
  52. #ifdef QIXIS_BASE
  53. u8 qixis_read(unsigned int reg)
  54. {
  55. void *p = (void *)QIXIS_BASE;
  56. return in_8(p + reg);
  57. }
  58. void qixis_write(unsigned int reg, u8 value)
  59. {
  60. void *p = (void *)QIXIS_BASE;
  61. out_8(p + reg, value);
  62. }
  63. #endif
  64. u16 qixis_read_minor(void)
  65. {
  66. u16 minor;
  67. /* this data is in little endian */
  68. QIXIS_WRITE(tagdata, 5);
  69. minor = QIXIS_READ(tagdata);
  70. QIXIS_WRITE(tagdata, 6);
  71. minor += QIXIS_READ(tagdata) << 8;
  72. return minor;
  73. }
  74. char *qixis_read_time(char *result)
  75. {
  76. time_t time = 0;
  77. int i;
  78. /* timestamp is in 32-bit big endian */
  79. for (i = 8; i <= 11; i++) {
  80. QIXIS_WRITE(tagdata, i);
  81. time = (time << 8) + QIXIS_READ(tagdata);
  82. }
  83. return ctime_r(&time, result);
  84. }
  85. char *qixis_read_tag(char *buf)
  86. {
  87. int i;
  88. char tag, *ptr = buf;
  89. for (i = 16; i <= 63; i++) {
  90. QIXIS_WRITE(tagdata, i);
  91. tag = QIXIS_READ(tagdata);
  92. *(ptr++) = tag;
  93. if (!tag)
  94. break;
  95. }
  96. if (i > 63)
  97. *ptr = '\0';
  98. return buf;
  99. }
  100. /*
  101. * return the string of binary of u8 in the format of
  102. * 1010 10_0. The masked bit is filled as underscore.
  103. */
  104. const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
  105. {
  106. char *ptr;
  107. int i;
  108. ptr = buf;
  109. for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
  110. *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
  111. *(ptr++) = ' ';
  112. for (i = 0x08; i > 0 ; i >>= 1, ptr++)
  113. *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
  114. *ptr = '\0';
  115. return buf;
  116. }
  117. #ifdef QIXIS_RST_FORCE_MEM
  118. void board_assert_mem_reset(void)
  119. {
  120. u8 rst;
  121. rst = QIXIS_READ(rst_frc[0]);
  122. if (!(rst & QIXIS_RST_FORCE_MEM))
  123. QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
  124. }
  125. void board_deassert_mem_reset(void)
  126. {
  127. u8 rst;
  128. rst = QIXIS_READ(rst_frc[0]);
  129. if (rst & QIXIS_RST_FORCE_MEM)
  130. QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
  131. }
  132. #endif
  133. #ifndef CONFIG_SPL_BUILD
  134. static void qixis_reset(void)
  135. {
  136. QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
  137. }
  138. #ifdef QIXIS_LBMAP_ALTBANK
  139. static void qixis_bank_reset(void)
  140. {
  141. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
  142. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
  143. }
  144. #endif
  145. static void __maybe_unused set_lbmap(int lbmap)
  146. {
  147. u8 reg;
  148. reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
  149. reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
  150. QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
  151. }
  152. static void __maybe_unused set_rcw_src(int rcw_src)
  153. {
  154. #ifdef CONFIG_NXP_LSCH3_2
  155. QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff));
  156. #else
  157. u8 reg;
  158. reg = QIXIS_READ(dutcfg[1]);
  159. reg = (reg & ~1) | (rcw_src & 1);
  160. QIXIS_WRITE(dutcfg[1], reg);
  161. QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
  162. #endif
  163. }
  164. static void qixis_dump_regs(void)
  165. {
  166. int i;
  167. printf("id = %02x\n", QIXIS_READ(id));
  168. printf("arch = %02x\n", QIXIS_READ(arch));
  169. printf("scver = %02x\n", QIXIS_READ(scver));
  170. printf("model = %02x\n", QIXIS_READ(model));
  171. printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
  172. printf("aux = %02x\n", QIXIS_READ(aux));
  173. for (i = 0; i < 16; i++)
  174. printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
  175. for (i = 0; i < 16; i++)
  176. printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
  177. printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
  178. QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
  179. printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
  180. QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
  181. printf("aux = %02x\n", QIXIS_READ(aux));
  182. printf("watch = %02x\n", QIXIS_READ(watch));
  183. printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
  184. printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
  185. printf("present = %02x\n", QIXIS_READ(present));
  186. printf("present2 = %02x\n", QIXIS_READ(present2));
  187. printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
  188. printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
  189. printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
  190. printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
  191. }
  192. void __weak qixis_dump_switch(void)
  193. {
  194. puts("Reverse engineering switch is not implemented for this board\n");
  195. }
  196. static int qixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  197. char *const argv[])
  198. {
  199. int i;
  200. if (argc <= 1) {
  201. set_lbmap(QIXIS_LBMAP_DFLTBANK);
  202. qixis_reset();
  203. } else if (strcmp(argv[1], "altbank") == 0) {
  204. #ifdef QIXIS_LBMAP_ALTBANK
  205. set_lbmap(QIXIS_LBMAP_ALTBANK);
  206. qixis_bank_reset();
  207. #else
  208. printf("No Altbank!\n");
  209. #endif
  210. } else if (strcmp(argv[1], "nand") == 0) {
  211. #ifdef QIXIS_LBMAP_NAND
  212. QIXIS_WRITE(rst_ctl, 0x30);
  213. QIXIS_WRITE(rcfg_ctl, 0);
  214. set_lbmap(QIXIS_LBMAP_NAND);
  215. set_rcw_src(QIXIS_RCW_SRC_NAND);
  216. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
  217. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
  218. #else
  219. printf("Not implemented\n");
  220. #endif
  221. } else if (strcmp(argv[1], "sd") == 0) {
  222. #ifdef QIXIS_LBMAP_SD
  223. QIXIS_WRITE(rst_ctl, 0x30);
  224. QIXIS_WRITE(rcfg_ctl, 0);
  225. #ifdef NON_EXTENDED_DUTCFG
  226. QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD);
  227. #else
  228. set_lbmap(QIXIS_LBMAP_SD);
  229. set_rcw_src(QIXIS_RCW_SRC_SD);
  230. #endif
  231. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
  232. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
  233. #else
  234. printf("Not implemented\n");
  235. #endif
  236. } else if (strcmp(argv[1], "ifc") == 0) {
  237. #ifdef QIXIS_LBMAP_IFC
  238. QIXIS_WRITE(rst_ctl, 0x30);
  239. QIXIS_WRITE(rcfg_ctl, 0);
  240. set_lbmap(QIXIS_LBMAP_IFC);
  241. set_rcw_src(QIXIS_RCW_SRC_IFC);
  242. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
  243. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
  244. #else
  245. printf("Not implemented\n");
  246. #endif
  247. } else if (strcmp(argv[1], "emmc") == 0) {
  248. #ifdef QIXIS_LBMAP_EMMC
  249. QIXIS_WRITE(rst_ctl, 0x30);
  250. QIXIS_WRITE(rcfg_ctl, 0);
  251. #ifndef NON_EXTENDED_DUTCFG
  252. set_lbmap(QIXIS_LBMAP_EMMC);
  253. #endif
  254. set_rcw_src(QIXIS_RCW_SRC_EMMC);
  255. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
  256. QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
  257. #else
  258. printf("Not implemented\n");
  259. #endif
  260. } else if (strcmp(argv[1], "sd_qspi") == 0) {
  261. #ifdef QIXIS_LBMAP_SD_QSPI
  262. QIXIS_WRITE(rst_ctl, 0x30);
  263. QIXIS_WRITE(rcfg_ctl, 0);
  264. set_lbmap(QIXIS_LBMAP_SD_QSPI);
  265. set_rcw_src(QIXIS_RCW_SRC_SD);
  266. qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
  267. QIXIS_RCFG_CTL_RECONFIG_IDLE);
  268. qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
  269. QIXIS_RCFG_CTL_RECONFIG_START);
  270. #else
  271. printf("Not implemented\n");
  272. #endif
  273. } else if (strcmp(argv[1], "qspi") == 0) {
  274. #ifdef QIXIS_LBMAP_QSPI
  275. QIXIS_WRITE(rst_ctl, 0x30);
  276. QIXIS_WRITE(rcfg_ctl, 0);
  277. set_lbmap(QIXIS_LBMAP_QSPI);
  278. set_rcw_src(QIXIS_RCW_SRC_QSPI);
  279. qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
  280. QIXIS_RCFG_CTL_RECONFIG_IDLE);
  281. qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
  282. QIXIS_RCFG_CTL_RECONFIG_START);
  283. #else
  284. printf("Not implemented\n");
  285. #endif
  286. } else if (strcmp(argv[1], "xspi") == 0) {
  287. #ifdef QIXIS_LBMAP_XSPI
  288. QIXIS_WRITE(rst_ctl, 0x30);
  289. QIXIS_WRITE(rcfg_ctl, 0);
  290. set_lbmap(QIXIS_LBMAP_XSPI);
  291. set_rcw_src(QIXIS_RCW_SRC_XSPI);
  292. qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
  293. QIXIS_RCFG_CTL_RECONFIG_IDLE);
  294. qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
  295. QIXIS_RCFG_CTL_RECONFIG_START);
  296. #else
  297. printf("Not implemented\n");
  298. #endif
  299. } else if (strcmp(argv[1], "watchdog") == 0) {
  300. static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
  301. "1min", "2min", "4min", "8min"};
  302. u8 rcfg = QIXIS_READ(rcfg_ctl);
  303. if (argv[2] == NULL) {
  304. printf("qixis watchdog <watchdog_period>\n");
  305. return 0;
  306. }
  307. for (i = 0; i < ARRAY_SIZE(period); i++) {
  308. if (strcmp(argv[2], period[i]) == 0) {
  309. /* disable watchdog */
  310. QIXIS_WRITE(rcfg_ctl,
  311. rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
  312. QIXIS_WRITE(watch, ((i<<2) - 1));
  313. QIXIS_WRITE(rcfg_ctl, rcfg);
  314. return 0;
  315. }
  316. }
  317. } else if (strcmp(argv[1], "dump") == 0) {
  318. qixis_dump_regs();
  319. return 0;
  320. } else if (strcmp(argv[1], "switch") == 0) {
  321. qixis_dump_switch();
  322. return 0;
  323. } else {
  324. printf("Invalid option: %s\n", argv[1]);
  325. return 1;
  326. }
  327. return 0;
  328. }
  329. U_BOOT_CMD(
  330. qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
  331. "Reset the board using the FPGA sequencer",
  332. "- hard reset to default bank\n"
  333. "qixis_reset altbank - reset to alternate bank\n"
  334. "qixis_reset nand - reset to nand\n"
  335. "qixis_reset sd - reset to sd\n"
  336. "qixis_reset sd_qspi - reset to sd with qspi support\n"
  337. "qixis_reset qspi - reset to qspi\n"
  338. "qixis watchdog <watchdog_period> - set the watchdog period\n"
  339. " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
  340. "qixis_reset dump - display the QIXIS registers\n"
  341. "qixis_reset emmc - reset to emmc\n"
  342. "qixis_reset switch - display switch\n"
  343. );
  344. #endif