fsl_i2c.h 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Freescale I2C Controller
  4. *
  5. * Copyright 2006 Freescale Semiconductor, Inc.
  6. *
  7. * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
  8. * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
  9. * and Jeff Brown.
  10. * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
  11. */
  12. #ifndef _ASM_FSL_I2C_H_
  13. #define _ASM_FSL_I2C_H_
  14. #include <asm/types.h>
  15. #include <linux/compiler.h>
  16. typedef struct fsl_i2c_base {
  17. u8 adr; /* I2C slave address */
  18. u8 res0[3];
  19. #define I2C_ADR 0xFE
  20. #define I2C_ADR_SHIFT 1
  21. #define I2C_ADR_RES ~(I2C_ADR)
  22. u8 fdr; /* I2C frequency divider register */
  23. u8 res1[3];
  24. #define IC2_FDR 0x3F
  25. #define IC2_FDR_SHIFT 0
  26. #define IC2_FDR_RES ~(IC2_FDR)
  27. u8 cr; /* I2C control redister */
  28. u8 res2[3];
  29. #define I2C_CR_MEN 0x80
  30. #define I2C_CR_MIEN 0x40
  31. #define I2C_CR_MSTA 0x20
  32. #define I2C_CR_MTX 0x10
  33. #define I2C_CR_TXAK 0x08
  34. #define I2C_CR_RSTA 0x04
  35. #define I2C_CR_BIT6 0x02 /* required for workaround A004447 */
  36. #define I2C_CR_BCST 0x01
  37. u8 sr; /* I2C status register */
  38. u8 res3[3];
  39. #define I2C_SR_MCF 0x80
  40. #define I2C_SR_MAAS 0x40
  41. #define I2C_SR_MBB 0x20
  42. #define I2C_SR_MAL 0x10
  43. #define I2C_SR_BCSTM 0x08
  44. #define I2C_SR_SRW 0x04
  45. #define I2C_SR_MIF 0x02
  46. #define I2C_SR_RXAK 0x01
  47. u8 dr; /* I2C data register */
  48. u8 res4[3];
  49. #define I2C_DR 0xFF
  50. #define I2C_DR_SHIFT 0
  51. #define I2C_DR_RES ~(I2C_DR)
  52. u8 dfsrr; /* I2C digital filter sampling rate register */
  53. u8 res5[3];
  54. #define I2C_DFSRR 0x3F
  55. #define I2C_DFSRR_SHIFT 0
  56. #define I2C_DFSRR_RES ~(I2C_DR)
  57. /* Fill out the reserved block */
  58. u8 res6[0xE8];
  59. } fsl_i2c_t;
  60. #if CONFIG_IS_ENABLED(DM_I2C)
  61. struct fsl_i2c_dev {
  62. struct fsl_i2c_base __iomem *base; /* register base */
  63. u32 i2c_clk;
  64. u32 index;
  65. u8 slaveadd;
  66. uint speed;
  67. };
  68. #endif
  69. #endif /* _ASM_I2C_H_ */