sunxi_de2.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Allwinner DE2 display driver
  4. *
  5. * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
  6. */
  7. #include <common.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <edid.h>
  11. #include <efi_loader.h>
  12. #include <fdtdec.h>
  13. #include <fdt_support.h>
  14. #include <log.h>
  15. #include <part.h>
  16. #include <video.h>
  17. #include <asm/global_data.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/display2.h>
  21. #include <dm/device-internal.h>
  22. #include <dm/uclass-internal.h>
  23. #include <linux/bitops.h>
  24. #include "simplefb_common.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. enum {
  27. /* Maximum LCD size we support */
  28. LCD_MAX_WIDTH = 3840,
  29. LCD_MAX_HEIGHT = 2160,
  30. LCD_MAX_LOG2_BPP = VIDEO_BPP32,
  31. };
  32. static void sunxi_de2_composer_init(void)
  33. {
  34. struct sunxi_ccm_reg * const ccm =
  35. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  36. #ifdef CONFIG_MACH_SUN50I
  37. u32 reg_value;
  38. /* set SRAM for video use (A64 only) */
  39. reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
  40. reg_value &= ~(0x01 << 24);
  41. writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
  42. #endif
  43. clock_set_pll10(432000000);
  44. /* Set DE parent to pll10 */
  45. clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
  46. CCM_DE2_CTRL_PLL10);
  47. /* Set ahb gating to pass */
  48. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
  49. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
  50. /* Clock on */
  51. setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
  52. }
  53. static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
  54. int bpp, ulong address, bool is_composite)
  55. {
  56. ulong de_mux_base = (mux == 0) ?
  57. SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
  58. struct de_clk * const de_clk_regs =
  59. (struct de_clk *)(SUNXI_DE2_BASE);
  60. struct de_glb * const de_glb_regs =
  61. (struct de_glb *)(de_mux_base +
  62. SUNXI_DE2_MUX_GLB_REGS);
  63. struct de_bld * const de_bld_regs =
  64. (struct de_bld *)(de_mux_base +
  65. SUNXI_DE2_MUX_BLD_REGS);
  66. struct de_ui * const de_ui_regs =
  67. (struct de_ui *)(de_mux_base +
  68. SUNXI_DE2_MUX_CHAN_REGS +
  69. SUNXI_DE2_MUX_CHAN_SZ * 1);
  70. struct de_csc * const de_csc_regs =
  71. (struct de_csc *)(de_mux_base +
  72. SUNXI_DE2_MUX_DCSC_REGS);
  73. u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
  74. int channel;
  75. u32 format;
  76. /* enable clock */
  77. #ifdef CONFIG_MACH_SUN8I_H3
  78. setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
  79. #else
  80. setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
  81. #endif
  82. setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
  83. setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
  84. clrbits_le32(&de_clk_regs->sel_cfg, 1);
  85. writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
  86. writel(0, &de_glb_regs->status);
  87. writel(1, &de_glb_regs->dbuff);
  88. writel(size, &de_glb_regs->size);
  89. for (channel = 0; channel < 4; channel++) {
  90. void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
  91. SUNXI_DE2_MUX_CHAN_SZ * channel);
  92. memset(ch, 0, (channel == 0) ?
  93. sizeof(struct de_vi) : sizeof(struct de_ui));
  94. }
  95. memset(de_bld_regs, 0, sizeof(struct de_bld));
  96. writel(0x00000101, &de_bld_regs->fcolor_ctl);
  97. writel(1, &de_bld_regs->route);
  98. writel(0, &de_bld_regs->premultiply);
  99. writel(0xff000000, &de_bld_regs->bkcolor);
  100. writel(0x03010301, &de_bld_regs->bld_mode[0]);
  101. writel(size, &de_bld_regs->output_size);
  102. writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
  103. &de_bld_regs->out_ctl);
  104. writel(0, &de_bld_regs->ck_ctl);
  105. writel(0xff000000, &de_bld_regs->attr[0].fcolor);
  106. writel(size, &de_bld_regs->attr[0].insize);
  107. /* Disable all other units */
  108. writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
  109. writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
  110. writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
  111. writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
  112. writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
  113. writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
  114. writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
  115. writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
  116. writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
  117. writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
  118. if (is_composite) {
  119. /* set CSC coefficients */
  120. writel(0x107, &de_csc_regs->coef11);
  121. writel(0x204, &de_csc_regs->coef12);
  122. writel(0x64, &de_csc_regs->coef13);
  123. writel(0x4200, &de_csc_regs->coef14);
  124. writel(0x1f68, &de_csc_regs->coef21);
  125. writel(0x1ed6, &de_csc_regs->coef22);
  126. writel(0x1c2, &de_csc_regs->coef23);
  127. writel(0x20200, &de_csc_regs->coef24);
  128. writel(0x1c2, &de_csc_regs->coef31);
  129. writel(0x1e87, &de_csc_regs->coef32);
  130. writel(0x1fb7, &de_csc_regs->coef33);
  131. writel(0x20200, &de_csc_regs->coef34);
  132. /* enable CSC unit */
  133. writel(1, &de_csc_regs->csc_ctl);
  134. } else {
  135. writel(0, &de_csc_regs->csc_ctl);
  136. }
  137. switch (bpp) {
  138. case 16:
  139. format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
  140. break;
  141. case 32:
  142. default:
  143. format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
  144. break;
  145. }
  146. writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
  147. writel(size, &de_ui_regs->cfg[0].size);
  148. writel(0, &de_ui_regs->cfg[0].coord);
  149. writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
  150. writel(address, &de_ui_regs->cfg[0].top_laddr);
  151. writel(size, &de_ui_regs->ovl_size);
  152. /* apply settings */
  153. writel(1, &de_glb_regs->dbuff);
  154. }
  155. static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
  156. enum video_log2_bpp l2bpp,
  157. struct udevice *disp, int mux, bool is_composite)
  158. {
  159. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  160. struct display_timing timing;
  161. struct display_plat *disp_uc_plat;
  162. int ret;
  163. disp_uc_plat = dev_get_uclass_plat(disp);
  164. debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
  165. if (display_in_use(disp)) {
  166. debug(" - device in use\n");
  167. return -EBUSY;
  168. }
  169. disp_uc_plat->source_id = mux;
  170. ret = device_probe(disp);
  171. if (ret) {
  172. debug("%s: device '%s' display won't probe (ret=%d)\n",
  173. __func__, dev->name, ret);
  174. return ret;
  175. }
  176. ret = display_read_timing(disp, &timing);
  177. if (ret) {
  178. debug("%s: Failed to read timings\n", __func__);
  179. return ret;
  180. }
  181. sunxi_de2_composer_init();
  182. sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
  183. ret = display_enable(disp, 1 << l2bpp, &timing);
  184. if (ret) {
  185. debug("%s: Failed to enable display\n", __func__);
  186. return ret;
  187. }
  188. uc_priv->xsize = timing.hactive.typ;
  189. uc_priv->ysize = timing.vactive.typ;
  190. uc_priv->bpix = l2bpp;
  191. debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
  192. #ifdef CONFIG_EFI_LOADER
  193. efi_add_memory_map(fbbase,
  194. timing.hactive.typ * timing.vactive.typ *
  195. (1 << l2bpp) / 8,
  196. EFI_RESERVED_MEMORY_TYPE);
  197. #endif
  198. return 0;
  199. }
  200. static int sunxi_de2_probe(struct udevice *dev)
  201. {
  202. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  203. struct udevice *disp;
  204. int ret;
  205. /* Before relocation we don't need to do anything */
  206. if (!(gd->flags & GD_FLG_RELOC))
  207. return 0;
  208. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  209. "sunxi_lcd", &disp);
  210. if (!ret) {
  211. int mux;
  212. mux = 0;
  213. ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
  214. false);
  215. if (!ret) {
  216. video_set_flush_dcache(dev, 1);
  217. return 0;
  218. }
  219. }
  220. debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
  221. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  222. "sunxi_dw_hdmi", &disp);
  223. if (!ret) {
  224. int mux;
  225. if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
  226. mux = 0;
  227. else
  228. mux = 1;
  229. ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
  230. false);
  231. if (!ret) {
  232. video_set_flush_dcache(dev, 1);
  233. return 0;
  234. }
  235. }
  236. debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
  237. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  238. "sunxi_tve", &disp);
  239. if (ret) {
  240. debug("%s: tv not found (ret=%d)\n", __func__, ret);
  241. return ret;
  242. }
  243. ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
  244. if (ret)
  245. return ret;
  246. video_set_flush_dcache(dev, 1);
  247. return 0;
  248. }
  249. static int sunxi_de2_bind(struct udevice *dev)
  250. {
  251. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  252. plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  253. (1 << LCD_MAX_LOG2_BPP) / 8;
  254. return 0;
  255. }
  256. static const struct video_ops sunxi_de2_ops = {
  257. };
  258. U_BOOT_DRIVER(sunxi_de2) = {
  259. .name = "sunxi_de2",
  260. .id = UCLASS_VIDEO,
  261. .ops = &sunxi_de2_ops,
  262. .bind = sunxi_de2_bind,
  263. .probe = sunxi_de2_probe,
  264. .flags = DM_FLAG_PRE_RELOC,
  265. };
  266. U_BOOT_DRVINFO(sunxi_de2) = {
  267. .name = "sunxi_de2"
  268. };
  269. /*
  270. * Simplefb support.
  271. */
  272. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
  273. int sunxi_simplefb_setup(void *blob)
  274. {
  275. struct udevice *de2, *hdmi, *lcd;
  276. struct video_priv *de2_priv;
  277. struct video_uc_plat *de2_plat;
  278. int mux;
  279. int offset, ret;
  280. u64 start, size;
  281. const char *pipeline = NULL;
  282. debug("Setting up simplefb\n");
  283. if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
  284. mux = 0;
  285. else
  286. mux = 1;
  287. /* Skip simplefb setting if DE2 / HDMI is not present */
  288. ret = uclass_find_device_by_name(UCLASS_VIDEO,
  289. "sunxi_de2", &de2);
  290. if (ret) {
  291. debug("DE2 not present\n");
  292. return 0;
  293. } else if (!device_active(de2)) {
  294. debug("DE2 present but not probed\n");
  295. return 0;
  296. }
  297. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  298. "sunxi_dw_hdmi", &hdmi);
  299. if (ret) {
  300. debug("HDMI not present\n");
  301. } else if (device_active(hdmi)) {
  302. if (mux == 0)
  303. pipeline = "mixer0-lcd0-hdmi";
  304. else
  305. pipeline = "mixer1-lcd1-hdmi";
  306. } else {
  307. debug("HDMI present but not probed\n");
  308. }
  309. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  310. "sunxi_lcd", &lcd);
  311. if (ret)
  312. debug("LCD not present\n");
  313. else if (device_active(lcd))
  314. pipeline = "mixer0-lcd0";
  315. else
  316. debug("LCD present but not probed\n");
  317. if (!pipeline) {
  318. debug("No active display present\n");
  319. return 0;
  320. }
  321. de2_priv = dev_get_uclass_priv(de2);
  322. de2_plat = dev_get_uclass_plat(de2);
  323. offset = sunxi_simplefb_fdt_match(blob, pipeline);
  324. if (offset < 0) {
  325. eprintf("Cannot setup simplefb: node not found\n");
  326. return 0; /* Keep older kernels working */
  327. }
  328. start = gd->bd->bi_dram[0].start;
  329. size = de2_plat->base - start;
  330. ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
  331. if (ret) {
  332. eprintf("Cannot setup simplefb: Error reserving memory\n");
  333. return ret;
  334. }
  335. ret = fdt_setup_simplefb_node(blob, offset, de2_plat->base,
  336. de2_priv->xsize, de2_priv->ysize,
  337. VNBYTES(de2_priv->bpix) * de2_priv->xsize,
  338. "x8r8g8b8");
  339. if (ret)
  340. eprintf("Cannot setup simplefb: Error setting properties\n");
  341. return ret;
  342. }
  343. #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */