colibri_imx6.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  5. * Copyright (C) 2014-2019, Toradex AG
  6. * copied from nitrogen6x
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <env.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <asm/arch/imx-regs.h>
  19. #include <asm/arch/mx6-ddr.h>
  20. #include <asm/arch/mx6-pins.h>
  21. #include <asm/arch/mxc_hdmi.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/bootm.h>
  24. #include <asm/gpio.h>
  25. #include <asm/mach-imx/boot_mode.h>
  26. #include <asm/mach-imx/iomux-v3.h>
  27. #include <asm/mach-imx/sata.h>
  28. #include <asm/mach-imx/video.h>
  29. #include <cpu.h>
  30. #include <dm/platform_data/serial_mxc.h>
  31. #include <fsl_esdhc_imx.h>
  32. #include <imx_thermal.h>
  33. #include <miiphy.h>
  34. #include <netdev.h>
  35. #include <cpu.h>
  36. #include "../common/tdx-cfg-block.h"
  37. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  38. #include "pf0100.h"
  39. #endif
  40. DECLARE_GLOBAL_DATA_PTR;
  41. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  42. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  43. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  44. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  45. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
  46. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  47. #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  48. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  49. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  50. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  51. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  52. PAD_CTL_SRE_SLOW)
  53. #define NO_PULLUP ( \
  54. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  55. PAD_CTL_SRE_SLOW)
  56. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  57. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  58. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  59. #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  60. int dram_init(void)
  61. {
  62. /* use the DDR controllers configured size */
  63. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  64. (ulong)imx_ddr_size());
  65. return 0;
  66. }
  67. /* Colibri UARTA */
  68. iomux_v3_cfg_t const uart1_pads[] = {
  69. MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  70. MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  71. };
  72. #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  73. /* Colibri MMC */
  74. iomux_v3_cfg_t const usdhc1_pads[] = {
  75. MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76. MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77. MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78. MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80. MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81. MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  82. # define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  83. };
  84. /* eMMC */
  85. iomux_v3_cfg_t const usdhc3_pads[] = {
  86. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  87. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  88. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  89. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  90. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  91. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  92. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  93. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  94. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  95. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  96. MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97. };
  98. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  99. /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
  100. iomux_v3_cfg_t const gpio_pads[] = {
  101. /* ADDRESS[17:18] [25] used as GPIO */
  102. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  103. MUX_MODE_SION,
  104. MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
  105. MUX_MODE_SION,
  106. MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
  107. MUX_MODE_SION,
  108. /* ADDRESS[19:24] used as GPIO */
  109. MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
  110. MUX_MODE_SION,
  111. MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
  112. MUX_MODE_SION,
  113. MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
  114. MUX_MODE_SION,
  115. MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
  116. MUX_MODE_SION,
  117. MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
  118. MUX_MODE_SION,
  119. MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
  120. MUX_MODE_SION,
  121. /* DATA[16:29] [31] used as GPIO */
  122. MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
  123. MUX_MODE_SION,
  124. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
  125. MUX_MODE_SION,
  126. MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
  127. MUX_MODE_SION,
  128. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
  129. MUX_MODE_SION,
  130. MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
  131. MUX_MODE_SION,
  132. MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
  133. MUX_MODE_SION,
  134. MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
  135. MUX_MODE_SION,
  136. MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  137. MUX_MODE_SION,
  138. MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
  139. MUX_MODE_SION,
  140. MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
  141. MUX_MODE_SION,
  142. MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
  143. MUX_MODE_SION,
  144. MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
  145. MUX_MODE_SION,
  146. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  147. MUX_MODE_SION,
  148. MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
  149. MUX_MODE_SION,
  150. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
  151. MUX_MODE_SION,
  152. /* DQM[0:3] used as GPIO */
  153. MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
  154. MUX_MODE_SION,
  155. MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
  156. MUX_MODE_SION,
  157. MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
  158. MUX_MODE_SION,
  159. MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
  160. MUX_MODE_SION,
  161. /* RDY used as GPIO */
  162. MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
  163. MUX_MODE_SION,
  164. /* ADDRESS[16] DATA[30] used as GPIO */
  165. MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
  166. MUX_MODE_SION,
  167. MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
  168. MUX_MODE_SION,
  169. /* CSI pins used as GPIO */
  170. MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  171. MUX_MODE_SION,
  172. MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  173. MUX_MODE_SION,
  174. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
  175. MUX_MODE_SION,
  176. MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
  177. MUX_MODE_SION,
  178. MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
  179. MUX_MODE_SION,
  180. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
  181. MUX_MODE_SION,
  182. MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  183. MUX_MODE_SION,
  184. MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
  185. MUX_MODE_SION,
  186. MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
  187. MUX_MODE_SION,
  188. MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
  189. MUX_MODE_SION,
  190. MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
  191. MUX_MODE_SION,
  192. MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
  193. MUX_MODE_SION,
  194. MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
  195. MUX_MODE_SION,
  196. /* GPIO */
  197. MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
  198. MUX_MODE_SION,
  199. MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
  200. MUX_MODE_SION,
  201. MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  202. MUX_MODE_SION,
  203. MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
  204. MUX_MODE_SION,
  205. MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
  206. MUX_MODE_SION,
  207. MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
  208. MUX_MODE_SION,
  209. MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  210. MUX_MODE_SION,
  211. MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  212. MUX_MODE_SION,
  213. MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
  214. MUX_MODE_SION,
  215. MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
  216. MUX_MODE_SION,
  217. MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
  218. MUX_MODE_SION,
  219. /* USBH_OC */
  220. MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
  221. /* USBC_ID */
  222. MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
  223. /* USBC_DET */
  224. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
  225. };
  226. static void setup_iomux_gpio(void)
  227. {
  228. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  229. }
  230. iomux_v3_cfg_t const usb_pads[] = {
  231. /* USBH_PEN */
  232. MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  233. # define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
  234. };
  235. /*
  236. * UARTs are used in DTE mode, switch the mode on all UARTs before
  237. * any pinmuxing connects a (DCE) output to a transceiver output.
  238. */
  239. #define UCR3 0x88 /* FIFO Control Register */
  240. #define UCR3_RI BIT(8) /* RIDELT DTE mode */
  241. #define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
  242. #define UFCR 0x90 /* FIFO Control Register */
  243. #define UFCR_DCEDTE BIT(6) /* DCE=0 */
  244. static void setup_dtemode_uart(void)
  245. {
  246. setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
  247. setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
  248. setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
  249. clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
  250. clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
  251. clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
  252. }
  253. static void setup_iomux_uart(void)
  254. {
  255. setup_dtemode_uart();
  256. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  257. }
  258. #ifdef CONFIG_USB_EHCI_MX6
  259. int board_ehci_hcd_init(int port)
  260. {
  261. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  262. return 0;
  263. }
  264. #endif
  265. #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  266. /* use the following sequence: eMMC, MMC */
  267. struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
  268. {USDHC3_BASE_ADDR},
  269. {USDHC1_BASE_ADDR},
  270. };
  271. int board_mmc_getcd(struct mmc *mmc)
  272. {
  273. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  274. int ret = true; /* default: assume inserted */
  275. switch (cfg->esdhc_base) {
  276. case USDHC1_BASE_ADDR:
  277. gpio_request(GPIO_MMC_CD, "MMC_CD");
  278. gpio_direction_input(GPIO_MMC_CD);
  279. ret = !gpio_get_value(GPIO_MMC_CD);
  280. break;
  281. }
  282. return ret;
  283. }
  284. int board_mmc_init(struct bd_info *bis)
  285. {
  286. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  287. unsigned reg = readl(&psrc->sbmr1) >> 11;
  288. /*
  289. * Upon reading BOOT_CFG register the following map is done:
  290. * Bit 11 and 12 of BOOT_CFG register can determine the current
  291. * mmc port
  292. * 0x1 SD1
  293. * 0x2 SD2
  294. * 0x3 SD4
  295. */
  296. switch (reg & 0x3) {
  297. case 0x0:
  298. imx_iomux_v3_setup_multiple_pads(
  299. usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  300. usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
  301. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  302. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  303. break;
  304. case 0x2:
  305. imx_iomux_v3_setup_multiple_pads(
  306. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  307. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  308. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  309. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  310. break;
  311. default:
  312. puts("MMC boot device not available");
  313. }
  314. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  315. }
  316. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  317. int board_phy_config(struct phy_device *phydev)
  318. {
  319. if (phydev->drv->config)
  320. phydev->drv->config(phydev);
  321. return 0;
  322. }
  323. int setup_fec(void)
  324. {
  325. int ret;
  326. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  327. /* provide the PHY clock from the i.MX 6 */
  328. ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  329. if (ret)
  330. return ret;
  331. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  332. return 0;
  333. }
  334. static iomux_v3_cfg_t const pwr_intb_pads[] = {
  335. /*
  336. * the bootrom sets the iomux to vselect, potentially connecting
  337. * two outputs. Set this back to GPIO
  338. */
  339. MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
  340. };
  341. #if defined(CONFIG_VIDEO_IPUV3)
  342. static iomux_v3_cfg_t const backlight_pads[] = {
  343. /* Backlight On */
  344. MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  345. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
  346. /* Backlight PWM, used as GPIO in U-Boot */
  347. MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
  348. MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  349. MUX_MODE_SION,
  350. #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
  351. };
  352. static iomux_v3_cfg_t const rgb_pads[] = {
  353. MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
  354. MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
  355. MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
  356. MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
  357. MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
  358. MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
  359. MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
  360. MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
  361. MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
  362. MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
  363. MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
  364. MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
  365. MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
  366. MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
  367. MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
  368. MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
  369. MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
  370. MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
  371. MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
  372. MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
  373. MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
  374. MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
  375. };
  376. static void do_enable_hdmi(struct display_info_t const *dev)
  377. {
  378. imx_enable_hdmi_phy();
  379. }
  380. static void enable_rgb(struct display_info_t const *dev)
  381. {
  382. imx_iomux_v3_setup_multiple_pads(
  383. rgb_pads,
  384. ARRAY_SIZE(rgb_pads));
  385. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  386. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  387. }
  388. static int detect_default(struct display_info_t const *dev)
  389. {
  390. (void) dev;
  391. return 1;
  392. }
  393. struct display_info_t const displays[] = {{
  394. .bus = -1,
  395. .addr = 0,
  396. .pixfmt = IPU_PIX_FMT_RGB24,
  397. .detect = detect_hdmi,
  398. .enable = do_enable_hdmi,
  399. .mode = {
  400. .name = "HDMI",
  401. .refresh = 60,
  402. .xres = 1024,
  403. .yres = 768,
  404. .pixclock = 15385,
  405. .left_margin = 220,
  406. .right_margin = 40,
  407. .upper_margin = 21,
  408. .lower_margin = 7,
  409. .hsync_len = 60,
  410. .vsync_len = 10,
  411. .sync = FB_SYNC_EXT,
  412. .vmode = FB_VMODE_NONINTERLACED
  413. } }, {
  414. .bus = -1,
  415. .addr = 0,
  416. .pixfmt = IPU_PIX_FMT_RGB666,
  417. .detect = detect_default,
  418. .enable = enable_rgb,
  419. .mode = {
  420. .name = "vga-rgb",
  421. .refresh = 60,
  422. .xres = 640,
  423. .yres = 480,
  424. .pixclock = 33000,
  425. .left_margin = 48,
  426. .right_margin = 16,
  427. .upper_margin = 31,
  428. .lower_margin = 11,
  429. .hsync_len = 96,
  430. .vsync_len = 2,
  431. .sync = 0,
  432. .vmode = FB_VMODE_NONINTERLACED
  433. } }, {
  434. .bus = -1,
  435. .addr = 0,
  436. .pixfmt = IPU_PIX_FMT_RGB666,
  437. .enable = enable_rgb,
  438. .mode = {
  439. .name = "wvga-rgb",
  440. .refresh = 60,
  441. .xres = 800,
  442. .yres = 480,
  443. .pixclock = 25000,
  444. .left_margin = 40,
  445. .right_margin = 88,
  446. .upper_margin = 33,
  447. .lower_margin = 10,
  448. .hsync_len = 128,
  449. .vsync_len = 2,
  450. .sync = 0,
  451. .vmode = FB_VMODE_NONINTERLACED
  452. } } };
  453. size_t display_count = ARRAY_SIZE(displays);
  454. static void setup_display(void)
  455. {
  456. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  457. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  458. int reg;
  459. enable_ipu_clock();
  460. imx_setup_hdmi();
  461. /* Turn on LDB0,IPU,IPU DI0 clocks */
  462. reg = __raw_readl(&mxc_ccm->CCGR3);
  463. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  464. writel(reg, &mxc_ccm->CCGR3);
  465. /* set LDB0, LDB1 clk select to 011/011 */
  466. reg = readl(&mxc_ccm->cs2cdr);
  467. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  468. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  469. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  470. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  471. writel(reg, &mxc_ccm->cs2cdr);
  472. reg = readl(&mxc_ccm->cscmr2);
  473. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  474. writel(reg, &mxc_ccm->cscmr2);
  475. reg = readl(&mxc_ccm->chsccdr);
  476. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  477. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  478. writel(reg, &mxc_ccm->chsccdr);
  479. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  480. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  481. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  482. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  483. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  484. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  485. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  486. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  487. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  488. writel(reg, &iomux->gpr[2]);
  489. reg = readl(&iomux->gpr[3]);
  490. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  491. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  492. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  493. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  494. writel(reg, &iomux->gpr[3]);
  495. /* backlight unconditionally on for now */
  496. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  497. ARRAY_SIZE(backlight_pads));
  498. /* use 0 for EDT 7", use 1 for LG fullHD panel */
  499. gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
  500. gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
  501. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  502. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  503. }
  504. /*
  505. * Backlight off before OS handover
  506. */
  507. void board_preboot_os(void)
  508. {
  509. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
  510. gpio_direction_output(RGB_BACKLIGHT_GP, 0);
  511. }
  512. #endif /* defined(CONFIG_VIDEO_IPUV3) */
  513. int board_early_init_f(void)
  514. {
  515. imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
  516. ARRAY_SIZE(pwr_intb_pads));
  517. setup_iomux_uart();
  518. return 0;
  519. }
  520. /*
  521. * Do not overwrite the console
  522. * Use always serial for U-Boot console
  523. */
  524. int overwrite_console(void)
  525. {
  526. return 1;
  527. }
  528. int board_init(void)
  529. {
  530. /* address of boot parameters */
  531. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  532. #if defined(CONFIG_FEC_MXC)
  533. setup_fec();
  534. #endif
  535. #if defined(CONFIG_VIDEO_IPUV3)
  536. setup_display();
  537. #endif
  538. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  539. (void) pmic_init();
  540. #endif
  541. #ifdef CONFIG_SATA
  542. setup_sata();
  543. #endif
  544. setup_iomux_gpio();
  545. return 0;
  546. }
  547. #ifdef CONFIG_BOARD_LATE_INIT
  548. int board_late_init(void)
  549. {
  550. #if defined(CONFIG_REVISION_TAG) && \
  551. defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
  552. char env_str[256];
  553. u32 rev;
  554. rev = get_board_rev();
  555. snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
  556. env_set("board_rev", env_str);
  557. #endif
  558. #ifdef CONFIG_CMD_USB_SDP
  559. if (is_boot_from_usb()) {
  560. printf("Serial Downloader recovery mode, using sdp command\n");
  561. env_set("bootdelay", "0");
  562. env_set("bootcmd", "sdp 0");
  563. }
  564. #endif /* CONFIG_CMD_USB_SDP */
  565. return 0;
  566. }
  567. #endif /* CONFIG_BOARD_LATE_INIT */
  568. int checkboard(void)
  569. {
  570. char it[] = " IT";
  571. int minc, maxc;
  572. switch (get_cpu_temp_grade(&minc, &maxc)) {
  573. case TEMP_AUTOMOTIVE:
  574. case TEMP_INDUSTRIAL:
  575. break;
  576. case TEMP_EXTCOMMERCIAL:
  577. default:
  578. it[0] = 0;
  579. };
  580. printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
  581. is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
  582. (gd->ram_size == 0x20000000) ? "512" : "256", it);
  583. return 0;
  584. }
  585. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  586. int ft_board_setup(void *blob, struct bd_info *bd)
  587. {
  588. u32 cma_size;
  589. ft_common_board_setup(blob, bd);
  590. cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
  591. cma_size = min((u32)(gd->ram_size >> 1), cma_size);
  592. fdt_setprop_u32(blob,
  593. fdt_path_offset(blob, "/reserved-memory/linux,cma"),
  594. "size",
  595. cma_size);
  596. return 0;
  597. }
  598. #endif
  599. #ifdef CONFIG_CMD_BMODE
  600. static const struct boot_mode board_boot_modes[] = {
  601. {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  602. {NULL, 0},
  603. };
  604. #endif
  605. int misc_init_r(void)
  606. {
  607. #ifdef CONFIG_CMD_BMODE
  608. add_board_boot_modes(board_boot_modes);
  609. #endif
  610. return 0;
  611. }
  612. #ifdef CONFIG_LDO_BYPASS_CHECK
  613. /* TODO, use external pmic, for now always ldo_enable */
  614. void ldo_mode_set(int ldo_bypass)
  615. {
  616. return;
  617. }
  618. #endif
  619. #ifdef CONFIG_SPL_BUILD
  620. #include <spl.h>
  621. #include <linux/libfdt.h>
  622. #include "asm/arch/mx6dl-ddr.h"
  623. #include "asm/arch/iomux.h"
  624. #include "asm/arch/crm_regs.h"
  625. static int mx6s_dcd_table[] = {
  626. /* ddr-setup.cfg */
  627. MX6_IOM_DRAM_SDQS0, 0x00000030,
  628. MX6_IOM_DRAM_SDQS1, 0x00000030,
  629. MX6_IOM_DRAM_SDQS2, 0x00000030,
  630. MX6_IOM_DRAM_SDQS3, 0x00000030,
  631. MX6_IOM_DRAM_SDQS4, 0x00000030,
  632. MX6_IOM_DRAM_SDQS5, 0x00000030,
  633. MX6_IOM_DRAM_SDQS6, 0x00000030,
  634. MX6_IOM_DRAM_SDQS7, 0x00000030,
  635. MX6_IOM_GRP_B0DS, 0x00000030,
  636. MX6_IOM_GRP_B1DS, 0x00000030,
  637. MX6_IOM_GRP_B2DS, 0x00000030,
  638. MX6_IOM_GRP_B3DS, 0x00000030,
  639. MX6_IOM_GRP_B4DS, 0x00000030,
  640. MX6_IOM_GRP_B5DS, 0x00000030,
  641. MX6_IOM_GRP_B6DS, 0x00000030,
  642. MX6_IOM_GRP_B7DS, 0x00000030,
  643. MX6_IOM_GRP_ADDDS, 0x00000030,
  644. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  645. MX6_IOM_GRP_CTLDS, 0x00000030,
  646. MX6_IOM_DRAM_DQM0, 0x00020030,
  647. MX6_IOM_DRAM_DQM1, 0x00020030,
  648. MX6_IOM_DRAM_DQM2, 0x00020030,
  649. MX6_IOM_DRAM_DQM3, 0x00020030,
  650. MX6_IOM_DRAM_DQM4, 0x00020030,
  651. MX6_IOM_DRAM_DQM5, 0x00020030,
  652. MX6_IOM_DRAM_DQM6, 0x00020030,
  653. MX6_IOM_DRAM_DQM7, 0x00020030,
  654. MX6_IOM_DRAM_CAS, 0x00020030,
  655. MX6_IOM_DRAM_RAS, 0x00020030,
  656. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  657. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  658. MX6_IOM_DRAM_RESET, 0x00020030,
  659. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  660. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  661. MX6_IOM_DRAM_SDODT0, 0x00003030,
  662. MX6_IOM_DRAM_SDODT1, 0x00003030,
  663. /* (differential input) */
  664. MX6_IOM_DDRMODE_CTL, 0x00020000,
  665. /* (differential input) */
  666. MX6_IOM_GRP_DDRMODE, 0x00020000,
  667. /* disable ddr pullups */
  668. MX6_IOM_GRP_DDRPKE, 0x00000000,
  669. MX6_IOM_DRAM_SDBA2, 0x00000000,
  670. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  671. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  672. /* Read data DQ Byte0-3 delay */
  673. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  674. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  675. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  676. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  677. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  678. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  679. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  680. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  681. /*
  682. * MDMISC mirroring interleaved (row/bank/col)
  683. */
  684. /* TODO: check what the RALAT field does */
  685. MX6_MMDC_P0_MDMISC, 0x00081740,
  686. /*
  687. * MDSCR con_req
  688. */
  689. MX6_MMDC_P0_MDSCR, 0x00008000,
  690. /* 800mhz_2x64mx16.cfg */
  691. MX6_MMDC_P0_MDPDC, 0x0002002D,
  692. MX6_MMDC_P0_MDCFG0, 0x2C305503,
  693. MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
  694. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  695. MX6_MMDC_P0_MDRWD, 0x000026D2,
  696. MX6_MMDC_P0_MDOR, 0x00301023,
  697. MX6_MMDC_P0_MDOTC, 0x00333030,
  698. MX6_MMDC_P0_MDPDC, 0x0002556D,
  699. /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
  700. MX6_MMDC_P0_MDASP, 0x00000017,
  701. /* DDR3 DATA BUS SIZE: 64BIT */
  702. /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
  703. /* DDR3 DATA BUS SIZE: 32BIT */
  704. MX6_MMDC_P0_MDCTL, 0x82190000,
  705. /* Write commands to DDR */
  706. /* Load Mode Registers */
  707. /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
  708. /* MX6_MMDC_P0_MDSCR, 0x04408032, */
  709. MX6_MMDC_P0_MDSCR, 0x04008032,
  710. MX6_MMDC_P0_MDSCR, 0x00008033,
  711. MX6_MMDC_P0_MDSCR, 0x00048031,
  712. MX6_MMDC_P0_MDSCR, 0x13208030,
  713. /* ZQ calibration */
  714. MX6_MMDC_P0_MDSCR, 0x04008040,
  715. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  716. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  717. MX6_MMDC_P0_MDREF, 0x00005800,
  718. MX6_MMDC_P0_MPODTCTRL, 0x00000000,
  719. MX6_MMDC_P1_MPODTCTRL, 0x00000000,
  720. MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
  721. MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
  722. MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
  723. MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
  724. MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
  725. MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
  726. MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
  727. MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
  728. MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
  729. MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
  730. MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
  731. MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
  732. MX6_MMDC_P0_MPMUR0, 0x00000800,
  733. MX6_MMDC_P1_MPMUR0, 0x00000800,
  734. MX6_MMDC_P0_MDSCR, 0x00000000,
  735. MX6_MMDC_P0_MAPSR, 0x00011006,
  736. };
  737. static int mx6dl_dcd_table[] = {
  738. /* ddr-setup.cfg */
  739. MX6_IOM_DRAM_SDQS0, 0x00000030,
  740. MX6_IOM_DRAM_SDQS1, 0x00000030,
  741. MX6_IOM_DRAM_SDQS2, 0x00000030,
  742. MX6_IOM_DRAM_SDQS3, 0x00000030,
  743. MX6_IOM_DRAM_SDQS4, 0x00000030,
  744. MX6_IOM_DRAM_SDQS5, 0x00000030,
  745. MX6_IOM_DRAM_SDQS6, 0x00000030,
  746. MX6_IOM_DRAM_SDQS7, 0x00000030,
  747. MX6_IOM_GRP_B0DS, 0x00000030,
  748. MX6_IOM_GRP_B1DS, 0x00000030,
  749. MX6_IOM_GRP_B2DS, 0x00000030,
  750. MX6_IOM_GRP_B3DS, 0x00000030,
  751. MX6_IOM_GRP_B4DS, 0x00000030,
  752. MX6_IOM_GRP_B5DS, 0x00000030,
  753. MX6_IOM_GRP_B6DS, 0x00000030,
  754. MX6_IOM_GRP_B7DS, 0x00000030,
  755. MX6_IOM_GRP_ADDDS, 0x00000030,
  756. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  757. MX6_IOM_GRP_CTLDS, 0x00000030,
  758. MX6_IOM_DRAM_DQM0, 0x00020030,
  759. MX6_IOM_DRAM_DQM1, 0x00020030,
  760. MX6_IOM_DRAM_DQM2, 0x00020030,
  761. MX6_IOM_DRAM_DQM3, 0x00020030,
  762. MX6_IOM_DRAM_DQM4, 0x00020030,
  763. MX6_IOM_DRAM_DQM5, 0x00020030,
  764. MX6_IOM_DRAM_DQM6, 0x00020030,
  765. MX6_IOM_DRAM_DQM7, 0x00020030,
  766. MX6_IOM_DRAM_CAS, 0x00020030,
  767. MX6_IOM_DRAM_RAS, 0x00020030,
  768. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  769. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  770. MX6_IOM_DRAM_RESET, 0x00020030,
  771. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  772. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  773. MX6_IOM_DRAM_SDODT0, 0x00003030,
  774. MX6_IOM_DRAM_SDODT1, 0x00003030,
  775. /* (differential input) */
  776. MX6_IOM_DDRMODE_CTL, 0x00020000,
  777. /* (differential input) */
  778. MX6_IOM_GRP_DDRMODE, 0x00020000,
  779. /* disable ddr pullups */
  780. MX6_IOM_GRP_DDRPKE, 0x00000000,
  781. MX6_IOM_DRAM_SDBA2, 0x00000000,
  782. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  783. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  784. /* Read data DQ Byte0-3 delay */
  785. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  786. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  787. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  788. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  789. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  790. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  791. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  792. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  793. /*
  794. * MDMISC mirroring interleaved (row/bank/col)
  795. */
  796. /* TODO: check what the RALAT field does */
  797. MX6_MMDC_P0_MDMISC, 0x00081740,
  798. /*
  799. * MDSCR con_req
  800. */
  801. MX6_MMDC_P0_MDSCR, 0x00008000,
  802. /* 800mhz_2x64mx16.cfg */
  803. MX6_MMDC_P0_MDPDC, 0x0002002D,
  804. MX6_MMDC_P0_MDCFG0, 0x2C305503,
  805. MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
  806. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  807. MX6_MMDC_P0_MDRWD, 0x000026D2,
  808. MX6_MMDC_P0_MDOR, 0x00301023,
  809. MX6_MMDC_P0_MDOTC, 0x00333030,
  810. MX6_MMDC_P0_MDPDC, 0x0002556D,
  811. /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
  812. MX6_MMDC_P0_MDASP, 0x00000017,
  813. /* DDR3 DATA BUS SIZE: 64BIT */
  814. MX6_MMDC_P0_MDCTL, 0x821A0000,
  815. /* DDR3 DATA BUS SIZE: 32BIT */
  816. /* MX6_MMDC_P0_MDCTL, 0x82190000, */
  817. /* Write commands to DDR */
  818. /* Load Mode Registers */
  819. /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
  820. /* MX6_MMDC_P0_MDSCR, 0x04408032, */
  821. MX6_MMDC_P0_MDSCR, 0x04008032,
  822. MX6_MMDC_P0_MDSCR, 0x00008033,
  823. MX6_MMDC_P0_MDSCR, 0x00048031,
  824. MX6_MMDC_P0_MDSCR, 0x13208030,
  825. /* ZQ calibration */
  826. MX6_MMDC_P0_MDSCR, 0x04008040,
  827. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  828. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  829. MX6_MMDC_P0_MDREF, 0x00005800,
  830. MX6_MMDC_P0_MPODTCTRL, 0x00000000,
  831. MX6_MMDC_P1_MPODTCTRL, 0x00000000,
  832. MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
  833. MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
  834. MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
  835. MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
  836. MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
  837. MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
  838. MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
  839. MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
  840. MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
  841. MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
  842. MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
  843. MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
  844. MX6_MMDC_P0_MPMUR0, 0x00000800,
  845. MX6_MMDC_P1_MPMUR0, 0x00000800,
  846. MX6_MMDC_P0_MDSCR, 0x00000000,
  847. MX6_MMDC_P0_MAPSR, 0x00011006,
  848. };
  849. static void ccgr_init(void)
  850. {
  851. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  852. writel(0x00C03F3F, &ccm->CCGR0);
  853. writel(0x0030FC03, &ccm->CCGR1);
  854. writel(0x0FFFFFF3, &ccm->CCGR2);
  855. writel(0x3FF0300F, &ccm->CCGR3);
  856. writel(0x00FFF300, &ccm->CCGR4);
  857. writel(0x0F0000F3, &ccm->CCGR5);
  858. writel(0x000003FF, &ccm->CCGR6);
  859. /*
  860. * Setup CCM_CCOSR register as follows:
  861. *
  862. * cko1_en = 1 --> CKO1 enabled
  863. * cko1_div = 111 --> divide by 8
  864. * cko1_sel = 1011 --> ahb_clk_root
  865. *
  866. * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
  867. */
  868. writel(0x000000FB, &ccm->ccosr);
  869. }
  870. static void ddr_init(int *table, int size)
  871. {
  872. int i;
  873. for (i = 0; i < size / 2 ; i++)
  874. writel(table[2 * i + 1], table[2 * i]);
  875. }
  876. static void spl_dram_init(void)
  877. {
  878. int minc, maxc;
  879. switch (get_cpu_temp_grade(&minc, &maxc)) {
  880. case TEMP_COMMERCIAL:
  881. case TEMP_EXTCOMMERCIAL:
  882. if (is_cpu_type(MXC_CPU_MX6DL)) {
  883. puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
  884. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  885. } else {
  886. puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
  887. ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
  888. }
  889. break;
  890. case TEMP_INDUSTRIAL:
  891. case TEMP_AUTOMOTIVE:
  892. default:
  893. if (is_cpu_type(MXC_CPU_MX6DL)) {
  894. puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
  895. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  896. } else {
  897. puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
  898. ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
  899. }
  900. break;
  901. };
  902. udelay(100);
  903. }
  904. static iomux_v3_cfg_t const gpio_reset_pad[] = {
  905. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  906. MUX_MODE_SION
  907. #define GPIO_NRESET IMX_GPIO_NR(6, 27)
  908. };
  909. #define IMX_RESET_CAUSE_POR 0x00011
  910. static void nreset_out(void)
  911. {
  912. int reset_cause = get_imx_reset_cause();
  913. if (reset_cause != IMX_RESET_CAUSE_POR) {
  914. imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
  915. ARRAY_SIZE(gpio_reset_pad));
  916. gpio_direction_output(GPIO_NRESET, 1);
  917. udelay(100);
  918. gpio_direction_output(GPIO_NRESET, 0);
  919. }
  920. }
  921. void board_init_f(ulong dummy)
  922. {
  923. /* setup AIPS and disable watchdog */
  924. arch_cpu_init();
  925. ccgr_init();
  926. gpr_init();
  927. /* iomux */
  928. board_early_init_f();
  929. /* setup GP timer */
  930. timer_init();
  931. /* UART clocks enabled and gd valid - init serial console */
  932. preloader_console_init();
  933. /* Make sure we use dte mode */
  934. setup_dtemode_uart();
  935. /* DDR initialization */
  936. spl_dram_init();
  937. /* Clear the BSS. */
  938. memset(__bss_start, 0, __bss_end - __bss_start);
  939. /* Assert nReset_Out */
  940. nreset_out();
  941. /* load/boot image from boot device */
  942. board_init_r(NULL, 0);
  943. }
  944. void reset_cpu(ulong addr)
  945. {
  946. }
  947. #endif /* CONFIG_SPL_BUILD */
  948. static struct mxc_serial_plat mxc_serial_plat = {
  949. .reg = (struct mxc_uart *)UART1_BASE,
  950. .use_dte = true,
  951. };
  952. U_BOOT_DRVINFO(mxc_serial) = {
  953. .name = "serial_mxc",
  954. .plat = &mxc_serial_plat,
  955. };